SN74LVC1G74 SCES794B – SEPTEMBER 2009 – REVISED FEBRUARY 2012 www.ti.com SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET Check for Samples: SN74LVC1G74 FEATURES 1 • 2 • • • • • • • Available in the Texas Instruments NanoFree™ Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 5.9 ns at 3.3 V Low Power Consumption, 10-μA Max ICC ±24-mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C DCT PACKAGE (TOP VIEW) • Ioff Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) • • DCU PACKAGE (TOP VIEW) CLK 1 8 VCC D 2 7 PRE Q 3 6 CLR GND 4 5 Q CLK D Q GND 1 8 2 7 3 6 4 5 YZP PACKAGE (TOP VIEW) VCC PRE CLR Q CLK D Q GND A1 1 8 A2 B1 2 7 B2 C1 3 6 C2 D1 45 D2 VCC PRE CLR Q See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2012, Texas Instruments Incorporated SN74LVC1G74 SCES794B – SEPTEMBER 2009 – REVISED FEBRUARY 2012 www.ti.com ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C –40°C to 125°C ORDERABLE PART NUMBER (2) NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) Reel of 3000 SN74LVC1G74YZPR _ _ _DP_ SSOP – DCT Reel of 3000 SN74LVC1G74DCTR N74_ _ _ SN74LVC1G74DCUR Reel of 3000 VSSOP – DCU SN74LVC1G74DCURG4 Reel of 250 (1) (2) (3) TOP-SIDE MARKING (3) N74_ SN74LVC1G74DCUT For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the wafer fab/assembly site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE INPUTS (1) OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H (1) H (1) H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. LOGIC DIAGRAM (POSITIVE LOGIC) PRE CLK 7 1 C C C 5 Q TG C C C C D 2 TG TG TG 3 C CLR 2 Q C C 6 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G74 SN74LVC1G74 SCES794B – SEPTEMBER 2009 – REVISED FEBRUARY 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V VO Voltage range applied to any output in the high or low state (2) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA (3) Continuous current through VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range DCT package 220 DCU package 227 YZP package (1) (2) (3) (4) °C/W 102 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G74 3 SN74LVC1G74 SCES794B – SEPTEMBER 2009 – REVISED FEBRUARY 2012 www.ti.com RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage Operating Data retention only High-level input voltage MAX 5.5 1.5 UNIT V 0.65 × VCC VCC = 1.65 V to 1.95 V VIH MIN 1.65 VCC = 2.3 V to 2.7 V 1.7 VCC = 3 V to 3.6 V V 2 0.7 × VCC VCC = 4.5 V to 5.5 V 0.35 × VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VIL Low-level input voltage VI Input voltage 0 5.5 V VO Output voltage 0 VCC V 0.3 × VCC VCC = 4.5 V to 5.5 V –4 VCC = 1.65 V –8 VCC = 2.3 V IOH High-level output current –16 VCC = 3 V Low-level output current Δt/Δv Input transition rise or fall rate –32 VCC = 1.65 V 4 VCC = 2.3 V 8 16 VCC = 3 V 32 VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 VCC = 5 V ± 0.5 V TA Operating free-air temperature DCT Package DCU Package (1) 4 mA 24 VCC = 4.5 V YZP Package mA –24 VCC = 4.5 V IOL V ns/V 5 –40 85 –40 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G74 SN74LVC1G74 SCES794B – SEPTEMBER 2009 – REVISED FEBRUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 μA VOH 1.65 V 1.2 IOH = –8 mA 2.3 V 1.9 4.5 V IOL = 100 μA 1.65 V to 5.5 V 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 IOL = 32 mA II 0.4 VI = 5.5 V or GND VI or VO = 5.5 V ICC VI = 5.5 V or GND, IO = 0 ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND V 0.55 4.5 V Ioff (1) 3.8 3V IOL = 24 mA Data or control inputs 2.3 IOH = –32 mA IOL = 16 mA UNIT V 2.4 3V IOH = –24 mA MAX VCC – 0.1 1.65 V to 5.5 V IOH = –4 mA IOH = –16 mA VOL MIN TYP (1) VCC 0.55 0 to 5.5 V ±5 μA 0 ±10 μA 1.65 V to 5.5 V 10 μA 3 V to 5.5 V 500 μA 3.3 V 5 pF All typical values are at VCC = 3.3 V, TA = 25°C. TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) Parame ter From To 85°C VCC = 1.8 V MIN fclock tw tsu MAX VCC = 2.5 V MIN 80 MAX 125°C VCC = 3.3 V MIN 175 MAX VCC = 5 V MIN 175 MAX VCC = 3.3 V MIN 200 MAX VCC = 5 V MIN 175 200 MHz CLK 6.2 2.7 2.7 2 2.7 2 PRE or CLR low 6.2 2.7 2.7 2 2.7 2 Data 2.9 1.7 1.3 1.1 1.3 1.1 PRE or CLR inactive 1.9 1.4 1.2 1 1.2 1.2 0 0.3 1.2 0.5 1.2 0.5 th UNIT MAX ns ns ns SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) Parame ter From To 85°C VCC = 1.8 V MIN fmax tpd MAX 80 CLK PRE or CLR low VCC = 2.5 V MIN MAX 175 125°C VCC = 3.3 V MIN MAX 175 VCC = 5 V MIN MAX 200 VCC = 3.3 V MIN MAX 175 VCC = 5 V MIN 200 MHz Q 4.8 13.4 2.2 7.1 2.2 5.9 1.4 4.1 2.2 7.9 1.4 6.1 Q 6 14.4 3 7.7 2.6 6.2 1.6 4.4 2.6 8.2 1.6 6.4 4.4 12.9 2.3 7 1.7 5.9 1.6 4.1 1.7 7.9 1.6 6.1 Q or Q Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G74 UNIT MAX ns 5 SN74LVC1G74 SCES794B – SEPTEMBER 2009 – REVISED FEBRUARY 2012 www.ti.com OPERATING CHARACTERISTICS TA = 25°C PARAMETER Cpd 6 Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 35 35 37 40 Submit Documentation Feedback UNIT pF Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G74 SN74LVC1G74 SCES794B – SEPTEMBER 2009 – REVISED FEBRUARY 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kW 500 W 500 W 500 W 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL VM VM 0V tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VM VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G74 7 SN74LVC1G74 SCES794B – SEPTEMBER 2009 – REVISED FEBRUARY 2012 www.ti.com REVISION HISTORY Changes from Original (October 2009) to Revision A Page • Changed Ioff description in FEATURES. ............................................................................................................................... 1 • Changed temperature range for DCT and DCU package from (–40°C to 85°C) to (–40°C to 125°). .................................. 2 • Changed TIMING REQUIREMENTS table. .......................................................................................................................... 5 • Changed SWITCHING CHARACTERISTICS table. ............................................................................................................. 5 Changes from Revision A (November 2011) to Revision B • 8 Page Added SN74LVC1G74DCURG4 part number to ORDERING INFORMATION table. ......................................................... 2 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G74 PACKAGE OPTION ADDENDUM www.ti.com 18-Feb-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) SN74LVC1G74DCT3 PREVIEW SM8 DCT 8 250 TBD SN74LVC1G74DCTR ACTIVE SM8 DCT 8 3000 Green (RoHS & no Sb/Br) SN74LVC1G74DCTRE6 PREVIEW SM8 DCT 8 3000 TBD Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) Call TI CU NIPDAU Level-1-260C-UNLIM Call TI Call TI Call TI Call TI SN74LVC1G74DCU PREVIEW US8 DCU 8 3000 TBD SN74LVC1G74DCU6 PREVIEW US8 DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G74DCUR ACTIVE US8 DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G74DCURG4 ACTIVE US8 DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G74DCUT ACTIVE US8 DCU 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G74YZPR PREVIEW DSBGA YZP 8 3000 TBD Call TI Call TI SN74LVC1G74YZTR PREVIEW DSBGA YZT 8 3000 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 18-Feb-2012 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVC1G74DCTR SM8 DCT 8 3000 180.0 13.0 3.35 4.5 1.55 4.0 12.0 Q3 SN74LVC1G74DCUR US8 DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3 SN74LVC1G74DCURG4 US8 DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3 SN74LVC1G74DCUT US8 DCU 8 250 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G74DCTR SM8 DCT 8 3000 182.0 182.0 20.0 SN74LVC1G74DCUR US8 DCU 8 3000 202.0 201.0 28.0 SN74LVC1G74DCURG4 US8 DCU 8 3000 202.0 201.0 28.0 SN74LVC1G74DCUT US8 DCU 8 250 202.0 201.0 28.0 Pack Materials-Page 2 MECHANICAL DATA MPDS049B – MAY 1999 – REVISED OCTOBER 2002 DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 8 0,13 M 5 0,15 NOM ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ 2,90 2,70 4,25 3,75 Gage Plane PIN 1 INDEX AREA 1 0,25 4 0° – 8° 3,15 2,75 0,60 0,20 1,30 MAX Seating Plane 0,10 0,10 0,00 NOTES: A. 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