September 2006 Advance Information AS7C31025C ® 3.3V 128K X 8 CMOS SRAM (Center power and ground) Features • Industrial and commercial temperatures • Organization: 131,072 x 8 bits • High speed - 10 ns address access time - 5 ns output enable access time • Low power consumption via ship deselect • Easy memory expansion with CE, OE inputs • Center power and ground • TTL/LVTTL-compatible, three-state I/O • JEDEC-standard packages - 32-pin, 300 mil SOJ - 32-pin, 400 mil SOJ - 32-pin, TSOP 2 • ESD protection ≥ 2000 volts Pin arrangement VCC GND 131,072 x 8 Array (1,048,576) I/O7 Sense amp A0 A1 A2 A3 A4 A5 A6 A7 A8 Address decoder Input buffer I/O0 Control circuit WE OE CE A9 A10 A11 A12 A13 A14 A15 A16 Address decoder 9/20/06, v. 1.0 Alliance Memory 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 GND VCC I/O5 I/O4 A12 A11 A10 A9 A8 32-pin SOJ (300 mil) 32-pin SOJ (400 mil) A0 A1 A2 A3 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AS7C31025C Logic block diagram AS7C31025C 32-pin TSOP 2 A0 A1 A2 A3 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A4 A5 A6 A7 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 GND VCC I/O5 I/O4 A12 A11 A10 A9 A8 P. 1 of 9 Copyright © Alliance Memory. All rights reserved. AS7C31025C ® Functional description The AS7C31025C is 3V a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10 ns with output enable access times (tOE) of 5 ns are ideal for high-performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems. When CE is high the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The AS7C31025C is packaged in common industry standard packages. Absolute maximum ratings Parameter Symbol Min Max Unit Voltage on VCC relative to GND Vt1 –0.50 +4.6 V Voltage on any pin relative to GND Vt2 –0.50 VCC + 0.5 V Power dissipation PD – 1.25 W +125 o Storage temperature (plastic) Tstg –55 C Ambient temperature with VCC applied Tbias –55 +125 oC DC current into outputs (low) IOUT – 50 mA NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE Data Mode H X X High Z Standby (ISB, ISB1) L H H High Z Output disable (ICC) L H L DOUT Read (ICC) L L X DIN Write (ICC) Key: X = don’t care, L = low, H = high. 9/20/06, v. 1.0 Alliance Memory P. 2 of 9 AS7C31025C ® Recommended operating conditions Parameter Symbol Min Nominal Max Unit VCC 3.0 3.3 3.6 V VIH 2.0 – VCC + 0.3 V VIL –0.5 – 0.8 Supply voltage Input voltage Ambient operating temperature (Industrial) TA –40 – V o 85 C VIL min = –2.0V for pulse width less than 5ns, once per cycle. VIH min = –VCC + 2.0V for pulse width less than 5ns, once per cycle. DC operating characteristics (over the operating range)1 AS7C31025C-10 Parameter Sym Test conditions Min Max Unit Input leakage current | ILI | VCC = Max, VIN = GND to VCC – 5 μA Output leakage current | ILO | VCC = Max, CE = VIH, Vout = GND to VCC – 5 μA – 150 mA – 50 mA VCC = Max Operating power supply current CE ≤ VIL, f = fMax, IOUT = 0 mA ICC VCC = Max ISB Standby power supply current1 Output voltage CE ≥ VIH, f = fMax ISB1 VCC = Max, CE ≥ VCC–0.2 V, VIN ≤ 0.2 V or VIN ≥ VCC –0.2 V, f=0 – 10 mA VOL IOL = 8 mA, VCC = Min – 0.4 V VOH IOH = –4 mA, VCC = Min 2.4 – V Capacitance (f = 1 MHz, Ta = 25o C, VCC = NOMINAL)2 Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CE, WE, OE VIN = 3dV 6 pF I/O capacitance CI/O I/O VOUT = 3dV 7 pF Note: 1. This parameter is guaranteed by device characterization, but is not production tested. 9/20/06, v. 1.0 Alliance Memory P. 3 of 9 AS7C31025C ® Read cycle (over the operating range)3,9 AS7C31025C-10 Parameter Symbol Min Max Unit Notes Read cycle time tRC 10 – ns Address access time tAA – 10 ns 3 Chip enable (CE) access time tACE – 10 ns 3 Output enable (OE) access time tOE – 5 ns Output hold from address change tOH 4 – ns 5 CE low to output in low Z tCLZ 4 – ns 4, 5 CE high to output in high Z tCHZ 0 5 ns 4, 5 OE low to output in low Z tOLZ 0 – ns 4, 5 OE high to output in high Z tOHZ 0 5 ns 4, 5 Power up time tPU 0 – ns 4, 5 Power down time tPD – 10 ns 4, 5 Key to switching waveforms Rising input Falling input Undefined/don’t care Read waveform 1 (address controlled)3,6,7,9 tRC Address tAA tOH DOUT Data valid Read waveform 2 (CE and OE controlled)3,6,8,9 tRC1 CE tOE OE DOUT Supply current 9/20/06, v. 1.0 tOHZ tCHZ tOLZ tACE tCLZ tPU Data valid tPD 50% ICC ISB 50% Alliance Memory P. 4 of 9 AS7C31025C ® Write cycle (over the operating range)11 AS7C31025C-10 Parameter Symbol Min Max Unit Notes Write cycle time tWC 10 – ns Chip enable (CE) to write end tCW 7 – ns Address setup to write end tAW 7 – ns Address setup time tAS 0 – ns Write pulse width tWP 7 – ns Write recovery time tWR 0 – ns Address hold from end of write tAH 0 – ns Data valid to write end tDW 5 – ns Data hold time tDH 0 – ns 4, 5 Write enable to output in high Z tWZ 0 5 ns 4, 5 Output active from write end tOW 3 – ns 4, 5 Write waveform 1 (WE controlled)10,11 tWC tAW tWR tAH Address tWP WE tAS tDW DIN tDH Data valid tWZ tOW DOUT Write waveform 2 (CE controlled)10,11 tAW tWC tAH tWR Address tAS tCW CE tWP WE tWZ DIN tDW tDH Data valid DOUT 9/20/06, v. 1.0 Alliance Memory P. 5 of 9 AS7C31025C ® AC test conditions – – – – Output load: see Figure B. Input pulse level: GND to 3.0 V. See Figure A. Input rise and fall times: 3 ns. See Figure A. Input and output timing reference levels: 1.5 V. Thevenin equivalent: 168 Ω DOUT +1.728 V +3.0 V DOUT 255 Ω +3.3 V 320 Ω GND 90% 10% 90% 3 ns 10% C13 GND Figure B: 3.3 V Output load Figure A: Input pulse Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A and B. tCLZ and tCHZ are specified with CL = 5 pF, as in Figure B. Transition is measured ±200 mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is high for read cycle. CE and OE are low for read cycle. Address is valid prior to or coincident with CE transition low. All read cycle timings are referenced from the last valid address to the first transitioning address. N/A All write cycle timings are referenced from the last valid address to the first transitioning address. N/A. C = 30 pF, except all high Z and low Z parameters where C = 5 pF. 9/20/06, v. 1.0 Alliance Memory P. 6 of 9 AS7C31025C ® Package dimensions 32-pin TSOP 2 N N/2+1 E E1 1 32-pin TSOP 2 (mm) Symbol Min Max A – 1.20 A1 0.05 0.15 b 0.3 0.52 C 0.12 0.21 D 20.82 21.08 E1 10.03 10.29 E 11.56 11.96 N/2 D Seating plane A ZD c A1 b e 1.27 BSC L 0.40 ZD a D e E1 E2 B Pin 1 A A1 c b A2 0° 5° c 32-pin SOJ 300 mil/400 mil Seating plane E 32-pin SOJ 300 mil 32-pin SOJ 400 mil Symbol Min Max Min Max A 0.128 0.145 0.132 0.146 A1 0.025 - 0.025 - A2 0.095 0.105 0.105 0.115 B 0.026 0.032 0.026 0.032 b 0.016 0.020 0.015 0.020 c 0.007 0.010 0.007 0.013 D 0.820 0.830 0.820 0.830 E 0.255 0.275 0.354 0.378 E1 0.295 0.305 0.395 0.405 E2 0.330 0.340 0.435 0.445 e 9/20/06, v. 1.0 0.95 REF. α L 0.60 Alliance Memory 0.050 BSC 0.050 BSC P. 7 of 9 AS7C31025C ® Ordering Codes Package Volt/Temperature 10 ns 300-mil SOJ 5V Industrial AS7C31025C-10TJIN 400-mil SOJ 5V Industrial AS7C31025C-10JIN TSOP 2 5V Industrial AS7C31025C-10TIN Part numbering system AS7C X SRAM prefix Voltage: 3 = 3.3 V CMOS 9/20/06, v. 1.0 1025B Device number –XX Access time X X X Package: TJ = SOJ 300 mil Temperature range J = SOJ 400 mil I = industrial, -40° N = Lead Free Part C to 85° C T = TSOP2 Alliance Memory P. 8 of 9 AS7C31025C ® ® Alliance Memory, Inc. 1116 South Amphlett San Mateo, CA 94402 Tel: 650-525-3737 Fax: 650-525-0449 www.alliancememory.com Copyright © Alliance Momory All Rights Reserved Part Number: AS7C31025C Document Version: v. 1.0 © Copyright 2003 Alliance Memory, Inc. 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