ALTERA EP2A70

APEX II
®
August 2002, ver. 3.0
Features...
Data Sheet
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Altera Corporation
DS-APEXII-3.0
Programmable Logic
Device Family
Programmable logic device (PLD) manufactured using a 0.15-µm alllayer copper-metal fabrication process (up to eight layers of metal)
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1-gigabit per second (Gbps) True-LVDSTM, LVPECL, pseudo
current mode logic (PCML), and HyperTransportTM interface
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Clock-data synchronization (CDS) in True-LVDS interface to
correct any fixed clock-to-data skew
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Enables common networking and communications bus I/O
standards such as RapidIOTM, CSIX, Utopia IV, and POS-PHY
Level 4
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Support for high-speed external memory interfaces, including
zero bus turnaround (ZBT), quad data rate (QDR), and double
data rate (DDR) static RAM (SRAM), and single data rate (SDR)
and DDR synchronous dynamic RAM (SDRAM)
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30% to 40% faster design performance than APEXTM 20KE
devices on average
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Enhanced 4,096-bit embedded system blocks (ESBs)
implementing first-in first-out (FIFO) buffers, Dual-Port+ RAM
(bidirectional dual-port RAM), and content-addressable
memory (CAM)
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High-performance, low-power copper interconnect
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Fast parallel byte-wide synchronous device configuration
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Look-up table (LUT) logic available for register-intensive
functions
High-density architecture
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1,900,000 to 5,250,000 maximum system gates (see Table 1)
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Up to 67,200 logic elements (LEs)
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Up to 1,146,880 RAM bits that can be used without reducing
available logic
Low-power operation design
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1.5-V supply voltage
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Copper interconnect reduces power consumption
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MultiVoltTM I/O support for 1.5-V, 1.8-V, 2.5-V, and 3.3-V
interfaces
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ESBs offer programmable power-saving mode
1
APEX II Programmable Logic Device Family Data Sheet
Table 1. APEX II Device Features
Feature
Maximum gates
EP2A15
EP2A25
EP2A40
EP2A70
1,900,000
2,750,000
3,000,000
5,250,000
Typical gates
600,000
900,000
1,500,000
3,000,000
LEs
16,640
24,320
38,400
67,200
104
152
160
280
425,984
622,592
655,360
1,146,880
36 (1)
36 (1)
36 (1)
RAM ESBs
Maximum RAM bits
True-LVDS channels
36 (1)
Flexible-LVDSTM channels (2)
56
56
88
True-LVDS PLLs (3)
4
4
4
4
General-purpose PLL outputs (4)
8
8
8
8
492
612
735
1,060
Maximum user I/O pins
88
Notes to Table 1:
(1)
(2)
(3)
(4)
Each device has 36 input channels and 36 output channels.
EP2A15 and EP2A25 devices have 56 input and 56 output channels; EP2A40 and EP2A70 devices have 88 input and
88 output channels.
PLL: phase-locked loop. True-LVDS PLLs are dedicated to implement True-LVDS functionality.
Two internal outputs per PLL are available. Additionally, the device has one external output per PLL pair (two
external outputs per device).
...and More
Features
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I/O features
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Up to 380 Gbps of I/O capability
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1-Gbps True-LVDS, LVPECL, PCML, and HyperTransport
support on 36 input and 36 output channels that feature clock
synchronization circuitry and independent clock multiplication
and serialization/deserialization factors
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Common networking and communications bus I/O standards
such as RapidIO, CSIX, Utopia IV, and POS-PHY Level 4 enabled
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400-megabits per second (Mbps) Flexible-LVDS and
HyperTransport support on up to 88 input and 88 output
channels (input channels also support LVPECL)
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Support for high-speed external memories, including ZBT, QDR,
and DDR SRAM, and SDR and DDR SDRAM
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Compliant with peripheral component interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits
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Compliant with 133-MHz PCI-X specifications
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Support for other advanced I/O standards, including AGP, CTT,
SSTL-3 and SSTL-2 Class I and II, GTL+, and HSTL Class I and II
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Six dedicated registers in each I/O element (IOE): two input
registers, two output registers, and two output-enable registers
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Programmable bus hold feature
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Programmable pull-up resistor on I/O pins available during
user mode
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
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Altera Corporation
Programmable output drive for 3.3-V LVTTL at 4 mA, 12 mA,
24 mA, or I/O standard levels
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Programmable output slew-rate control reduces switching noise
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Hot-socketing operation supported
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Pull-up resistor on I/O pins before and during configuration
Enhanced internal memory structure
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High-density 4,096-bit ESBs
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Dual-Port+ RAM with bidirectional read and write ports
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Support for many other memory functions, including CAM,
FIFO, and ROM
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ESB packing mode partitions one ESB into two 2,048-bit blocks
Device configuration
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Fast byte-wide synchronous configuration minimizes in-circuit
reconfiguration time
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Device configuration supports multiple voltages (either 3.3 V
and 2.5 V or 1.8 V)
Flexible clock management circuitry with eight general-purpose PLL
outputs
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Four general-purpose PLLs with two outputs per PLL
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Built-in low-skew clock tree
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Eight global clock signals
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ClockLockTM feature reducing clock delay and skew
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ClockBoostTM feature providing clock multiplication (by 1 to 160)
and division (by 1 to 256)
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ClockShiftTM feature providing programmable clock phase and
delay shifting with coarse (90°, 180°, or 270°) and fine (0.5 to
1.0 ns) resolution
Advanced interconnect structure
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All-layer copper interconnect for high performance
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Four-level hierarchical FastTrack® interconnect structure for fast,
predictable interconnect delays
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Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
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Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
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Interleaved local interconnect allowing one LE to drive 29 other
LEs through the fast local interconnect
Advanced software support
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Software design support and automatic place-and-route
provided by the Altera® QuartusTM II development system for
Windows-based PCs, Sun SPARCstations, and HP 9000
Series 700/800 workstations
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Altera MegaCore® functions and Altera Megafunction Partners
Program (AMPPSM) megafunctions optimized for APEX II
architecture
3
APEX II Programmable Logic Device Family Data Sheet
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LogicLockTM incremental design for intellectual property (IP)
integration and team-based design
NativeLinkTM integration with popular synthesis, simulation,
and timing analysis tools
SignalTap® embedded logic analyzer simplifies in-system design
evaluation by giving access to internal nodes during device
operation
Support for popular revision-control software packages,
including PVCS, RCS, and SCCS
Tables 2 and 3 show the APEX II ball-grid array (BGA) and
FineLine BGATM device package sizes, options, and I/O pin counts.
Table 2. APEX II Package Sizes
Feature
672-Pin
FineLine BGA
724-Pin BGA
1,020-Pin
FineLine BGA
1,508-Pin
FineLine BGA
Pitch (mm)
1.00
1.27
1.00
1.00
Area (mm 2)
729
1,225
1,089
1,600
27 × 27
35 × 35
33 × 33
40 × 40
1,020-Pin
FineLine BGA
1,508-Pin
FineLine BGA
Length × Width (mm × mm)
Table 3. APEX II Package Options & I/O Pin Count
Notes (1), (2)
Feature
672-Pin
FineLine BGA
724-Pin BGA
EP2A15
492
492
EP2A25
492
536
EP2A40
492
EP2A70
536
536
735
1,060
Notes to Table 3:
(1)
(2)
4
All APEX II devices support vertical migration within the same package (e.g., the designer can migrate between the
EP2A15, EP2A25, and EP2A40 devices in the 672-pin FineLine BGA package). Vertical migration means that
designers can migrate to devices whose dedicated pins, configuration pins, LVDS pins, and power pins are the same
for a given package across device densities. Migration of I/O pins across densities requires the designer to cross
reference the available I/O pins using the device pin-outs. This must be done for all planned densities for a given
package type to identify which I/O pins are migratable.
I/O pin counts include dedicated clock and fast I/O pins.
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
General
Description
APEX II devices integrate high-speed differential I/O support using the
True-LVDS interface. The dedicated serializer, deserializer, and CDS
circuitry in the True-LVDS interface support the LVDS, LVPECL,
HyperTransport, and PCML I/O standards. Flexible-LVDS pins located
in regular user I/O banks offer additional differential support, increasing
the total device bandwidth. This circuitry, together with enhanced IOEs
and support for numerous I/O standards, allows APEX II devices to meet
high-speed interface requirements.
APEX II devices also include other high-performance features such as
bidirectional dual-port RAM, CAM, general-purpose PLLs, and
numerous global clocks.
Configuration
The logic, circuitry, and interconnects in the APEX II architecture are
configured with CMOS SRAM elements. APEX II devices are
reconfigurable and are 100% tested prior to shipment. As a result, test
vectors do not have to be generated for fault coverage. Instead, the
designer can focus on simulation and design verification. In addition, the
designer does not need to manage inventories of different ASIC designs;
APEX II devices can be configured on the board for the specific
functionality required.
APEX II devices are configured at system power-up with data either
stored in an Altera configuration device or provided by a system
controller. Altera offers in-system programmability (ISP)-capable
configuration devices, which configure APEX II devices via a serial data
stream. The enhanced configuration devices can configure any APEX II
device in under 100 ms. Moreover, APEX II devices contain an optimized
interface that permits microprocessors to configure APEX II devices
serially or in parallel, synchronously or asynchronously. This interface
also enables microprocessors to treat APEX II devices as memory and to
configure the device by writing to a virtual memory location, simplifying
reconfiguration.
APEX II devices also support a new byte-wide, synchronous
configuration scheme at speeds of up to 66 MHz using EPC16
configuration devices or a microprocessor. This parallel configuration
reduces configuration time by using eight data lines to send configuration
data versus one data line in serial configuration.
APEX II devices support multi-voltage configuration; device
configuration can be performed at 3.3 V and 2.5 V or 1.8 V.
Altera Corporation
5
APEX II Programmable Logic Device Family Data Sheet
After an APEX II device has been configured, it can be reconfigured incircuit by resetting the device and loading new data. Real-time changes
can be made during system operation, enabling innovative reconfigurable
computing applications.
Software
APEX II devices are supported by the Altera Quartus II development
system: a single, integrated package that offers hardware description
language (HDL) and schematic design entry, compilation and logic
synthesis, full simulation and worst-case timing analysis, SignalTap logic
analysis, and device configuration. The Quartus II software runs on
Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800
workstations.
The Quartus II software includes the LogicLock incremental design
feature. The LogicLock feature allows the designer to make pin and
timing assignments, verify functionality and performance, and then set
constraints to lock down the placement and performance of a specific
block of logic using LogicLock constraints. Constraints set by the
LogicLock function guarantee repeatable placement when implementing
a block of logic in a current project or exporting the block to another
project. The constraints set by the LogicLock feature can lock down logic
to a fixed location in the device. The LogicLock feature can also lock the
logic down to a floating location, and the Quartus II software determines
the best relative placement of the block to meet design requirements.
Adding additional logic to a project will not affect the performance of
blocks locked down with LogicLock constraints.
The Quartus II software provides NativeLink interfaces to other industrystandard PC- and UNIX workstation-based EDA tools. For example,
designers can open the Quartus II software from within third-party
design tools. The Quartus II software also contains built-in optimized
synthesis libraries; synthesis tools can use these libraries to optimize
designs for APEX II devices. For example, the Synopsys Design Compiler
library, supplied with the Quartus II development system, includes
DesignWare functions optimized for the APEX II architecture.
Functional
Description
6
APEX II devices incorporate LUT-based logic, product-term-based logic,
memory, and high-speed I/O standards into one device. Signal
interconnections within APEX II devices (as well as to and from device
pins) are provided by the FastTrack interconnect—a series of fast,
continuous row and column channels that run the entire length and width
of the device.
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Each I/O pin is fed by an IOE located at the end of each row and column
of the FastTrack interconnect. Each IOE contains a bidirectional I/O buffer
and six registers that can be used for registering input, output, and
output-enable signals. When used with a dedicated clock pin, these
registers provide exceptional performance and interface support with
external memory devices such as DDR SDRAM and ZBT and QDR SRAM
devices.
IOEs provide a variety of features such as: 3.3-V, 64-bit, 66-MHz PCI
compliance, 3.3-V, 64-bit, 133-MHz PCI-X compliance, Joint Test Action
Group (JTAG) boundary-scan test (BST) support, output drive strength
control, slew-rate control, tri-state buffers, bus-hold circuitry,
programmable pull-up resistors, programmable input and output delays,
and open-drain outputs.
APEX II devices offer enhanced I/O support, including support for 1.5 V,
1.8 V, 2.5 V, 3.3 V, LVCMOS, LVTTL, HSTL, LVDS, LVPECL,
HyperTransport, PCML, 3.3-V PCI, PCI-X, GTL+, SSTL-2, SSTL-3, CTT,
and 3.3-V AGP I/O standards. High-speed (up to 1.0 Gbps) differential
transfers are supported with True-LVDS circuitry for LVDS, LVPECL,
HyperTransport, and PCML I/O standards. The optional CDS feature
corrects any clock-to-data skew at the True-LVDS receiver channels,
allowing for flexible board topologies. Up to 88 Flexible-LVDS channels
support differential transfer at up to 400 Mbps (DDR) for LVDS and
HyperTransport I/O standards.
An ESB can implement many types of memory, including Dual-Port+
RAM, CAM, ROM, and FIFO functions. Embedding the memory directly
into the die improves performance and reduces die area compared to
distributed-RAM implementations. The abundance of cascadable ESBs
ensures that the APEX II device can implement multiple wide memory
blocks for high-density designs. The ESB’s high speed ensures it can
implement small memory blocks without any speed penalty. The
abundance of ESBs, in conjunction with the ability for one ESB to
implement two separate memory blocks, ensures that designers can create
as many different-sized memory blocks as the system requires.
Figure 1 shows an overview of the APEX II device.
Altera Corporation
7
APEX II Programmable Logic Device Family Data Sheet
Figure 1. APEX II Device Block Diagram
Clock Management Circuitry
Four-input LUT
for data path and
DSP functions.
Product-term
integration for
high-speed
control logic and
state machines.
FastTrack
Interconnect
IOE
ClockLock
IOE
LUT
LUT
LUT
LUT
IOE
Product Term
Product Term
Product Term
Product Term
Memory
Memory
Memory
Memory
IOE
IOE
IOE
LUT
LUT
LUT
LUT
LUT
Product Term
Product Term
Product Term
Product Term
Memory
Memory
Memory
Memory
IOE
IOE
IOE
IOE
IOE
IOEs support
PCI, GTL+,
SSTL-3, LVDS,
and other
standards.
IOE
Flexible integration
of embedded
memory, including
CAM, RAM,
ROM, FIFO, and
other memory
functions.
Table 4 lists the resources available in APEX II devices.
Table 4. APEX II Device Resources
Device
MegaLAB Rows
MegaLAB
Columns
ESBs
EP2A15
26
4
104
EP2A25
38
4
152
EP2A40
40
4
160
EP2A70
70
4
280
APEX II devices provide eight dedicated clock input pins and four
dedicated fast I/O pins that globally drive register control inputs,
including clocks. These signals ensure efficient distribution of high-speed,
low-skew control signals. The control signals use dedicated routing
channels to provide short delays and low skew. The dedicated fast signals
can also be driven by internal logic, providing an ideal solution for a clock
divider or internally-generated asynchronous control signal with high
fan-out. The dedicated clock and fast I/O pins on APEX II devices can also
feed logic. Dedicated clocks can also be used with the APEX II generalpurpose PLLs for clock management.
8
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
MegaLAB Structure
APEX II devices are constructed from a series of MegaLABTM structures.
Each MegaLAB structure contains a group of logic array blocks (LABs),
one ESB, and a MegaLAB interconnect, which routes signals within the
MegaLAB structure. EP2A15 and EP2A25 devices have 16 LABs and
EP2A40 and EP2A70 devices have 24 LABs. Signals are routed between
MegaLAB structures and I/O pins via the FastTrack interconnect. In
addition, edge LABs can be driven by I/O pins through the local
interconnect. Figure 2 shows the MegaLAB structure.
Figure 2. MegaLAB Structure
MegaLAB Interconnect
To Adjacent
LAB or IOEs
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
Local
Interconnect
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
ESB
LABs
Logic Array Block
Each LAB consists of 10 LEs, the LEs’ associated carry and cascade chains,
LAB control signals, and the local interconnect. The local interconnect
transfers signals between LEs in the same or adjacent LABs, IOEs, or ESBs.
The Quartus II Compiler places associated logic within a LAB or adjacent
LABs, allowing the use of a fast local interconnect for high performance.
APEX II devices use an interleaved LAB structure, so that each LAB can
drive two local interconnect areas. Every other LE drives to either the left
or right local interconnect area, alternating by LE. The local interconnect
can drive LEs within the same LAB or adjacent LABs. This feature
minimizes the use of the row and column interconnects, providing higher
performance and flexibility. Each LAB structure can drive 30 LEs through
fast local interconnects.
Altera Corporation
9
APEX II Programmable Logic Device Family Data Sheet
Figure 3 shows the APEX II LAB.
Figure 3. APEX II LAB Structure
Row
Interconnect
MegaLAB Interconnect
LEs drive local,
MegaLAB, row,
and column
interconnects.
To/From
Adjacent LAB,
ESB, or IOEs
To/From
Adjacent LAB,
ESB, or IOEs
Local Interconnect
Column
Interconnect
The 10 LEs in the LAB are driven by
two local interconnect areas. These LEs
can drive two local interconnect areas.
Each LAB contains dedicated logic for driving control signals to its LEs
and ESBs. The control signals include clock, clock enable, asynchronous
clear, asynchronous preset, asynchronous load, synchronous clear, and
synchronous load signals. A maximum of six control signals can be used
at a time. Although synchronous load and clear signals are generally used
when implementing counters, they can also be used with other functions.
Each LAB can use two clocks and two clock enable signals. The LAB’s
clock and clock enable signals are linked (e.g., any LE in a particular LAB
using CLK1 will also use CLKENA1). LEs with the same clock but different
clock enable signals either use both clock signals in one LAB or are placed
into separate LABs. If both the rising and falling edges of a clock are used
in an LAB, both LAB-wide clock signals are used.
10
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
The LAB-wide control signals can be generated from the LAB local
interconnect, global signals, and dedicated clock pins. The inherent low
skew of the FastTrack interconnect enables it to be used for clock
distribution. Figure 4 shows the LAB control signal generation circuit.
Figure 4. LAB Control Signal Generation
Dedicated
Clocks
8
Fast Global
Signals
4
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
SYNCLOAD
or LABCLKENA2
SYNCCLR
or LABCLK2 (2)
LABCLKENA1
LABCLK1
LABCLR1 (1)
LABCLR2 (1)
Notes to Figure 4:
(1)
(2)
The LABCLR1 and LABCLR2 signals also control asynchronous load and asynchronous preset for LEs within the
LAB.
The SYNCCLR signal can be generated by the local interconnect or global signals.
Logic Element
The LE is the smallest unit of logic in the APEX II architecture. Each LE
contains a four-input LUT, which is a function generator that can quickly
implement any function of four variables. In addition, each LE contains a
programmable register and carry and cascade chains. Each LE drives the
local interconnect, MegaLAB interconnect, and FastTrack interconnect
routing structures. See Figure 5.
Altera Corporation
11
APEX II Programmable Logic Device Family Data Sheet
Figure 5. APEX II Logic Element
Register Bypass
Carry-In
data1
data2
data3
data4
Look-Up
Table
(LUT)
Carry
Chain
LAB-wide
LAB-wide
Synchronous Synchronous
Load
Clear
Cascade-In
Cascade
Chain
Synchronous
Load & Clear
Logic
Packed
Register Select
Programmable
Register
D
PRN
Q
To FastTrack Interconnect,
MegaLAB Interconnect,
or Local Interconnect
ENA
CLRN
To FastTrack Interconnect,
MegaLAB Interconnect,
or Local Interconnect
labclr1
labclr2
Chip-Wide
Reset
Asynchronous
Clear/Preset/
Load Logic
Clock &
Clock Enable
Select
labclk1
labclk2
labclkena1
labclkena2
Carry-Out
Cascade-Out
Each LE’s programmable register can be configured for D, T, JK, or SR
operation. The register’s clock and clear control signals can be driven by
global signals, general-purpose I/O pins, or any internal logic. For
combinatorial functions, the register is bypassed and the output of the
LUT drives the outputs of the LE.
12
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Each LE has two outputs that drive the local, MegaLAB, or FastTrack
interconnect routing structure. Each output can be driven independently
by the LUT’s or register’s output. For example, the LUT can drive one
output while the register drives the other output. This feature, called
register packing, improves device utilization because the register and the
LUT can be used for unrelated functions. The LE can also drive out
registered and unregistered versions of the LUT output. The APEX II
architecture provides two types of dedicated high-speed data paths that
connect adjacent LEs without using local interconnect paths: carry chains
and cascade chains. A carry chain supports high-speed arithmetic
functions such as counters and adders, while a cascade chain implements
wide-input functions such as equality comparators with minimum delay.
Carry and cascade chains connect LEs 1 through 10 in an LAB and all
LABs in the same MegaLAB structure.
Carry Chain
The carry chain provides a fast carry-forward function between LEs. The
carry-in signal from a lower-order bit drives forward into the higherorder bit via the carry chain, and feeds into both the LUT and the next
portion of the carry chain. This feature allows the APEX II architecture to
implement high-speed counters, adders, and comparators of arbitrary
width. The Quartus II Compiler can create carry chain logic automatically
during the design process, or the designer can create it manually during
design entry. Parameterized functions such as DesignWare functions
from Synopsys and library of parameterized modules (LPM) functions
automatically take advantage of carry chains for the appropriate
functions.
The Quartus II Compiler creates carry chains longer than 10 LEs by
linking LABs together automatically. For enhanced fitting, a long carry
chain skips alternate LABs in a MegaLAB structure. A carry chain longer
than one LAB skips either from an even-numbered LAB to the next evennumbered LAB, or from an odd-numbered LAB to the next oddnumbered LAB. For example, the last LE of the first LAB in the upper-left
MegaLAB structure carries to the first LE of the third LAB in the
MegaLAB structure.
Figure 6 shows how an n-bit full adder can be implemented in n + 1 LEs
with the carry chain. One portion of the LUT generates the sum of two bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. The register can be bypassed for simple adders or used
for accumulator functions. Another portion of the LUT and the carry chain
logic generates the carry-out signal, which is routed directly to the carryin signal of the next-higher-order bit. The final carry-out signal is routed
to an LE, where it is driven onto the local, MegaLAB, or FastTrack
interconnect routing structures.
Altera Corporation
13
APEX II Programmable Logic Device Family Data Sheet
Figure 6. APEX II Carry Chain
Carry-In
a1
b1
LUT
s1
Register
Carry Chain
LE1
a2
b2
LUT
s2
Register
Carry Chain
LE2
an
bn
LUT
sn
Register
Carry Chain
LEn
LUT
Register
Carry-Out
Carry Chain
LEn + 1
14
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Cascade Chain
With the cascade chain, the APEX II architecture can implement functions
with a very wide fan-in. Adjacent LUTs can compute portions of a
function in parallel; the cascade chain serially connects the intermediate
values. The cascade chain can use a logical AND or logical OR (via
DeMorgan’s inversion) to connect the outputs of adjacent LEs. Each
additional LE provides four more inputs to the effective width of a
function, with a short cascade delay. The Quartus II Compiler can create
cascade chain logic automatically during the design process, or the
designer can create it manually during design entry.
Cascade chains longer than 10 LEs are implemented automatically by
linking LABs together. For enhanced fitting, a long cascade chain skips
alternate LABs in a MegaLAB structure. A cascade chain longer than one
LAB skips either from an even-numbered LAB to the next even-numbered
LAB, or from an odd-numbered LAB to the next odd-numbered LAB. For
example, the last LE of the first LAB in the upper-left MegaLAB structure
carries to the first LE of the third LAB in the MegaLAB structure. Figure 7
shows how the cascade function can connect adjacent LEs to form
functions with a wide fan-in.
Figure 7. APEX II Cascade Chain
AND Cascade Chain
d[3..0]
OR Cascade Chain
d[3..0]
LUT
LUT
LE1
LE1
d[7..4]
d[7..4]
LUT
LUT
LE2
LE2
d[(4n — 1)..(4n — 4)]
d[(4n — 1)..(4n — 4)]
LUT
LEn
Altera Corporation
LUT
LEn
15
APEX II Programmable Logic Device Family Data Sheet
LE Operating Modes
The APEX II LE can operate in one of the following three modes:
■
■
■
Normal mode
Arithmetic mode
Counter mode
Each mode uses LE resources differently. In each mode, seven available
inputs to the LE—the four data inputs from the LAB local interconnect,
the feedback from the programmable register, and the carry-in and
cascade-in from the previous LE—are directed to different destinations to
implement the desired logic function. LAB-wide signals provide clock,
asynchronous clear, asynchronous preset, asynchronous load,
synchronous clear, synchronous load, and clock enable control for the
register. These LAB-wide signals are available in all LE modes.
The Quartus II software, in conjunction with parameterized functions
such as LPM and DesignWare functions, automatically chooses the
appropriate mode for common functions such as counters, adders, and
multipliers. If required, the designer can also create special-purpose
functions that specify which LE operating mode to use for optimal
performance. Figure 8 shows the LE operating modes.
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Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Figure 8. APEX II LE Operating Modes
LAB-Wide
Clock Enable (2)
Normal Mode (1)
Carry-In (3)
Cascade-In
LE-Out
data1
data2
4-Input
LUT
data3
D
PRN
Q
LE-Out
data4
ENA
CLRN
Cascade-Out
LAB-Wide
Clock Enable (2)
Arithmetic Mode
Carry-In
Cascade-In
LE-Out
data1
data2
D
3-Input
LUT
PRN
Q
LE-Out
ENA
CLRN
3-Input
LUT
Cascade-Out
Carry-Out
Counter Mode
LAB-Wide
Synchronous
Clear (6)
Cascade-In
Carry-In
LAB-Wide
Synchronous
Load (6)
LAB-Wide
Clock Enable (2)
(4)
data1 (5)
data2 (5)
LE-Out
3-Input
LUT
D
PRN
Q
LE-Out
data3
ENA
CLRN
3-Input
LUT
Carry-Out Cascade-Out
Notes to Figure 8:
(1)
(2)
(3)
(4)
(5)
(6)
LEs in normal mode support register packing.
There are two LAB-wide clock enables per LAB.
When using the carry-in in normal mode, the packed register feature is unavailable.
A register feedback multiplexer is available on LE1 of each LAB.
The DATA1 and DATA2 input signals can supply counter enable, up or down control, or register feedback signals for
LEs other than the second LE in a LAB.
The LAB-wide synchronous clear and LAB-wide synchronous load affect all registers in a LAB.
Altera Corporation
17
APEX II Programmable Logic Device Family Data Sheet
Normal Mode
The normal mode is suitable for general logic applications, combinatorial
functions, or wide decoding functions that can take advantage of a
cascade chain. In normal mode, four data inputs from the LAB local
interconnect and the carry-in are inputs to a four-input LUT. The
Quartus II Compiler automatically selects the carry-in or the DATA3 signal
as one of the inputs to the LUT. The LUT output can be combined with the
cascade-in signal to form a cascade chain through the cascade-out signal.
LEs in normal mode support packed registers.
Arithmetic Mode
The arithmetic mode is ideal for implementing adders, accumulators, and
comparators. An LE in arithmetic mode uses two 3-input LUTs. One LUT
computes a three-input function; the other generates a carry output. As
shown in Figure 8, the first LUT uses the carry-in signal and two data
inputs from the LAB local interconnect to generate a combinatorial or
registered output. For example, when implementing an adder, this output
is the sum of three signals: DATA1, DATA2, and carry-in. The second LUT
uses the same three signals to generate a carry-out signal, thereby creating
a carry chain. The arithmetic mode also supports simultaneous use of the
cascade chain. LEs in arithmetic mode can drive out registered and
unregistered versions of the LUT output.
The Quartus II software implements parameterized functions that use the
arithmetic mode automatically where appropriate; the designer does not
need to specify how the carry chain will be used.
Counter Mode
The counter mode offers clock enable, counter enable, synchronous
up/down control, synchronous clear, and synchronous load options. The
counter enable and synchronous up/down control signals are generated
from the data inputs of the LAB local interconnect. The synchronous clear
and synchronous load options are LAB-wide signals that affect all
registers in the LAB. Consequently, if any of the LEs in an LAB use the
counter mode, other LEs in that LAB must be used as part of the same
counter or be used for a combinatorial function. The Quartus II software
automatically places any registers that are not used by the counter into
other LABs.
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Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
The counter mode uses two three-input LUTs: one generates the counter
data, and the other generates the fast carry bit. A 2-to-1 multiplexer
provides synchronous loading, and another AND gate provides
synchronous clearing. If the cascade function is used by an LE in counter
mode, the synchronous clear or load overrides any signal carried on the
cascade chain. The synchronous clear overrides the synchronous load.
LEs in arithmetic mode can drive out registered and unregistered versions
of the LUT output.
Clear & Preset Logic Control
Logic for the register’s clear and preset signals is controlled by LAB-wide
signals. The LE directly supports an asynchronous clear function. The
Quartus II Compiler can use a NOT-gate push-back technique to emulate
an asynchronous preset. Moreover, the Quartus II Compiler can use a
programmable NOT-gate push-back technique to emulate simultaneous
preset and clear or asynchronous load. However, this technique uses three
additional LEs per register. All emulation is performed automatically
when the design is compiled. Registers that emulate simultaneous preset
and load will enter an unknown state upon power-up or when the chipwide reset is asserted.
In addition to the two clear and preset modes, APEX II devices provide a
chip-wide reset pin (DEV_CLRn) that resets all registers in the device. Use
of this pin is controlled through an option in the Quartus II software that
is set before compilation. The chip-wide reset overrides all other control
signals. Registers using an asynchronous preset are preset when the chipwide reset is asserted; this effect results from the inversion technique used
to implement the asynchronous preset.
FastTrack Interconnect
In the APEX II architecture, connections between LEs, ESBs, and I/O pins
are provided by the FastTrack interconnect. The FastTrack interconnect is
a series of continuous horizontal and vertical routing channels that
traverse the device. This global routing structure provides predictable
performance, even in complex designs. In contrast, the segmented routing
in FPGAs requires switch matrices to connect a variable number of
routing paths, increasing the delays between logic resources and reducing
performance.
Altera Corporation
19
APEX II Programmable Logic Device Family Data Sheet
The FastTrack interconnect consists of row and column interconnect
channels that span the entire device. The row interconnect routes signals
throughout a row of MegaLAB structures; the column interconnect routes
signals throughout a column of MegaLAB structures. When using the row
and column interconnect, an LE, IOE, or ESB can drive any other LE, IOE,
or ESB in a device. See Figure 9.
Figure 9. APEX II Interconnect Structure
Row
Interconnect
I/O
I/O
I/O
I/O
I/O
I/O
MegaLAB
MegaLAB
MegaLAB
MegaLAB
I/O
MegaLAB
MegaLAB
MegaLAB
MegaLAB
I/O
MegaLAB
MegaLAB
MegaLAB
MegaLAB
I/O
Column
Interconnect
I/O
I/O
I/O
I/O
I/O
A row line can be driven directly by LEs, IOEs, or ESBs in that row.
Further, a column line can drive a row line, allowing an LE, IOE, or ESB to
drive elements in a different row via the column and row interconnect.
The row interconnect drives the MegaLAB interconnect to drive LEs,
IOEs, or ESBs in a particular MegaLAB structure.
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Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
A column line can be directly driven by the LEs, IOEs, or ESBs in that
column. Row IOEs can drive a column line on a device’s left or right edge.
The column line is used to route signals from one row to another. A
column line can drive a row line; it can also drive the MegaLAB
interconnect directly, allowing faster connections between rows.
Figure 10 shows how the FastTrack interconnect uses the local
interconnect to drive LEs within MegaLAB structures.
Figure 10. FastTrack Connection to Local Interconnect
I/O
Row
I/O
L E
A S
B B
L L
A A
B B
E L L
S A A
B B B
L
A
B
MegaLAB
MegaLAB
Row & Column
Interconnect Drives
MegaLAB Interconnect
Column
Row
MegaLAB
Interconnect
MegaLAB
Interconnect Drives
Local Interconnect
Column
L
A
B
L
A
B
L
A
B
E
S
B
Figure 11 shows the intersection of a row and column interconnect and
how these forms of interconnects and LEs drive each other.
Altera Corporation
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APEX II Programmable Logic Device Family Data Sheet
Figure 11. Driving the FastTrack Interconnect
Row
Interconnect
MegaLAB
Interconnect
Column
Interconnect
LE
Local
Interconnect
APEX II devices feature FastRowTM lines for quickly routing input signals
with high fan-out. Column I/O pins can drive the FastRow interconnect,
which routes signals directly into the local interconnect without having to
drive through the MegaLAB interconnect. FastRow lines traverse two
MegaLAB structures. The FastRow interconnect drives the four
MegaLABs in the top row and the four MegaLABs in the bottom row of
the device. The FastRow interconnect drives all local interconnects in the
appropriate MegaLABs. Column pins using the FastRow interconnect
achieve a faster set-up time, because the signal does not need to use a
MegaLab interconnect line to reach the destination LE. Figure 12 shows
the FastRow interconnect.
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Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Figure 12. APEX II FastRow Interconnect
FastRow
Interconnect
IOE
IOE
FastRow Interconnect
Drives Local Interconnect
in Two MegaLAB Structures
IOE
IOE
Select Vertical I/O Pins
Drive Local Interconnect
and FastRow
Interconnect
Local
Interconnect
LEs
MegaLAB
Altera Corporation
LABs
MegaLAB
23
APEX II Programmable Logic Device Family Data Sheet
Table 5 summarizes how elements of the APEX II architecture drive each
other.
Table 5. APEX II Routing Scheme
Source
Destination
Row Column
I/O Pin I/O Pin
LE
ESB
Local
MegaLAB
Interconnect Interconnect
v
Row I/O pin
v
Row
Column
FastRow
FastTrack
FastTrack Interconnect
Interconnect Interconnect
v
v
v
Column I/O
pin
LE
v
v
v
v
ESB
v
v
v
v
Local
interconnect
MegaLAB
interconnect
v
v
v
v
v
Row
FastTrack
interconnect
v
Column
FastTrack
interconnect
v
FastRow
interconnect
v
v
v
v
Product-Term Logic
The product-term portion of the MultiCore architecture is implemented
with the ESB. The ESB can be configured to act as a block of macrocells on
an ESB-by-ESB basis. 32 inputs from the adjacent local interconnect feed
each ESB; therefore, the either MegaLAB or the adjacent LAB can drive the
ESB. Also, nine ESB macrocells feed back into the ESB through the local
interconnect for higher performance. Dedicated clock pins, global signals,
and additional inputs from the local interconnect drive the ESB control
signals.
In product-term mode, each ESB contains 16 macrocells. Each macrocell
consists of two product terms and a programmable register. Figure 13
shows the ESB in product-term mode.
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Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Figure 13. Product-Term Logic in ESB
Dedicated Clocks
Global Signals
MegaLAB Interconnect
4
8
(1)
65
9
32
From
Adjacent
LAB
2
2
2
Macrocell
Inputs (1 to 16)
CLK[1..0]
16
To Row
and Column
Interconnect
ENA[1..0]
CLRN[1..0]
Local
Interconnect
Note ot Figure 13:
(1)
PLL outputs cannot drive data input ports.
Macrocells
APEX II macrocells can be configured individually for either sequential or
combinatorial logic operation. The macrocell consists of three functional
blocks: the logic array, the product-term select matrix, and the
programmable register.
Combinatorial logic is implemented in the product terms. The productterm select matrix allocates these product terms for use as either primary
logic inputs (to the OR and XOR gates) to implement combinatorial
functions, or as parallel expanders to be used to increase the logic
available to another macrocell. One product term can be inverted; the
Quartus II software uses this feature to perform DeMorgan’s inversion for
more efficient implementation of wide OR functions. The Quartus II
Compiler can use a NOT-gate push-back technique to emulate an
asynchronous preset. Figure 14 shows the APEX II macrocell.
Altera Corporation
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APEX II Programmable Logic Device Family Data Sheet
Figure 14. APEX II Macrocell
ESB-Wide ESB-Wide
ESB-Wide
Clears Clock Enables
Clocks
2
2
2
Parallel Logic
Expanders
(From Other
Macrocells)
ProductTerm
Select
Matrix
Programmable
Register
D
Clock/
Enable
Select
Q
ESB
Output
ENA
CLRN
32 Signals
from Local
Interconnect
Clear
Select
For registered functions, each macrocell register can be programmed
individually to implement D, T, JK, or SR operation with programmable
clock control. The register can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired register type; the
Quartus II software then selects the most efficient register operation for
each registered function to optimize resource utilization. The Quartus II
software or other synthesis tools can also select the most efficient register
operation automatically when synthesizing HDL designs.
Each programmable register can be clocked by one of two ESB-wide
clocks. The ESB-wide clocks can be generated from device dedicated clock
pins, global signals, or local interconnect. Each clock also has an
associated clock enable, generated from the local interconnect. The clock
and clock enable signals are related for a particular ESB; any macrocell
using a clock also uses the associated clock enable.
If both the rising and falling edges of a clock are used in an ESB, both
ESB-wide clock signals are used.
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Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
The programmable register also supports an asynchronous clear function.
Within the ESB, two asynchronous clears are generated from global
signals and the local interconnect. Each macrocell can either choose
between the two asynchronous clear signals or choose to not be cleared.
Either of the two clear signals can be inverted within the ESB. Figure 15
shows the ESB control logic when implementing product-terms.
Figure 15. ESB Product-Term Mode Control Logic
Dedicated
Clocks
8
Global
Signals
4
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
CLK2
CLKENA2
CLK1
CLKENA1 CLR2
CLR1
Parallel Expanders
Parallel expanders are unused product terms that can be allocated to a
neighboring macrocell to implement fast, complex logic functions.
Parallel expanders allow up to 32 product terms to feed the macrocell OR
logic directly, with two product terms provided by the macrocell and
30 parallel expanders provided by the neighboring macrocells in the ESB.
The Quartus II Compiler can allocate up to 15 sets of up to two parallel
expanders per set to the macrocells automatically. Each set of two parallel
expanders incurs a small, incremental timing delay. Figure 16 shows the
APEX II parallel expanders.
Altera Corporation
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APEX II Programmable Logic Device Family Data Sheet
Figure 16. APEX II Parallel Expanders
From
Previous
Macrocell
ProductTerm
Select
Matrix
Macrocell
ProductTerm Logic
Parallel Expander
Switch
ProductTerm
Select
Matrix
Macrocell
ProductTerm Logic
Parallel Expander
Switch
32 Signals from
Local Interconnect
Embedded
System Block
To Next
Macrocell
The ESB can implement various types of memory blocks, including DualPort+ RAM (bidirectional dual-port RAM), dual- and single-port RAM,
ROM, FIFO, and CAM blocks.
The ESB includes input and output registers; the input registers
synchronize writes, and the output registers can pipeline designs to
improve system performance. The ESB offers a bidirectional, dual-port
mode, which supports any combination of two port operations: two reads,
two writes, or one read and one write at two different clock frequencies.
Figure 17 shows the ESB block diagram.
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Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Figure 17. Bidirectional Dual-Port Memory Configuration
A
dataA[ ]
addressA[ ]
wrenA
clockA
clockenA
qA[ ]
aclrA
B
dataB[ ]
addressB[ ]
wrenB
clockB
clockenB
qB[ ]
aclrB
In addition to bidirectional dual-port memory, the ESB also supports
dual-port, and single-port RAM. Dual-port memory supports a
simultaneous read and write. Single-port memory supports independent
read and write. Figure 18 shows these different RAM memory port
configurations for an ESB.
Figure 18. Dual- & Single-Port Memory Configurations
Dual-Port Memory
data[ ]
wraddress[ ]
wren
inclock
inclocken
inaclr
rdaddress[ ]
rden
q[ ]
outclock
outclocken
outaclr
Single-Port Memory (1)
data[ ]
address[ ]
wren
inclock
inclocken
inaclr
q[ ]
outclock
outclocken
outaclr
Note to Figure 18:
(1)
Altera Corporation
Two single-port memory blocks can be implemented in a single ESB.
29
APEX II Programmable Logic Device Family Data Sheet
The ESB also enables variable width data ports for reading and writing to
the RAM ports in dual-port RAM configuration. For example, the ESB can
be written in 1× mode at port A while being read in 16× mode from port B.
Table 6 lists the supported variable width configurations for an ESB in
dual-port mode.
Table 6. Variable Width Configurations for Dual-Port RAM
Read Port Width
Write Port Width
1 bit
2 bits, 4 bits, 8 bits, or 16 bits
2 bits, 4 bits, 8 bits, or 16 bits
1 bit
ESBs can implement synchronous RAM, which is easier to use than
asynchronous RAM. A circuit using asynchronous RAM must generate
the RAM write enable (WE) signal while ensuring that its data and address
signals meet setup and hold time specifications relative to the WE signal.
In contrast, the ESB’s synchronous RAM generates its own WE signal and
is self-timed with respect to the global clock. Circuits using the ESB’s selftimed RAM only need to meet the setup and hold time specifications of
the global clock.
ESB inputs are driven by the adjacent local interconnect, which in turn can
be driven by the MegaLAB or FastTrack interconnects. Because the ESB
can be driven by the local interconnect, an adjacent LE can drive it directly
for fast memory access. ESB outputs drive the MegaLAB and FastTrack
interconnects and the local interconnect for fast connection to adjacent LEs
or for fast feedback product-term logic.
When implementing memory, each ESB can be configured in any of the
following sizes: 512 × 8, 1,024 × 4, 2,048 × 2, or 4,096 × 1. For dual-port and
single-port modes, the ESB can be configured for 256 × 16 in addition to
the list above.
The ESB can also be split in half and used for two independent 2,048-bit
single-port RAM blocks. The two independent RAM blocks must have
identical configurations with a maximum width of 256 × 8. For example,
one half of the ESB can be used as a 256 × 8 single-port memory while the
other half is also used for a 256 × 8 single-port memory. This effectively
doubles the number of RAM blocks an APEX II device can implement for
its given number of ESBs. The Quartus II software automatically merges
two logical memory functions in a design into an ESB; the designer does
not need to merge the functions manually.
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Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
By combining multiple ESBs, the Quartus II software implements larger
memory blocks automatically. For example, two 256 × 16 RAM blocks can
be combined to form a 256 x 32 RAM block, and two 512 × 8 RAM blocks
can be combined to form a 512 × 16 RAM block. Memory performance
does not degrade for memory blocks up to 4,096 words deep. Each ESB
can implement a 4,096-word-deep memory; the ESBs are used in parallel,
eliminating the need for any external control logic that would increase
delays. To create a high-speed memory block more than 4,096-words
deep, the Quartus II software automatically combines ESBs with LE
control logic.
Input/Output Clock Mode
The ESB implements input/output clock mode for both dual-port and
bidirectional dual-port memory. An ESB using input/output clock mode
can use up to two clocks. On each of the two ports, A or B, one clock
controls all registers for inputs into the ESB: data input, WREN, read
address, and write address. The other clock controls the ESB data output
registers. Each ESB port, A or B, also supports independent read clock
enable, write clock enable, and asynchronous clear signals. Input/output
clock mode is commonly used for applications where the reads and writes
occur at the same system frequency, but require different clock enable
signals for the input and output registers. Figure 19 shows the ESB in
input/output clock mode.
Altera Corporation
31
outclock
inclock
inclkenA
outclkenA
wrenA
4
ENA
D
ENA
D
ENA
D
Q
Q
Q
Write
Pulse
Generator
Q
qA[]
qB[]
Q
D
ENA
Data Out[]
Data Out[]
Address B
Data In
B
Write/Read
Enable
ENA
D
RAM/ROM
256 × 16 (2)
512 × 8
1,024 × 4
2,048 × 2
4,096 × 1
Write/Read
Enable
Address A
Data In
A
Write
Pulse
Generator
Q
Q
Q
D
ENA
D
D
ENA
ENA
6
4
outclock
inclock
inclkenB
outclkenB
wrenB
wraddressB[ ]
dataB[ ]
Figure 19. ESB in Input/Output Clock Mode
addressA[ ]
dataA[ ]
8
Four Dedicated Inputs & Global Signals
Eight Dedicated Clocks
APEX II Programmable Logic Device Family Data Sheet
Note (1)
Notes to Figure 19:
(1)
(2)
All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset.
This configuration is not supported for bidirectional dual-port configuration.
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APEX II Programmable Logic Device Family Data Sheet
In addition to the input/output mode clocking scheme, the clock
connections to the various ESB input/output registers are customizable in
the MegaWizard® Plug-In Manager.
Single-Port Mode
The APEX II ESB also supports a single-port mode, which is used when
simultaneous reads and writes are not required. See Figure 20. A single
ESB can support up to two single-port mode RAMs.
Figure 20. ESB in Single-Port Mode
Note (1)
Dedicated Fast
Global Signals
Dedicated Clocks
8
RAM/ROM
256 × 16
512 × 8
1,024 × 4
Data In
2,048 × 2
4,096 × 1
4
data[ ]
D
Q
ENA
Data Out
D
Q
ENA
To FastTrack
Interconnect
Address
address[ ]
D
Q
ENA
wren
outclken
inclken
inclock
Write Enable
D
Q
ENA
Write
Pulse
Generator
outclock
Note to Figure 20:
(1)
All registers can be asynchronously cleared by ESB local interconnect signals, global signals, or chip-wide reset.
Altera Corporation
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APEX II Programmable Logic Device Family Data Sheet
Content-Addressable Memory
APEX II devices can implement CAM in ESBs. CAM can be thought of as
the inverse of RAM. RAM stores data in a specific location; when the
system submits an address, the RAM block provides the data. Conversely,
when the system submits data to CAM, the CAM block provides the
address where the data is found. For example, if the data FA12 is stored
in address 14, the CAM outputs 14 when FA12 is driven into it.
CAM is used for high-speed search operations. When searching for data
within a RAM block, the search is performed serially. Thus, finding a
particular data word can take many cycles. CAM searches all addresses in
parallel and outputs the address storing a particular word. When a match
is found, a match flag is set high. CAM is ideally suited for applications
such as Ethernet address lookup, data compression, pattern recognition,
cache tags, fast routing table lookup, and high-bandwidth address
filtering. Figure 21 shows the CAM block diagram.
Figure 21. CAM Block Diagram
data[ ]
wraddress[ ]
wren
inclock
inclocken
inaclr
data_address[ ]
match
outclock
outclocken
outaclr
The APEX II on-chip CAM provides faster system performance than
traditional discrete CAM. Integrating CAM and logic into the APEX II
device eliminates off-chip and on-chip delays, improving system
performance.
When in CAM mode, the ESB implements a 32-word, 32-bit CAM. Wider
or deeper CAM, such as a 32-word, 64-bit or 128-word, 32-bit block, can
be implemented by combining multiple CAM blocks with some ancillary
logic implemented in LEs. The Quartus II software automatically
combines ESBs and LEs to create larger CAM blocks.
CAM supports writing “don’t care” bits into words of the memory. The
don’t-care bit can be used as a mask for CAM comparisons; any bit set to
don’t-care has no effect on matches.
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Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
CAM can generate outputs in three different modes: single-match mode,
multiple-match mode, and fast multiple-match mode. In each mode, the
ESB outputs the matched data’s location as an encoded or unencoded
address. When encoded, the ESB outputs an encoded address of the data’s
location. For instance, if the data is located in address 12, the ESB output
is 12. When unencoded, each ESB port uses its 16 outputs to show the
location of the data over two clock cycles. In this case, if the data is located
in address 12, the 12th output line goes high. Figures 21 and 22 show the
encoded CAM outputs and unencoded CAM outputs, respectively.
Figure 22. Encoded CAM Address Outputs
CAM
addr[15..0] = 12
data[31..0] = 45
Data
Address
15
27
45
85
10
11
12
13
Encoded Output
match = 1
Figure 23. Unencoded CAM Address Outputs
q0
CAM
data[30..0] =45 (1)
select (2)
Data
Address
15
27
45
85
10
11
12
13
q12
q13
Unencoded outputs.
q12 goes high to
signify a match.
q14
q15
Notes to Figures 22 and 23:
(1)
(2)
For an unencoded output, the ESB only supports 31 input data bits. One input bit
is used by the select line to choose one of the two banks of 16 outputs.
If the select input is a 1, then CAM outputs odd words between 1 through 15. If
the select input is a 0, CAM outputs even words between 0 through 14.
In single-match mode, it takes two clock cycles to write into CAM, but
only one clock cycle to read from CAM. In this mode, both encoded and
unencoded outputs are available without external logic. Single-match
mode is better suited for designs without duplicate data in the memory.
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APEX II Programmable Logic Device Family Data Sheet
If the same data is written into multiple locations in the memory, a CAM
block can be used in multiple-match or fast multiple-match modes. The
ESB outputs the matched data’s locations as an encoded or unencoded
address. In multiple-match mode, it takes two clock cycles to write into a
CAM block. For reading, there are 16 outputs from each ESB at each clock
cycle. Therefore, it takes two clock cycles to represent the 32 words from
a single ESB port. In this mode, encoded and unencoded outputs are
available. To implement the encoded version, the Quartus II software
adds a priority encoder with LEs. Fast multiple-match is identical to the
multiple match mode, however, it only takes one clock cycle to read from
a CAM block and generate valid outputs. To do this, the entire ESB is used
to represent 16 outputs. In fast multiple-match mode, the ESB can
implement a maximum CAM block size of 16 words.
A CAM block can be pre-loaded with data during configuration, or it can
be written during system operation. In most cases, two clock cycles are
required to write each word into CAM. When don’t-care bits are used, a
third clock cycle is required.
f
For more information on CAM, see Application Note 119 (Implementing
High-Speed Search Applications with APEX CAM).
Driving Signals to the ESB
ESBs provide flexible options for driving control signals. Different clocks
can be used for the ESB inputs and outputs. Registers can be inserted
independently on the data input, data output, read address, write
address, WE, and RE signals. The global signals and the local interconnect
can drive the WE and RE signals. The global signals, dedicated clock pins,
and local interconnects can drive the ESB clock signals. Because the LEs
drive the local interconnect, the LEs can control the WE and RE signals and
the ESB clock, clock enable, and synchronous clear signals. Figure 24
shows the ESB control signal generation logic.
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Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Figure 24. ESB Control Signal Generation
Dedicated
Clocks
Fast Global
Signals
8
4
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
INCLKENA
RDEN
WREN INCLOCK
OUTCLKENA
OUTCLOCK
INCLR OUTCLR
An ESB is fed by the local interconnect, which is driven by adjacent LEs
(for high-speed connection to the ESB) or the MegaLAB interconnect. The
ESB can drive the local, MegaLAB, or FastTrack interconnect routing
structure to drive LEs and IOEs in the same MegaLAB structure or
anywhere in the device.
Implementing Logic in ROM
In addition to implementing logic with product terms, the ESB can
implement logic functions when it is programmed with a read-only
pattern during configuration, creating a large LUT. With LUTs,
combinatorial functions are implemented by looking up the results, rather
than by computing them. This implementation of combinatorial functions
can be faster than using algorithms implemented in general logic, a
performance advantage that is further enhanced by the fast access times
of ESBs. The large capacity of ESBs enables designers to implement
complex functions in one logic level without the routing delays associated
with linked LEs or distributed RAM blocks. Parameterized functions such
as LPM functions can take advantage of the ESB automatically. Further,
the Quartus II software can implement portions of a design with ESBs
where appropriate.
Altera Corporation
37
APEX II Programmable Logic Device Family Data Sheet
Programmable Speed/Power Control
APEX II ESBs offer a high-speed mode that supports fast operation on an
ESB-by-ESB basis. When high speed is not required, this feature can be
turned off to reduce the ESB’s power dissipation by up to 50%. ESBs that
run at low power incur a nominal timing delay adder. This Turbo BitTM
option is available for ESBs that implement product-term logic or memory
functions. An ESB that is not used will be powered down so that it does
not consume DC current.
Designers can program each ESB in the APEX II device for either highspeed or low-power operation. As a result, speed-critical paths in the
design can run at high speed, while the remaining paths operate at
reduced power.
I/O Structure
38
The IOE in APEX II devices contains a bidirectional I/O buffer, six
registers, and a latch for a complete embedded bidirectional single data
rate or DDR IOE. Figure 25 shows the structure of the APEX II IOE. The
IOE contains two input registers (plus a latch), two output registers, and
two output enable registers. Both input registers and the latch can be used
for capturing DDR input. Both output registers can be used to drive DDR
outputs. The output enable (OE) register can be used for fast clock-tooutput enable timing. The negative edge-clocked OE register is used for
DDR SDRAM interfacing. The Quartus II software automatically
duplicates a single OE register that controls multiple output or
bidirectional pins.
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Figure 25. APEX II IOE Structure
Logic Array
OE Register
D
OE
Q
OE Register
D
Q
Output Register
Output A
D
Q
CLK
Output Register
Output B
D
Q
Input Register
D
Q
Input A
Input B
Input Register
D
Q
Input Latch
D
Q
ENA
The IOEs are located around the periphery of the APEX II device. Each
IOE drives a row, column, MegaLAB, or local interconnect when used as
an input or bidirectional pin. A row IOE can drive a local, MegaLAB, row,
and column interconnect; a column IOE can drive the FastTrack or column
interconnect. Figure 26 shows how a row IOE connects to the
interconnect.
Altera Corporation
39
APEX II Programmable Logic Device Family Data Sheet
Figure 26. Row IOE Connection to the Interconnect
Row Interconnect
Any LE can drive a
pin through the row,
column, and MegaLAB
interconnect.
MegaLAB Interconnect
IOE
LAB
Each IOE can drive local,
MegaLAB, row, and column
interconnect. Each IOE data
and OE signal is driven by
the local interconnect.
IOE
An LE can drive a pin through the
local interconnect for faster
clock-to-output times.
Figure 27 shows how a column IOE connects to the interconnect.
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Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Figure 27. Column IOE Connection to the Interconnect
Each IOE can drive column and FastRow
interconnects. Each IOE data and
OE signal is driven by local interconnect.
IOE
IOE
An LE or ESB can drive a
pin through a local
interconnect for faster
clock-to-output times.
LAB
Any LE or ESB can drive
a column pin through a
row, column, and MegaLAB
interconnect.
Row Interconnect
Column Interconnect
MegaLAB Interconnect
FastRow interconnects connect a column I/O pin directly to the LAB local
interconnect within two MegaLAB structures. This feature provides fast
setup times for pins that drive high fan-outs with complex logic, such as
PCI designs. For fast bidirectional I/O timing, LE registers using local
routing can improve setup times and OE timing.
APEX II devices have a peripheral control bus made up of 12 signals that
drive the IOE control signals. The peripheral bus is composed of six
output enables, OE[5:0] and six clock enables, CE[5:0]. These twelve
signals can be driven from internal logic or from the Fast I/O signals.
Table 7 lists the peripheral control signal destinations.
Altera Corporation
41
APEX II Programmable Logic Device Family Data Sheet
Table 7. Peripheral Control Bus Destinations
Peripheral Bus
I/O Control Signal
Output Enable 0 [OE0]
OE
Output Enable 1 [OE1]
OE
Output Enable 2 [OE2]
OE
Output Enable 3 [OE3]
OE
Output Enable 4 [OE4]
OE
Output Enable 5 [OE5]
OE
Clock Enable 0 [CE0]
CE, CLK
Clock Enable 1 [CE1]
CE, OE
Clock Enable 2 [CE2]
CE, CLK
Clock Enable 3 [CE3]
CE, OE
Clock Enable 4 [CE4]
CE, CLR
Clock Enable 5 [CE5]
CE, CLR
In normal bidirectional operation, the input register can be used for input
data requiring fast setup times. The input register can have its own clock
input and clock enable separate from the OE and output registers. The
output register can be used for data requiring fast clock-to-output
performance. The OE register can be used for fast clock-to-output enable
timing. The OE and output register share the same clock source and the
same clock enable source from local interconnect in the associated LAB,
fast global signals, or row global signals. Figure 28 shows the IOE in
bidirectional configuration.
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Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Figure 28. APEX II IOE in Bidirectional I/O Configuration
Column, Row
or Local
Interconnect
Eight
Dedicated
Clocks
12 Peripheral
Signals
OE Register
D
Output Clock
Enable Delay
Q
Output
tZX Delay
ENA
CLRN/PRN
VCCIO
OE Register
tCO Delay
Optional
PCI Clamp
VCCIO
Programmable
Pull-Up
Chip-Wide Reset
Logic Array
to Output
Register Delay
Output Register
D
Output
Pin
Delay
Q
ENA
CLRN/PRN
Drive Strength Control
Open-Drain Output
Slew Control
Input Pin to
Logic Array Delay
Input Register
D
Input Clock
Enable Delay
Input Pin to
Input Register Delay
Bus-Hold
Circuit
Q
ENA
CLRN/PRN
The APEX II IOE includes programmable delays that can be activated to
ensure zero hold times, minimum clock-to-output times, input IOE
register-to-logic array register transfers, or logic array-to-output IOE
register transfers.
Altera Corporation
43
APEX II Programmable Logic Device Family Data Sheet
A path in which a pin directly drives a register may require the delay to
ensure zero hold time, whereas a path in which a pin drives a register
through combinatorial logic may not require the delay. Programmable
delays exist for decreasing input pin to logic array and IOE input register
delays. The Quartus II Compiler can program these delays automatically
to minimize setup time while providing a zero hold time. Delays are also
programmable for increasing the register to pin delays for output and/or
output enable registers. A programmable delay exists for increasing the
tZX delay to the output pin, which is required for ZBT interfaces. Table 8
shows the programmable delays for APEX II devices.
Table 8. APEX II Programmable Delay Chain
Programmable Delays
Quartus II Logic Option
Input pin to logic array delay (1)
Decrease input delay to internal cells
Input pin to input register delay
Decrease input delay to input register
Output propagation delay
Increase delay to output pin
Output enable register tCO delay
Increase delay to output enable pin
Output tZX delay
Increase tZX delay to output pin
Output clock enable delay
Increase output clock enable delay
Input clock enable delay
Increase input clock enable delay
Logic array to output register delay
Decrease input delay to output register
Note to Table 8:
(1)
This delay has four settings: off and three levels of delay.
The IOE registers in APEX II devices share the same source for clear or
preset. The designer can program preset and clear for each individual
IOE. The registers can be programmed to power up high or low after
configuration is complete. If programmed to power up low, an
asynchronous clear can control the registers. If programmed to power up
high, an asynchronous preset can control the registers. This feature
prevents the inadvertent activation of another device’s active-low input
upon power-up. If one register in an IOE uses a preset or clear signal then
all registers in the IOE must use that preset or clear signal.
Double Data Rate I/O
APEX II devices have six-register IOEs which support DDR interfacing by
clocking data on both positive and negative clock edges. The IOEs in
APEX II devices support DDR inputs, DDR outputs, and bidirectional
DDR modes.
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Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
When using the IOE for DDR inputs, the two input registers are used to
clock double rate input data on alternating edges. An input latch is also
used within the IOE for DDR input acquisition. The latch holds the data
that is present during the clock high times. This allows both bits of data to
be synchronous to the same clock edge (either rising or falling). Figure 29
shows an IOE configured for DDR input.
Figure 29. APEX II IOE in DDR Input I/O Configuration
Column, Row
or Local
Interconnect
VCCIO
Eight
Dedicated
Clocks
Optional
PCI Clamp
12 Peripheral
Signals
VCCIO
Programmable
Pull-Up
Input Pin to Input
Register Delay
Input Register
D
Q
ENA
CLRN/PRN
Bus-Hold
Circuit
Input Clock
Enable Delay
Chip-Wide Reset
Input Register
D
Q
ENA
CLRN/PRN
Latch
D
Q
ENA
CLRN/PRN
When using the IOE for DDR outputs, the two output registers are
configured to clock two data paths from LEs on rising clock edges. These
register outputs are multiplexed by the clock to drive the output pin at a
×2 rate. One output register clocks the first bit out on the clock high time,
while the other output register clocks the second bit out on the clock low
time. Figure 30 shows the IOE configured for DDR output.
Altera Corporation
45
APEX II Programmable Logic Device Family Data Sheet
Figure 30. APEX II IOE in DDR Output I/O Configuration
Column, Row
or Local
Interconnect
Eight
Dedicated
Clocks
12 Peripheral
Signals
OE Register
D
Output
tZX Delay
Q
VCCIO
Output Clock
Enable Delay
Optional
PCI Clamp
ENA
CLRN/PRN
OE Register
tCO Delay
VCCIO
Programmable
Pull-Up
Chip-Wide Reset
OE Register
D
Q
ENA
CLRN/PRN
Logic Array
to Output
Register Delay
Output Register
D
Output Register
D
Output
Propagation
Delay
Q
ENA
CLRN/PRN
Logic Array
to Output
Register Delay
Used for
DDR SDRAM
clk
Drive Strength Control
Open-Drain Output
Slew Control
Q
ENA
CLRN/PRN
Bus-Hold
Circuit
The APEX II IOE operates in bidirectional DDR mode by combining the
DDR input and DDR output configurations.
APEX II I/O pins transfer data on a DDR bidirectional bus to support
DDR SDRAM at 167 MHz (334 Mbps). The negative-edge-clocked OE
register is used to hold the OE signal inactive until the falling edge of the
clock. This is done to meet DDR SDRAM timing requirements. QDR
SRAMs are also supported with DDR I/O pins on separate read and write
ports.
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Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Zero Bus Turnaround SRAM Interface Support
In addition to DDR SDRAM support, APEX II device I/O pins also
support interfacing with ZBT SRAM devices at up to 200 MHz. ZBT
SRAM blocks are designed to eliminate dead bus cycles when turning a
bidirectional bus around between reads and writes, or writes and reads.
ZBT allows for 100% bus utilization because ZBT SRAM can be read or
written on every clock cycle.
To avoid bus contention, the output clock-to-low-impedance time (tZX)
delay ensures that the tZX is greater than the clock-to-high-impedance
time (tXZ). Phase delay control of clocks to the OE/output and input
registers using two general-purpose PLLs enable the APEX II device to
meet ZBT tCO and tSU times.
Programmable Drive Strength
The output buffer for each APEX II device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL standard has
several levels of drive strength that the user can control. SSTL-3 class I
and II, SSTL-2 class I and II, HSTL class I and II, 3.3-V GTL+, PCI, and
PCI-X support a minimum setting. The minimum setting is the lowest
drive strength that guarantees the IOH/IOL of the standard. Using
minimum settings provides signal slew rate control to reduce system
noise and signal overshoot. Table 9 shows the possible settings for the I/O
standards with drive strength control.
Altera Corporation
47
APEX II Programmable Logic Device Family Data Sheet
Table 9. Programmable Drive Strength
I/O Standard
LVTTL (3.3 V)
IOH/IOL Current Strength
Setting
4 mA
12 mA
24 mA (default)
LVTTL (2.5 V)
2 mA
16 mA (default)
LVTTL (1.8 V)
2 mA
8mA (default)
LVTTL (1.5 V)
SSTL-3 class I and II
SSTL-2 class I and II
HSTL class I and II
GTL+ (3.3 V)
PCI
PCI-X
2 mA (default)
Minimum (default)
Open-Drain Output
APEX II devices provide an optional open-drain (equivalent to an opencollector) output for each I/O pin. This open-drain output enables the
device to provide system-level control signals (e.g., interrupt and writeenable signals) that can be asserted by any of several devices.
Slew-Rate Control
The output buffer for each APEX II device I/O pin has a programmable
output slew rate control that can be configured for low-noise or highspeed performance. A faster slew rate provides high-speed transitions for
high-performance systems. However, these fast transitions may introduce
noise transients into the system. A slow slew rate reduces system noise,
but adds a nominal delay to rising and falling edges. Each I/O pin has an
individual slew rate control, allowing the designer to specify the slew rate
on a pin-by-pin basis. The slew rate control affects both the rising and
falling edges.
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Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Bus Hold
Each APEX II device I/O pin provides an optional bus-hold feature. When
this feature is enabled for an I/O pin, the bus-hold circuitry weakly holds
the signal at its last driven state. By holding the last driven state of the pin
until the next input signal is present, the bus-hold feature eliminates the
need to add external pull-up or pull-down resistors to hold a signal level
when the bus is tri-stated. The bus-hold circuitry also pulls undriven pins
away from the input threshold voltage where noise can cause unintended
high-frequency switching. This feature can be selected individually for
each I/O pin. The bus-hold output will drive no higher than VCCIO to
prevent overdriving signals. If the bus-hold feature is enabled, the
programmable pull-up option cannot be used. The bus-hold feature
should also be disabled if open-drain outputs are used with the GTL+ I/O
standard.
The bus-hold circuitry weakly pulls the signal level to the last driven state
through a resistor with a nominal resistance (RBH) of approximately 7 kΩ.
Table 41 on page 74 gives specific sustaining current that will be driven
through this resistor and overdrive current that will identify the next
driven input level. This information is provided for each VCCIO voltage
level.
The bus-hold circuitry is active only after configuration. When going into
user mode, the bus-hold circuit captures the value on the pin present at
the end of configuration.
Programmable Pull-Up Resistor
Each APEX II device I/O pin provides an optional programmable pull-up
resistor during user mode. When this feature is enabled for an I/O pin, the
pull-up resistor (typically 25 kΩ) weakly holds the output to the VCCIO
level of the bank that the output pin resides in.
Dedicated Fast I/O Pins
APEX II devices incorporate dedicated bidirectional pins for signals with
high internal fanout, such as PCI control signals. These pins are called
dedicated fast I/O pins (FAST1, FAST2, FAST3, and FAST4) and can
drive the four global fast lines throughout the device, ideal for fast clock,
clock enable, preset, clear, or high fanout logic signal distribution. The
dedicated fast I/O pins have one output register and one OE register, but
they do not have input registers. The dedicated fast lines can also be
driven by a LE local interconnect to generate internal global signals.
Altera Corporation
49
APEX II Programmable Logic Device Family Data Sheet
Advanced I/O Standard Support
APEX II device IOEs support the following I/O standards:
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
50
LVTTL
LVCMOS
1.5-V
1.8-V
2.5-V
3.3-V PCI
3.3-V PCI-X
3.3-V AGP (1×, 2×)
LVDS
LVPECL
PCML
HyperTransport
GTL+
HSTL class I and II
SSTL-3 class I and II
SSTL-2 class I and II
CTT
Differential HSTL
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Table 10 describes the I/O standards supported by APEX II devices.
Table 10. APEX II Supported I/O Standards
I/O Standard
Type
Input
Reference
Voltage (VREF)
(V)
Output
Supply
Voltage
(VCCIO) (V)
Board
Termination
Voltage
(VTT) (V)
LVTTL
Single-ended
N/A
3.3
N/A
LVCMOS
Single-ended
N/A
3.3
N/A
2.5 V
Single-ended
N/A
2.5
N/A
1.8 V
Single-ended
N/A
1.8
N/A
1.5 V
Single-ended
N/A
1.5
N/A
3.3-V PCI
Single-ended
N/A
3.3
N/A
3.3-V PCI-X
Single-ended
N/A
3.3
N/A
LVDS
Differential
N/A
3.3
N/A
LVPECL
Differential
N/A
3.3
N/A
PCML
Differential
N/A
3.3
N/A
HyperTransport
Differential
N/A
2.5
N/A
Differential HSTL (1)
Differential
N/A
1.5
N/A
GTL+
Voltage referenced
1.0
N/A
1.5
HSTL class I and II
Voltage referenced
0.75
1.5
0.75
SSTL-2 class I and II
Voltage referenced
1.25
2.5
1.25
1.5
SSTL-3 class I and II
Voltage referenced
1.5
3.3
AGP (1× and 2×)
Voltage referenced
1.32
3.3
N/A
CTT
Voltage referenced
1.5
3.3
1.5
Note to Table 10:
(1)
Differential HSTL is only supported on the eight dedicated global clock pins and four dedicated high-speed PLL
clock pins.
f
For more information on I/O standards supported by APEX II devices,
see Application Note 117 (Using Selectable I/O Standards in Altera Devices).
APEX II devices contain eight I/O banks, as shown in Figure 31. Two
blocks within the right I/O banks contain circuitry to support high-speed
True-LVDS, LVPECL, PCML, and HyperTransport inputs, and another
two blocks within the left I/O banks support high-speed True-LVDS,
LVPECL, PCML, and HyperTransport outputs. All other standards are
supported by all I/O banks.
Altera Corporation
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APEX II Programmable Logic Device Family Data Sheet
Figure 31. APEX II I/O Banks
I/O banks 1 and 2 support Flexible-LVDS,
HyperTransport, and LVPECL inputs, and
regular I/O pin standards.
I/O Bank 1
I/O Bank 2
True-LVDS, LVPECL,
PCML, and HyperTransport
Output Block (2)
(1)
I/O Bank 8
True-LVDS, LVPECL,
PCML, and HyperTransport
Input Block (2)
Regular I/O Pins Support
■ 3.3-V, 2.5-V, 1.8-V, and
1.5-V LVTTL
■ 3.3-V PCI and PCI-X
■ GTL+
■ AGP
■ SSTL-2 Class I and II
■ SSTL-3 Class I and II
■ HSTL Class I and II
■ CTT
(1)
I/O Bank 3
I/O Bank 4
(1)
I/O Bank 7
(1)
Individual
Power Bus
True-LVDS, LVPECL,
PCML, and HyperTransport
Output Block (2)
I/O Bank 6
True-LVDS, LVPECL,
PCML, and HyperTransport
Input Block (2)
I/O Bank 5
I/O banks 5 and 6 support Flexible-LVDS and
HyperTransport outputs and regular I/O pin standards.
Notes to Figure 31:
(1)
(2)
For more information on placing I/O pins within LVDS blocks, refer to the “High-Speed Interface Pin Location”
section in Application Note 166 (Using High-Speed I/O Standards in APEX II Devices).
If the True-LVDS pins or the Flexible-LVDS pins are not used for high-speed differential signalling, they can
support all of the I/O standards and can be used as input, output, or bidirectional pins with V CCIO set to 3.3 V, 2.5 V,
1.8 V, or 1.5 V. However, True-LVDS pins do not support the HSTL Class II output.
Each I/O bank has its own VCCIO pins. A single device can support 1.5-V,
1.8-V, 2.5-V, and 3.3-V interfaces; each bank can support a different
standard independently. Each bank can also use a separate VREF level to
support any one of the terminated standards (such as SSTL-3)
independently.
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Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Each bank can support multiple standards with the same VCCIO for input
and output pins. Each bank can support one voltage-referenced I/O
standard, but it can support multiple I/O standards with the same VCCIO
voltage level. For example, when VCCIO is 3.3 V, a bank can support
LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs. When
the True-LVDS banks are not used for LVDS I/O pins, they support all of
the other I/O standards except HSTL Class II output.
True-LVDS Interface
APEX II devices contain dedicated circuitry for supporting differential
standards at speeds up to 1.0 Gbps. APEX II devices have dedicated
differential buffers and circuitry to support LVDS, LVPECL,
HyperTransport, and PCML I/O standards. Four dedicated high-speed
PLLs (separate from the general-purpose PLLs) multiply reference clocks
and drive high-speed differential serializer/deserializer channels. In
addition, CDS circuitry at each receiver channel corrects any fixed clockto-data skew. All APEX II devices support 36 input channels, 36 output
channels, two dedicated receiver PLLs, and two dedicated transmitter
PLLs.
The True-LVDS circuitry supports the following standards and
applications:
■
■
■
■
RapidIO
POS-PHY Level 4
Utopia IV
HyperTransport
APEX II devices support source-synchronous interfacing with LVDS,
LVPECL,PCML, or HyperTransport signaling at up to 1 Gbps. Serial
channels are transmitted and received along with a low-speed clock. The
receiving device then multiplies the clock by a factor of 1, 2, or 4 to 10. The
serialization/deserialization rate can be any number from 1, 2, or 4 to 10
and does not have to equal the clock multiplication value.
For example, an 840-Mbps LVDS channel can be received along with an
84-MHz clock. The 84-MHz clock is multiplied by 10 to drive the serial
shift register, but the register can be clocked out in parallel at 8- or 10-bits
wide at 84 or 105 MHz. See Figures 32 and 33.
Altera Corporation
53
APEX II Programmable Logic Device Family Data Sheet
Figure 32. True-LVDS Receiver Diagram
Notes (1), (2)
J Bits Wide
Receiver
Channel
RX_CLK1 (3)
Deserializer
+
–
Data to
LEs
×W
Receiver
PLL1 W
×
J
Receiver Channel 1
Receiver
Channel
+
–
Receiver Channel 2
Receiver
Channel
+
–
Receiver Channel 18
To Global
Clock
Notes to Figure 32:
(1)
(2)
(3)
54
Two sets of 18 receiver channels are located in each APEX II device. Each set of 18 channels has one receiver PLL.
W = 1, 2, 4 to 10
J = 1, 2, 4 to 10
W does not have to equal J. When J = 1 or 2, the deserializer is bypassed. When J = 2, DDR I/O registers are used.
These clock pins drive receiver PLLs only. They do not drive directly to the logic array. However, the receiver PLL
can drive the logic array via a global clock line.
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Figure 33. True-LVDS Transmitter Diagram
Notes (1), (2)
J Bits Wide
Serializer
Transmitter
Channel
Global Clock
from Receiver
or System Clock
Data from
LEs
×W
Transmitter
W
PLL1
×
J
Transmitter Channel 1
TXOUTCLOCK1
Transmitter
Channel
Transmitter Channel 2
Transmitter
Channel
Transmitter Channel 18
Notes to Figure 33:
(1)
(2)
Two sets of 18 transmitter channels are located in each APEX II device. Each set of 18 channels has one transmitter
PLL.
W = 1, 2, 4 to 10
J = 1, 2, 4 to 10
W does not have to equal J. When J = 1 or 2, the deserializer is bypassed. When J = 2, DDR I/O registers are used.
Clock-Data Synchronization
In addition to dedicated serial-to-parallel converters, APEX II True-LVDS
circuitry contains CDS circuitry in every receiver channel. The CDS
feature can be turned on or off independently for each receiver channel.
There are two modes for the CDS circuitry: single-bit mode, which
corrects a fixed clock-to-data skew of up to ±50% of the data bit period,
and multi-bit mode, which corrects any fixed clock-to-data skew.
Altera Corporation
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APEX II Programmable Logic Device Family Data Sheet
Single-Bit Mode
Single-bit CDS corrects a fixed clock-to-data skew of up to ±50% of the
data bit period, which allows receiver input skew margin (RSKM) to
increase by 50% of the data period. To use single-bit CDS, the
deserialization factor, J, must be equal to the multiplication factor, W. The
combination of allowable W/J factors and the associated CDS training
patterns automatically determine byte alignment (see Table 11).
Table 11. Single-Bit CDS Training Patterns
W/J Factor
Single-Bit CDS Pattern
10
0000011111
9
000001111
8
00001111
7
0000111
6
000111
5
00011
4
0011
Multi-Bit Mode
Multi-bit CDS corrects any fixed clock-to-data skew. This feature enables
flexible board topologies, such as an N:1 topology (see Figure 34), a switch
topology, or a matrix topology. Multi-bit CDS corrects for the skews
inherent with these topologies, making them possible to use.
56
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Figure 34. Multi-Bit CDS Supports N:1 Topology
Clock
APEX II
Device
Data
Data
APEX II
Device
APEX II
Device
Clock
APEX II
Device
Clock
Clock
When using multi-bit CDS, the J and W factors do not need to be the same
value. The byte boundary cannot be distinguished with multi-bit CDS
patterns (see Table 12). Therefore, the byte must be aligned using internal
logic. Table 12 shows the possible training patterns for multi-bit CDS.
Either pattern can be used.
Table 12. Multi-Bit CDS Patterns
W Factor
J Factor
Multi-Bit CDS Pattern
1, 2, 4 to 10
4 to 10
3 × J-bits of 010101 pattern
1, 2, 4 to 10
4 to 10
3 × J-bits of 101010 pattern
Pre-Programmed CDS
When the fixed clock-to-data skew is known, CDS can be preprogrammed into the device during configuration. If CDS is preprogrammed into the device, the training patterns do not need to be
transmitted to the receiver channels. The resolution of each preprogrammed setting is 25% of the data period, to compensate for skew up
to ±50% of the data period.
Altera Corporation
57
APEX II Programmable Logic Device Family Data Sheet
Pre-programmed CDS may also be used to resolve clock-to-data skew
greater than 50% of the bit period. However, internal logic must be used
to implement the byte alignment circuitry for this operation.
Flexible-LVDS I/O Pins
A subset of pins in the top two I/O banks supports interfacing with
Flexible-LVDS, LVPECL, and HyperTransport inputs. These
Flexible-LVDS input pins include dedicated LVDS, LVPECL, and
HyperTransport input buffers. A subset of pins in the bottom two I/O
banks supports interfacing with Flexible-LVDS and HyperTransport
outputs. These Flexible-LVDS output pins include dedicated LVDS and
HyperTransport output buffers. The Flexible-LVDS pins do not require
any external components except for 100-Ω termination resistors on
receiver channels. These pins do not contain dedicated
serialization/deserialization circuitry; therefore, internal logic is used to
perform serialization/deserialization functions.
The EP2A15 and EP2A25 devices support 56 input and 56 output
Flexible-LVDS channels. The EP2A40 and larger devices support 88 input
and 88 output Flexible-LVDS channels. All APEX II devices support the
Flexible-LVDS interface up to 400 Mbps (DDR) per channel. FlexibleLVDS pins along with the True-LVDS pins provide up to 144-Gbps total
device bandwidth. Table 13 shows the Flexible-LVDS timing
specification.
Table 13. APEX II Flexible-LVDS Timing Specification
Symbol
Timing Parameter Definition
Speed Grade
-7
Min
Unit
-8
Max
Min
-9
Max
Min
Max
Data Rate Maximum operating speed
400
311
311
Mbps
TCCS
Transmitter channel-to-channel
skew
700
900
900
ps
SW
Receiver sampling window
MultiVolt I/O
Interface
58
1,100
1,400
1,400
ps
The APEX II architecture supports the MultiVolt I/O interface feature,
which allows APEX II devices in all packages to interface with systems of
different supply voltages. The devices have one set of VCC pins for
internal operation and input buffers (VCCINT), and another set for I/O
output drivers (VCCIO).
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
The APEX II VCCINT pins must always be connected to a 1.5-V power
supply. With a 1.5-V VCCINT level, input pins are 1.5-V, 1.8-V, 2.5-V and
3.3-V tolerant. The VCCIO pins can be connected to either a 1.5-V, 1.8-V,
2.5-V or 3.3-V power supply, depending on the output requirements. The
output levels are compatible with systems of the same voltage as the
power supply (i.e., when VCCIO pins are connected to a 1.5-V power
supply, the output levels are compatible with 1.5-V systems). When
VCCIO pins are connected to a 3.3-V power supply, the output high is
3.3 V and is compatible with 3.3-V or 5.0-V systems.
Table 14 summarizes APEX II MultiVolt I/O support.
Table 14. APEX II MultiVolt I/O Support
VCCIO (V)
Note (1)
Input Signal
Output Signal
1.5 V
1.8 V
2.5 V
3.3 V
5.0 V
1.5
v
v
v
v
v
1.8
v (2)
v
v
v
v (3)
v
2.5
v (2)
v (2)
v
v
v (4)
v (4)
v
3.3
v (2)
v (2)
v
v
v (6)
v (6)
v (6)
v (5)
1.5 V
1.8 V
2.5 V
3.3 V
5.0 V
v
v
Notes to Table 14:
(1)
(2)
(3)
(4)
(5)
(6)
The PCI clamping diode must be disabled to drive an input with voltages higher than VCCIO, except for with a 5.0-V
input.
These input levels are only allowed if the input standard is set to any VREF standard (i.e., SSTL-3, SSTL-2, HSTL,
GTL+, and AGP 2×). The VREF standard inputs are powered by VCCINT. LVTTL, PCI, PCI-X, and AGP 1× standard
inputs are powered by VCCIO. As a result, input levels below the VCCIO setting cannot drive these standards.
When VCCIO = 1.8 V, an APEX II device can drive a 1.5-V device with 1.8-V tolerant inputs.
When VCCIO = 2.5 V, an APEX II device can drive a 1.5-V or 1.8-V device with 2.5-V tolerant inputs.
APEX II devices can be 5.0-V tolerant with the use of an external series resistor and enabling the PCI clamping diode.
When VCCIO = 3.3 V, an APEX II device can drive a 1.5-V, 1.8-V, or 2.5-V device with 3.3-V tolerant inputs.
Open-drain output pins with a pull-up resistor to the 5.0-V supply and a
series register to the I/O pin can drive 5.0-V CMOS input pins that require
a VIH of 3.5 V. When the pin is inactive, the trace will be pulled up to 5.0 V
by the resistor. The open-drain pin will only drive low or tri-state; it will
never drive high. The rise time is dependent on the value of the pull-up
resistor and load impedance. The IOL current specification should be
considered when selecting a pull-up resistor.
Power
Sequencing &
Hot Socketing
Altera Corporation
Because APEX II devices can be used in a mixed-voltage environment,
they have been designed specifically for any possible power-up sequence.
Therefore, the VCCIO and VCCINT power supplies may be powered in any
order.
59
APEX II Programmable Logic Device Family Data Sheet
Signals can be driven into APEX II devices before and during power-up
without damaging the device. In addition, APEX II devices do not drive
out during power-up. Once operating conditions are reached and the
device is configured, APEX II devices operate as specified by the user.
GeneralPurpose PLLs
APEX II devices have ClockLock, ClockBoost, and ClockShift features,
which use four general-purpose PLLs (separate from the four dedicated
True-LVDS PLLs) to provide clock management and clock-frequency
synthesis. These PLLs allow designers to increase performance and
provide clock-frequency synthesis. The PLL reduces the clock delay
within a device. This reduction minimizes clock-to-output and setup
times while maintaining zero hold times. The PLLs, which provide
programmable multiplication, allow the designer to distribute a lowspeed clock and multiply that clock on-device. APEX II devices include a
high-speed clock tree: unlike ASICs, the user does not have to design and
optimize the clock tree. The PLLs work in conjunction with the APEX II
device’s high-speed clock to provide significant improvements in system
performance and bandwidth.
The PLLs in APEX II devices are enabled through the Quartus II software.
External devices are not required to use these features. Table 15 shows the
general-purpose PLL features for APEX II devices. Figure 35 shows an
APEX II general-purpose PLL.
Table 15. APEX II General-Purpose PLL Features
Number of PLLs
ClockBoost
Feature
Number of External
Clock Outputs
Number of
Feedback Inputs
4
m/(n × k, v)
8
2
Figure 35. APEX II General-Purpose PLL
Note (1)
Phase
Comparator
inclock
Voltage-Controlled
Oscillator
n
Phase Shift
Circuitry
m
k
clock0
v
clock1
fbin
60
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Note to Figure 35:
(1)
n represents the prescale divider for the PLL input. m represents the multiplier. k and v represent the different post
scale dividers for the two possible PLL outputs. m and k are integers that range from 1 to 160. n and v are integers
that range from 1 to 16.
Advanced ClockBoost Multiplication & Division
APEX II PLLs include circuitry that provides clock synthesis for eight
internal outputs and two external outputs using m/(n × output divider)
scaling. When a PLL is locked, the locked output clock aligns to the rising
edge of the input clock. The closed loop equation for Figure 35 gives an
output frequency fclock0 = (m/(n × k))fIN and fclock1 = (m/(n × v))fIN. These
equations allow the multiplication or division of clocks by a
programmable number. The Quartus II software automatically chooses
the appropriate scaling factors according to the frequency, multiplication,
and division values entered.
A single PLL in an APEX II device allows for multiple user-defined
multiplication and division ratios that are not possible even with multiple
delay-locked loops (DLLs). For example, if a frequency scaling factor of
3.75 is needed for a given input clock, a multiplication factor of 15 and a
division factor of 4 can be entered. This advanced multiplication scaling
can be performed with a single PLL, making it unnecessary to cascade
PLL outputs.
External Clock Outputs
APEX II devices have two low-jitter external clocks available for external
clock sources. Other devices on the board can use these outputs as clock
sources.
There are three modes for external clock outputs.
■
■
■
Altera Corporation
Zero Delay Buffer: The external clock output pin is phase aligned
with the clock input pin for zero delay. Multiplication,
programmable phase shift, and time delay shift are not allowed in
this configuration. The MegaWizard interface for altclklock
should be used to verify possible clock settings.
External Feedback: The external feedback input pin is phase aligned
with clock input pin. By aligning these clocks, you can actively
remove clock delay and skew between devices. This mode has the
same restrictions as zero delay buffer mode.
Normal Mode: The external clock output pin will have phase delay
relative to the clock input pin. If an internal clock is used in this mode,
the IOE register clock will be phase aligned to the input clock pin.
Multiplication is allowed with the normal mode.
61
APEX II Programmable Logic Device Family Data Sheet
ClockShift Circuitry
General-purpose PLLs in APEX II devices have ClockShift circuitry that
provides programmable phase shift. Users can enter a phase shift (in
degrees or time units) that affects all PLL outputs. Phase shifts of 90°, 180°,
and 270° can be implemented exactly. Other values of phase shifting, or
delay shifting in time units, are allowed with a resolution range of 0.5 ns
to 1.0 ns. This resolution varies with frequency input and the user-entered
multiplication and division factors. The phase shift ability is only possible
on a multiplied or divided clock if the input and output frequency have
an integer multiple relationship (i.e., fIN/fOUT or fOUT/fIN must be an
integer).
Clock Enable Signal
APEX II PLLs have a CLKLK_ENA pin for enabling/disabling all device
PLLs. When the CLKLK_ENA pin is high, the PLL drives a clock to all its
output ports. When the CLKLK_ENA pin is low, the clock0, clock1, and
extclock ports are driven by GND and all of the PLLs go out of lock.
When the CLKLK_ENA pin goes high again, the PLL relocks.
The individual enable port for each PLL is programmable. If more than
one PLL is instantiated, each one does not have to use the clock enable. To
enable/disable the device PLLs with the CLKLK_ENA pin, the inclocken
port on the altclklock instance must be connected to the CLKLK_ENA
input pin.
Lock Signals
The APEX II device PLL circuits support individual LOCK signals. The
LOCK signal drives high when the PLL has locked onto the input clock.
LOCK remains high as long as the input remains within specification. It
will go low if the input is out of specification. A LOCK pin is optional for
each PLL used in the APEX II devices; when not used, they are I/O pins.
This signal is not available internally; if it is used in the logic array, it must
be fed back in with an input pin.
SignalTap
Embedded
Logic Analyzer
62
APEX II devices include device enhancements to support the SignalTap
embedded logic analyzer. By including this circuitry, the APEX II device
provides the ability to monitor design operation over a period of time
through the IEEE Std. 1149.1 (JTAG) circuitry; a designer can analyze
internal logic at speed without bringing internal signals to the I/O pins.
This feature is particularly important for advanced packages such as
FineLine BGA packages because adding a connection to a pin during the
debugging process can be difficult after a board is designed and
manufactured.
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
All APEX II devices provide JTAG BST circuitry that complies with the
IEEE Std. 1149.1-1990 specification. JTAG boundary-scan testing can be
performed before or after configuration, but not during configuration.
APEX II devices can also use the JTAG port for configuration with the
Quartus II software or with hardware using either JamTM Standard Test
and Programming Language (STAPL) Files (.jam) or Jam Byte-Code Files
(.jbc). Finally, APEX II devices use the JTAG port to monitor the logic
operation of the device with the SignalTap embedded logic analyzer.
APEX II devices support the JTAG instructions shown in Table 16.
Table 16. APEX II JTAG Instructions
JTAG Instruction
Description
SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern to be output at the device pins.
Also used by the SignalTap embedded logic analyzer.
EXTEST (1)
Allows the external circuitry and board-level interconnections to be tested by forcing a test
pattern at the output pins and capturing test results at the input pins.
BYPASS
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data
to pass synchronously through selected devices to adjacent devices during normal device
operation.
USERCODE
Selects the 32-bit USERCODE register and places it between the TDI and TDO pins,
allowing the USERCODE to be serially shifted out of TDO.
IDCODE
Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE
to be serially shifted out of TDO.
HIGHZ (1)
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data
to pass synchronously through selected devices to adjacent devices during normal device
operation, while tri-stating all of the I/O pins.
CLAMP (1)
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data
to pass synchronously through selected devices to adjacent devices during normal device
operation while holding I/O pins to a state defined by the data in the boundary-scan
register.
ICR instructions
Used when configuring an APEX II device via the JTAG port with a MasterBlasterTM or
ByteBlasterMVTM download cable, or when using a Jam File or Jam Byte-Code File via an
embedded processor.
SignalTap
instructions
Monitors internal device operation with the SignalTap embedded logic analyzer.
Note to Table 16:
(1)
Bus hold and weak pull-up features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
The APEX II device instruction register length is 10 bits. The APEX II
device USERCODE register length is 32 bits. Tables 17 and 18 show the
boundary-scan register length and device IDCODE information for
APEX II devices.
Altera Corporation
63
APEX II Programmable Logic Device Family Data Sheet
Table 17. APEX II JTAG Boundary-Scan Register Length
Device
Boundary-Scan Register Length
EP2A15
1,524
EP2A25
1,884
EP2A40
2,328
EP2A70
3,228
Table 18. 32-Bit APEX II Device IDCODE
Device
IDCODE (32 Bits) (1)
Version
(4 Bits)
Part Number (16 Bits)
Manufacturer
Identity (11 Bits)
1 (1 Bit)
(2)
EP2A15
0000
1100 0100 0000 0000
000 0110 1110
1
EP2A25
0000
1100 0110 0000 0000
000 0110 1110
1
EP2A40
0000
1101 0000 0000 0000
000 0110 1110
1
EP2A70
0000
1110 0000 0000 0000
000 0110 1110
1
Notes to Tables 17 and 18:
(1)
(2)
The most significant bit (MSB) is on the left.
The IDCODE’s least significant bit (LSB) is always 1.
Figure 36 shows the timing requirements for the JTAG signals.
64
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Figure 36. APEX II JTAG Waveforms
TMS
TDI
t JCP
t JCH
t JCL
t JPSU
t JPH
TCK
tJPZX
t JPXZ
t JPCO
TDO
tJSH
tJSSU
Signal
to Be
Captured
Signal
to Be
Driven
tJSCO
tJSZX
tJSXZ
Table 19 shows the JTAG timing parameters and values for APEX II
devices.
Table 19. APEX II JTAG Timing Parameters & Values
Symbol
Altera Corporation
Parameter
Min
Max
100
Unit
tJCP
TCK clock period
tJCH
TCK clock high time
50
ns
ns
tJCL
TCK clock low time
50
ns
tJPSU
JTAG port setup time
20
ns
tJPH
JTAG port hold time
45
tJPCO
JTAG port clock to output
tJPZX
JTAG port high impedance to valid output
25
ns
tJPXZ
JTAG port valid output to high impedance
25
ns
tJSSU
Capture register setup time
20
tJSH
Capture register hold time
45
tJSCO
Update register clock to output
35
ns
tJSZX
Update register high impedance to valid output
35
ns
tJSXZ
Update register valid output to high impedance
35
ns
ns
25
ns
ns
ns
65
APEX II Programmable Logic Device Family Data Sheet
f
For more information, see the following documents:
■
■
Generic Testing
Application Note 39 (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in
Altera Devices)
Jam Programming & Test Language Specification
Each APEX II device is functionally tested. Complete testing of each
configurable static random access memory (SRAM) bit and all logic
functionality ensures 100% yield. AC test measurements for APEX II
devices are made under conditions equivalent to those shown in
Figure 37. Multiple test patterns can be used to configure devices during
all stages of the production flow. AC test criteria include:
■
■
■
■
Power supply transients can affect AC measurements.
Simultaneous transitions of multiple outputs should be avoided for
accurate measurement.
Threshold tests must not be performed under AC conditions.
Large-amplitude, fast-ground-current transients normally occur as
the device outputs discharge the load capacitances. When these
transients flow through the parasitic inductance between the device
ground pin and the test system ground, significant reductions in
observable noise immunity can result.
Figure 37. APEX II AC Test Conditions
Device
Output
To Test
System
Device input
rise and fall
times < 3 ns
Operating
Conditions
66
C1 (includes
jig capacitance)
APEX II devices are offered in both commercial and industrial grades.
However, industrial-grade devices may have limited speed-grade
availability.
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Tables 20 through 41 provide information on absolute maximum ratings,
recommended operating conditions, and DC operating conditions for
1.5-V APEX II devices.
Table 20. APEX II Device Absolute Maximum Ratings
Symbol
VCCINT
Parameter
Notes (1), (2)
Conditions
With respect to ground (3)
Supply voltage
VCCIO
Minimum
Maximum
Unit
–0.5
2.4
V
–0.5
4.6
V
VI
DC input voltage
–0.5
4.6
V
IOUT
DC output current, per pin
–25
25
mA
TSTG
Storage temperature
No bias
–65
150
°C
TAMB
Ambient temperature
Under bias
–65
135
°C
TJ
Junction temperature
BGA packages under bias
135
°C
Table 21. APEX II Device Recommended Operating Conditions
Symbol
Parameter
Conditions
Minimum
Maximum
Unit
1.425
1.575
V
3.00 (3.135)
3.60 (3.465)
V
Supply voltage for output buffers, (4)
2.5-V operation
2.375
2.625
V
Supply voltage for output buffers, (4)
1.8-V operation
1.71
1.89
V
Supply voltage for output buffers, (4)
1.5-V operation
1.4
1.6
V
(4)
VCCINT
Supply voltage for internal logic
and input buffers
VCCIO
Supply voltage for output buffers, (4), (5)
3.3-V operation
VI
Input voltage
VO
Output voltage
TJ
Operating junction temperature
tR
Input rise time
tF
Input fall time
(3), (6)
For commercial
use
For industrial use
Altera Corporation
–0.5
4.1
V
0
VCCIO
V
0
85
°C
–40
100
°C
40
ns
40
ns
67
APEX II Programmable Logic Device Family Data Sheet
Table 22. APEX II Device DC Operating Conditions
Symbol
Parameter
Note (7)
Conditions
Minimum
Typical
Maximum
Unit
II
Input pin leakage
current
VI = VCCIO to 0 V (8)
–10
10
µA
IOZ
Tri-stated I/O pin
leakage current
VO = VCCIO to 0 V (8)
–10
10
µA
ICC0
VCC supply current
(standby) (All ESBs
in power-down
mode)
VI = ground, no load,
no toggling inputs, -7
speed grade
10
mA
VI = ground, no load,
no toggling inputs, -8,
-9 speed grades
5
mA
RCONF
Value of I/O pin pull- VCCIO = 3.0 V (9)
up resistor before
VCCIO = 2.375 V (9)
and during
VCCIO = 1.71 V (9)
configuration
20
50
kΩ
30
80
kΩ
60
150
kΩ
Table 23. LVTTL Specifications
Symbol
Parameter
Conditions
Minimum
Maximum
Units
V
VCCIO
Output supply voltage
3.0
3.6
VI H
High-level input voltage
1.7
4.1
V
VIL
Low-level input voltage
–0.5
0.8
V
II
Input pin leakage current
VIN = 0 V or VCCIO
–5
5
µA
VOH
High-level output voltage
IOH = –4 to –24 mA (10)
2.4
VOL
Low-level output voltage
IOL = 4 to 24 mA (10)
V
0.45
V
Minimum
Maximum
Units
3.0
3.6
V
Table 24. LVCMOS Specifications
Symbol
Parameter
Conditions
VCCIO
Output supply voltage
VIH
High-level input voltage
1.7
4.1
V
VIL
Low-level input voltage
–0.5
0.7
V
–10
10
µA
II
Input pin leakage current
VIN = 0 V or VCCIO
VOH
High-level output voltage
VCCIO = 3.0,
IOH = –0.1 mA
VOL
Low-level output voltage
VCCIO = 3.0,
IOL = 0.1 mA
68
VCCIO – 0.2
V
0.2
V
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Table 25. 2.5-V I/O Specifications
Symbol
Parameter
VCCIO
Output supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
II
Input pin leakage current
VOH
High-level output voltage
VOL
Low-level output voltage
Note (10)
Conditions
VIN = 0 V or VCCIO
Minimum
Maximum
Units
2.375
2.625
V
1.7
4.1
V
–0.5
0.7
V
–10
10
µA
IOH = –0.1 mA
2.1
V
IOH = –1 mA
2.0
V
IOH = –2 to –16 mA
1.7
V
IOL = 0.1 mA
0.2
V
IOL = 1 mA
0.4
V
IOL = 2 to 16 mA
0.7
V
Minimum
Maximum
Units
Table 26. 1.8-V I/O Specifications
Symbol
Parameter
Conditions
VCCIO
Output supply voltage
1.65
1.95
V
VI H
High-level input voltage
0.65 × VCCIO
4.1
V
VIL
Low-level input voltage
–0.5
0.35 × VCCIO
V
II
Input pin leakage current
VIN = 0 V or VCCIO
–10
10
µA
VOH
High-level output voltage
IOH = –2 to –8 mA (10) VCCIO – 0.45
VOL
Low-level output voltage
IOL = 2 to 8 mA (10)
0.45
V
Maximum
Units
V
Table 27. 1.5-V I/O Specifications
Symbol
Parameter
VCCIO
Output supply voltage
VI H
High-level input voltage
Conditions
VIL
Low-level input voltage
II
Input pin leakage current
VIN = 0 V or VCCIO
VOH
High-level output voltage
IOH = –2 mA (10)
VOL
Low-level output voltage
IOL = 2 mA (10)
Altera Corporation
Minimum
1.4
1.6
V
0.65 × VCCIO
4.1
V
–0.5
0.35 × VCCIO
V
–10
10
µA
0.75 × VCCIO
V
0.25 × VCCIO
V
69
APEX II Programmable Logic Device Family Data Sheet
Table 28. 3.3-V PCI Specifications
Symbol
Parameter
Conditions
Minimum
Typical
3.0
3.3
Maximum
Units
VCCIO
Output supply voltage
3.6
V
VIH
High-level input voltage
0.5 ×
VCCIO
VCCIO +
0.5
V
VIL
Low-level input voltage
–0.5
0.3 ×
VCCIO
V
II
Input pin leakage current
0 < VIN < VCCIO
–10
10
µA
VOH
High-level output voltage
IOUT = –500 µA
0.9 ×
VCCIO
VOL
Low-level output voltage
IOUT = 1,500 µA
V
0.1 ×
VCCIO
V
Table 29. PCI-X Specifications
Symbol
Parameter
Maximum
Units
3.0
3.6
V
High-level input voltage
0.5 ×
VCCIO
VCCIO +
0.5
V
VIL
Low-level input voltage
–0.5
0.35 ×
VCCIO
V
VIPU
Input pull-up voltage
IIL
Input leakage current
0 < VIN < VCCIO
–10
VOH
High-level output voltage
IOUT = –500 µA
0.9 ×
VCCIO
VOL
Low-level output voltage
IOUT = 1,500 µA
LPIN
Pin inductance
VCCIO
Output supply voltage
VIH
Conditions
Minimum
Typical
0.7 ×
VCCIO
V
10
µA
V
0.1 ×
VCCIO
V
15
nH
Maximum
Units
Table 30. GTL+ I/O Specifications
Symbol
Parameter
Conditions
Minimum
Typical
VTT
Termination voltage
1.35
1.5
1.65
V
VREF
Reference voltage
0.88
1.0
1.12
V
VREF – 0.1
V
0.65
V
VIH
High-level input voltage
VIL
Low-level input voltage
VOL
Low-level output voltage
70
VREF + 0.1
IOL = 36 mA (10)
V
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Table 31. SSTL-2 Class I Specifications
Symbol
Parameter
VCCIO
Output supply voltage
VTT
Termination voltage
VREF
Reference voltage
VIH
High-level input voltage
Conditions
VIL
Low-level input voltage
VOH
High-level output voltage
IOH = –7.6 mA
(10)
VOL
Low-level output voltage
IOL = 7.6 mA (10)
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
VREF – 0.04
VREF
VREF + 0.04
V
1.15
1.25
1.35
V
VREF + 0.18
3.0
V
–0.3
VREF – 0.18
V
VTT + 0.57
V
VTT – 0.57
V
Units
Table 32. SSTL-2 Class II Specifications
Symbol
Parameter
Conditions
VCCIO
Output supply voltage
VTT
Termination voltage
VREF
Reference voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage
IOH = –15.2 mA
(10)
VOL
Low-level output voltage
IOL = 15.2 mA
(10)
Minimum
Typical
Maximum
2.3
2.5
2.7
V
VREF – 0.04
VREF
VREF + 0.04
V
1.15
1.25
1.35
V
VREF + 0.18
VCCIO + 0.3
V
–0.3
VREF – 0.18
V
VTT + 0.76
V
VTT – 0.76
V
Table 33. SSTL-3 Class I Specifications
Symbol
Parameter
VCCIO
Output supply voltage
VTT
Termination voltage
VREF
Reference voltage
VIH
High-level input voltage
Conditions
VIL
Low-level input voltage
VOH
High-level output voltage
IOH = –8 mA (10)
VOL
Low-level output voltage
IOL = 8 mA (10)
Altera Corporation
Minimum
Typical
Maximum
Units
3.0
3.3
3.6
V
VREF – 0.05
VREF
VREF + 0.05
V
1.3
1.5
1.7
V
VREF + 0.2
VCCIO + 0.3
V
–0.3
VREF – 0.2
V
VTT + 0.6
V
VTT – 0.6
V
71
APEX II Programmable Logic Device Family Data Sheet
Table 34. SSTL-3 Class II Specifications
Symbol
Parameter
Conditions
VCCIO
Output supply voltage
VTT
Termination voltage
VREF
Reference voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage
IOH = –16 mA
(10)
VOL
Low-level output voltage
IOL = 16 mA (10)
Minimum
Typical
Maximum
Units
3.0
3.3
3.6
V
VREF – 0.05
VREF
VREF + 0.05
V
1.3
1.5
1.7
V
VREF + 0.2
VCCIO + 0.3
V
–0.3
VREF – 0.2
V
VT T + 0.8
V
VTT – 0.8
V
Units
Table 35. 3.3-V AGP 2× Specifications
Symbol
Parameter
VCCIO
Output supply voltage
VREF
Reference voltage
VIH
High-level input voltage
(11)
Conditions
Minimum
Typical
Maximum
3.15
3.3
3.45
V
0.39 × VCCIO
0.41 × VCCIO
V
0.5 × VCCIO
VCCIO + 0.5
V
0.3 × VCCIO
V
VIL
Low-level input voltage (11)
VOH
High-level output voltage
IOUT = –20 µA
VOL
Low-level output voltage
IOUT = 20 µA
II
Input pin leakage current
0 < VI N < V CCIO
–10
Conditions
Minimum
Typical
3.15
3.3
0.9 × VCCIO
3.6
V
0.1 × VCCIO
V
10
µA
Maximum
Units
Table 36. 3.3-V AGP 1× Specifications
Symbol
Parameter
VCCIO
Output supply voltage
VIH
High-level input voltage
(11)
0.5 × VCCIO
VIL
Low-level input voltage (11)
VOH
High-level output voltage
IOUT = –20 µA
VOL
Low-level output voltage
IOUT = 20 µA
II
Input pin leakage current
0 < VI N < V CCIO
72
0.9 × VCCIO
–10
3.45
V
VCCIO + 0.5
V
0.3 × VCCIO
V
3.6
V
0.1 × VCCIO
V
10
µA
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Table 37. 1.5-V HSTL Class I Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VCCIO
Output supply voltage
1.4
1.5
1.6
V
VREF
Input reference voltage
0.68
0.75
0.9
V
0.7
0.75
0.8
VTT
Termination voltage
VIH (DC)
DC high-level input voltage
VREF + 0.1
VIL (DC)
DC low-level input voltage
–0.3
VIH (AC)
AC high-level input voltage
VREF + 0.2
VIL (AC)
AC low-level input voltage
VOH
High-level output voltage
IOH = 8 mA (10)
VOL
Low-level output voltage
IOL = –8 mA (10)
V
V
VREF – 0.1
V
VREF – 0.2
V
0.4
V
Maximum
Units
V
VCCIO – 0.4
V
Table 38. 1.5-V HSTL Class II Specifications
Symbol
Parameter
Conditions
Minimum
Typical
VCCIO
Output supply voltage
1.4
1.5
1.6
V
VREF
Input reference voltage
0.68
0.75
0.9
V
0.7
0.75
0.8
VTT
Termination voltage
VIH (DC)
DC high-level input voltage
VREF + 0.1
VIL (DC)
DC low-level input voltage
–0.3
VIH (AC)
AC high-level input voltage
VREF + 0.2
VIL (AC)
AC low-level input voltage
VOH
High-level output voltage
IOH = 16 mA (10) VCCIO – 0.4
VOL
Low-level output voltage
IOL = –16 mA
(10)
V
V
VREF – 0.1
V
VREF – 0.2
V
0.4
V
Units
V
V
Table 39. 1.5-V Differential HSTL Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
1.5
1.6
VCCIO
I/O supply voltage
1.4
VDIF (DC)
DC input differential
voltage
0.2
VCM (DC)
DC common mode input
voltage
0.68
VDIF (AC)
AC differential input
voltage
0.4
Altera Corporation
V
V
0.9
V
V
73
APEX II Programmable Logic Device Family Data Sheet
Table 40. CTT I/O Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VCCIO
Output supply voltage
3.0
3.3
3.6
V
VTT/VREF
Termination and input
reference voltage
1.35
1.5
1.65
V
VREF – 0.2
V
10
µA
VREF – 0.4
V
10
µA
VIH
High-level input voltage
VIL
Low-level input voltage
II
Input pin leakage current
VREF + 0.2
0 < VIN < VCCIO
VOH
High-level output voltage
IOH = –8 mA
VOL
Low-level output voltage
IOL = 8 mA
IO
Output leakage current
(when output is high Z)
GND ð VOUT ð
VCCIO
V
–10
VREF + 0.4
V
–10
Table 41. Bus Hold Parameters
Parameter
VCCIO Level
Conditions
1.5 V
Min
Max
1.8 V
Min
Units
2.5 V
Max
Min
3.3 V
Max
Min
Max
VIN > VIL
(maximum)
30
50
70
µA
High sustaining VIN < VIH
(minimum)
current
–30
–50
–70
µA
Low sustaining
current
Low overdrive
current
0 V < VIN <
VCCIO
200
300
500
µA
High overdrive
current
0 V < VIN <
VCCIO
–200
–300
–500
µA
Notes to Tables 20 – 41:
(1)
(2)
See the Operating Requirements for Altera Devices Data Sheet.
Conditions beyond those listed in Table 20 may cause permanent damage to a device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.
(3) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to - 2 V or overshoot to 4.6 V for input
currents less than 100 mA and periods shorter than 20 ns.
(4) Maximum V CC rise time is 100 ms, and VCC must rise monotonically.
(5) VCCIO maximum and minimum conditions for LVPECL, LVDS, RapidIO, and PCML are shown in parentheses.
(6) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(7) Typical values are for T A = 25° C, VCCINT = 1.5 V, and VCCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
(8) This value is specified for normal device operation. The value may vary during power-up.
(9) Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO.
(10) Drive strength is programmable according to values in Table 9 on page 48.
(11) VREF specifies the center point of the switching range.
74
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Figures 38 and 39 show receiver input and transmitter output waveforms,
respectively, for all differential I/O standards (LVDS, 3.3-V PCML,
LVPECL, and HyperTransport technology).
Figure 38. Receiver Input Waveforms for Differential I/O Standards
Single-Ended Waveform
Positive Channel (p) = VIH
±VID
Negative Channel (n) = VIL
VCM
Ground
Differential Waveform
+VID
p−n=0V
VID (Peak-to-Peak)
− VID
Figure 39. Transmitter Output Waveforms for Differential I/O Standards
Single-Ended Waveform
Positive Channel (p) = VOH
±VOD
Negative Channel (n) = VOL
VCM
Ground
Differential Waveform
+VOD
p−n=0V
VSS (1)
− VOD
Note to Figure 39:
(1)
VSS: steady-state differential output voltage.
Tables 42 through 45 provide information on absolute maximum ratings,
recommended operating conditions, and DC operating conditions for
1.5-V APEX II devices.
Altera Corporation
75
APEX II Programmable Logic Device Family Data Sheet
Table 42. 3.3-V LVDS I/O Specifications
Symbol
Parameter
Conditions
VCCIO
I/O supply voltage
VOD
Differential output voltage
RL = 100 Ω
∆ VOD
Change in VOD between
high and low
RL = 100 Ω
VOS
Output Offset voltage
RL = 100 Ω
∆ VOS
Change in VOS between
high and low
RL = 100 Ω
VTH
Differential input threshold VCM = 1.2 V
VIN
RL
Minimum
Typical
3.135
3.3
250
1.125
1.25
Maximum
Units
3.465
V
850 (1)
mV
50
mV
1.375
V
50
mV
–100
100
mV
Receiver input voltage
range
0.0
2.4
V
Receiver differential input
resistor (external to
APEX II devices)
90
100
110
Ω
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VCCIO –
0.3
V
Table 43. 3.3-V PCML Specifications
Symbol
Parameter
VCCIO
I/O supply voltage
VIL
Low-level input voltage
Conditions
VIH
High-level input voltage
VCCIO
VOL
Low-level output voltage
VCCIO –
0.6
VCCIO –
0.3
V
V
VOH
High-level output voltage
VCCIO
VCCIO –
0.3
V
600
mV
VT
Output termination voltage
VOD
Differential output voltage
tR
Rise time (20 to 80%)
85
325
ps
tF
Fall time (20 to 80%)
85
325
ps
RO
Output load
RL
Receiver differential input
resistor
76
VCCIO
300
450
V
Ω
100
45
50
55
Ω
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Table 44. LVPECL Specifications
Symbol
Note (2)
Parameter
Conditions
Minimum
Typical
3.135
3.3
Maximum
Units
VCCIO
I/O supply voltage
3.465
V
VIL
Low-level input voltage
800
2,000
mV
VIH
High-level input voltage
2,100
VCCIO
mV
VOL
Low-level output voltage
1,450
1,650
mV
VOH
High-level output voltage
2,275
2,420
mV
VID
Differential input voltage
100
600
2,500
mV
VOD
Differential output voltage
625
800
970
mV
tR
Rise time (20 to 80%)
85
325
ps
tF
Fall time (20 to 80%)
85
325
ps
Typical
Maximum
Units
2.375
2.5
2.625
V
380
600
820
mV
500
600
700
mV
Table 45. HyperTransport Specifications
Symbol
Parameter
Conditions
Minimum
VCCIO
I/O supply voltage
VOD
Differential output voltage
VOCM
Output common mode
voltage
VID
Differential input voltage
300
600
900
mV
VICM
Input common mode
voltage
450
600
750
mV
RL
Receiver differential input
resistor
90
100
110
Ω
RTT = 100 Ω
Notes to Tables 42 – 45:
(1)
(2)
Maximum VOD is measured under static conditions.
When APEX II devices drive LVPECL signals, the APEX II LVPECL outputs must be terminated with a resistor
network.
Capacitance
Altera Corporation
Table 46 and Figure 40 provide information on APEX II device
capacitance.
77
APEX II Programmable Logic Device Family Data Sheet
Table 46. APEX II Device Capacitance
Symbol
Parameter
Conditions
Minimum
Maximum
Unit
CIN
Input capacitance
VIN = 0 V,
f = 1.0 MHz
(1)
pF
CINCLK
Input capacitance on
dedicated clock pin
VIN = 0 V,
f = 1.0 MHz
12
pF
COUT
Output capacitance
VIN = 0 V,
f = 1.0 MHz
(1)
pF
Note to Table 46:
(1)
See Figure 40.
Figure 40. APEX II Maximum Input & Output Pin Capacitance
CIN = 10 pF
I/O Bank 1
I/O Bank 2
I/O Bank 8
I/O Bank 3
CIN = 12 pF
CIN = 7 pF
I/O Bank 7
I/O Bank 4
I/O Bank 6
I/O Bank 5
CIN = 15 pF
78
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Timing Model
The high-performance FastTrack and MegaLAB interconnect routing
structures ensure predictable performance, and accurate simulation and
timing analysis. In contrast, the unpredictable performance of FPGAs is
caused by their segmented connection scheme.
All specifications are always representative of worst-case supply voltage
and junction temperature conditions. All output-pin-timing specifications
are reported for maximum drive strength.
Figure 41 shows the fMAX timing model for APEX II devices. These
parameters can be used to estimate fMAX for multiple levels of logic.
However, the Quartus II software timing analysis provides more accurate
timing information because the Quartus II software usually has more upto-date timing information than the data sheet until the timing model is
final. Also, the Quartus II software can model delays caused by loading
and distance effects more accurately than by using the numbers in this
data sheet.
Altera Corporation
79
APEX II Programmable Logic Device Family Data Sheet
Figure 41. fMAX Timing Model
LE
Routing Delay
t SU
t F1—4
tH
t F5—20
t CO
t F20+
t LUT
ESB
t ESBARC
t ESBSRC
t ESBAWC
t ESBSWC
t ESBWASU
t ESBWDSU
t ESBSRASU
t ESBWESU
t ESBDATASU
t ESBWADDRSU
t ESBRADDRSU
t ESBDATACO1
t ESBDATACO2
t ESBDD
t PD
t PTERMSU
t PTERMCO
80
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Figure 42 shows the timing model for bi-directional, input, and output
IOE timing.
Figure 42. Synchronous External TIming Model
OE Register (1)
D
Dedicated
Clock
PRN
Q
CLRN
tXZ
tZX
tOUTCO
Output IOE Register (2)
D
PRN
Q
CLRN
Bidirectional Pin
tINSU
tINH
Input Register (3)
PRN
D
Q
CLRN
Notes to Figure 42:
(1)
(2)
(3)
The output enable register is in the IOE and is controlled by the
“Fast Output Enable Register = ON” option in the Quartus II software.
The output register is in the IOE and is controlled by the
“Fast Output Register = ON” option in the Quartus II software.
The input register is in the IOE and is controlled by the “Fast Input Register = ON”
option in the Quartus II software.
Tables 47 through 50 show APEX II LE, ESB, and routing delays and
minimum pulse-width timing parameters for the fMAX timing model.
Table 47. APEX II fMAX LE Timing Parameters
Symbol
Parameter
tSU
LE register setup time before clock
tH
LE register hold time before clock
tCO
LE register clock-to-output delay
tLUT
LUT delay for data-in to data-out
Altera Corporation
81
APEX II Programmable Logic Device Family Data Sheet
Table 48. APEX II fMAX ESB Timing Parameters
Symbol
Parameter
tESBARC
ESB asynchronous read cycle time
tESBSRC
ESB synchronous read cycle time
tESBAWC
ESB asynchronous write cycle time
tESBSWC
ESB synchronous write cycle time
tESBWASU
ESB write address setup time with respect to WE
tESBWAH
ESB write address hold time with respect to WE
tESBWDSU
ESB data setup time with respect to WE
tESBWDH
ESB data hold time with respect to WE
tESBRASU
ESB read address setup time with respect to RE
tESBRAH
ESB read address hold time with respect to RE
tESBWESU
ESB WE setup time before clock when using input register
tESBDATASU
ESB data setup time before clock when using input register
tESBWADDRSU
ESB write address setup time before clock when using input registers
tESBRADDRSU
ESB read address setup time before clock when using input registers
tESBDATACO1
ESB clock-to-output delay when using output registers
tESBDATACO2
ESB clock-to-output delay without output registers
tESBDD
ESB data-in to data-out delay for RAM mode
tPD
ESB macrocell input to non-registered output
tPTERMSU
ESB macrocell register setup time before clock
tPTERMCO
ESB macrocell register clock-to-output delay
Figure shows the dual-port RAM timing microparameter waveform.
82
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Figure 43. Dual-Port RAM Timing Microparameter Waveform
wrclock
tESBWEH
tESBWESU
wren
tESBADDRH
tESBADDRSU
wraddress
an-1
an
a0
a1
a2
a3
a4
a5
a6
din0
din1
din2
din3
din4
din5
din6
tESBDATAH
data-in
din-1
din
tESBDATASU
rdclock
tESBREH
tESBRESU
rden
tESBSRC
rdaddress
bn
b1
b0
b2
b3
tESBDATACO1
reg_data-out
doutn-1
doutn-2
doutn
dout0
tESBDATACO2
unreg_data-out
doutn-1
doutn
dout0
Table 49. APEX II fMAX Routing Delays
Symbol
Parameter
tF1-4
Fan-out delay estimate using local interconnect; use to estimate routing delay for a signal
with fan-out of 1 to 4
tF5-20
Fan-out delay estimate using MegaLab interconnect; use to estimate routing delay for a
signal with fan-out of 5 to 20
tF20+
Fan-out delay estimate using FastTrack interconnect; use to estimate routing delay for a
signal with fan-out greater than 20
Altera Corporation
83
APEX II Programmable Logic Device Family Data Sheet
Table 50. APEX II Minimum Pulse Width Timing Parameters
Symbol
Parameter
tCH
Minimum clock high time from clock pin
tCL
Minimum clock low time from clock pin
tCLRP
LE clear pulse width
tPREP
LE preset pulse width
tESBCH
Clock high time
tESBCL
Clock low time
tESBWP
Write pulse width
tESBRP
Read pulse width
Table 51. APEX II External Timing Parameters
Symbol
Note (1)
Parameter
Conditions
tINSU
Setup time with global clock at IOE input register
tINH
Hold time with global clock at IOE input register
tOUTCO
Clock-to-output delay with global clock at IOE output register C1 = 35 pF
tXZ
Clock-to-output buffer disable delay
tZX
Clock-to-output buffer enable delay
tINSUPLL
Setup time with PLL clock at IOE input register
tINHPLL
Hold time with PLL clock at IOE input register
tOUTCOPLL
Clock-to-output delay with PLL clock at IOE output register
tXZPLL
PLL clock-to-output buffer disable delay
tZXPLL
PLL clock-to-output buffer enable delay
Slow slew rate = OFF
C1 = 35 pF
Slow slew rate = OFF
Note to Table 51:
(1)
84
External timing parameters are factory tested, worst-case values specified by Altera. These timing parameters are
sample-tested only.
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Tables 52 through 67 show the APEX II device fMAX and functional timing
parameters.
Table 52. EP2A15 fMAX LE Timing Parameters
Symbol
-7 Speed Grade
-8 Speed Grade
-9 Speed Grade
Min
Min
Min
tSU
0.25
tH
0.25
Max
Max
0.29
Max
0.33
0.29
Unit
ns
0.33
ns
tCO
0.18
0.20
0.23
ns
tLUT
0.53
0.61
0.70
ns
Table 53. EP2A15 fMAX ESB Timing Parameters
Symbol
-7 Speed Grade
-8 Speed Grade
-9 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tESBARC
1.28
1.47
1.69
ns
tESBSRC
2.49
2.86
3.29
ns
tESBAWC
2.20
2.53
2.91
ns
tESBSWC
3.02
3.47
3.99
ns
tESBWASU
− 0.55
− 0.64
− 0.73
ns
tESBWAH
0.15
0.18
0.20
ns
tESBWDSU
0.37
0.43
0.49
ns
tESBWDH
0.16
0.18
0.21
ns
tESBRASU
0.84
0.96
1.11
ns
tESBRAH
0.00
0.00
0.00
ns
tESBWESU
0.14
0.16
0.19
ns
tESBDATASU
− 0.02
− 0.03
− 0.03
ns
tESBWADDRSU
− 0.40
− 0.46
− 0.53
ns
tESBRADDRSU
− 0.38
− 0.44
− 0.51
ns
tESBDATACO1
1.30
1.50
1.72
ns
tESBDATACO2
1.84
2.12
2.44
ns
tESBDD
2.42
2.78
3.19
ns
tPD
1.69
1.94
2.23
ns
1.08
ns
tPTERMSU
tPTERMCO
Altera Corporation
1.10
1.26
0.82
1.45
0.94
ns
85
APEX II Programmable Logic Device Family Data Sheet
Table 54. EP2A15 fMAX Routing Delays
Symbol
-7 Speed Grade
-8 Speed Grade
-9 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tF1-4
0.19
0.21
0.25
ns
tF5-20
0.64
0.73
0.84
ns
tF20+
1.18
1.35
1.56
ns
Table 55. EP2A15 Minimum Pulse Width Timing Parameters
Symbol
-7 Speed Grade
-8 Speed Grade
-9 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tCH
1.00
1.15
1.32
ns
tCL
1.00
1.15
1.32
ns
tCLRP
0.13
0.15
0.17
ns
tPREP
0.13
0.15
0.17
ns
tESBCH
1.00
1.15
1.32
ns
tESBCL
1.00
1.15
1.32
ns
tESBWP
1.12
1.28
1.48
ns
tESBRP
0.88
1.02
1.17
ns
Table 56. EP2A25 fMAX LE Timing Parameters
Symbol
-7 Speed Grade
-8 Speed Grade
-9 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tSU
0.25
0.29
0.33
ns
tH
0.25
0.29
0.33
ns
tCO
0.18
0.20
0.23
ns
tLUT
0.53
0.61
0.70
ns
86
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Table 57. EP2A25 fMAX ESB Timing Parameters
Symbol
-7 Speed Grade
-8 Speed Grade
-9 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tESBARC
1.28
1.47
1.69
ns
tESBSRC
2.49
2.86
3.29
ns
tESBAWC
2.20
2.53
2.91
ns
3.99
ns
3.02
tESBSWC
3.47
tESBWASU
0.07
0.07
0.09
tESBWAH
0.15
0.18
0.20
ns
ns
tESBWDSU
0.37
0.43
0.49
ns
tESBWDH
0.16
0.18
0.21
ns
tESBRASU
0.84
0.96
1.11
ns
tESBRAH
0.00
0.00
0.00
ns
tESBWESU
0.14
0.16
0.19
ns
tESBDATASU
− 0.02
− 0.03
− 0.03
ns
tESBWADDRSU
− 0.40
− 0.46
− 0.53
ns
tESBRADDRSU
− 0.38
− 0.44
− 0.51
ns
tESBDATACO1
1.30
1.50
1.72
ns
tESBDATACO2
1.84
2.12
2.44
ns
tESBDD
2.42
2.78
3.19
ns
tPD
1.69
1.94
2.23
ns
tPTERMSU
1.10
1.26
0.82
tPTERMCO
1.45
0.94
ns
1.08
ns
Table 58. EP2A25 fMAX Routing Delays
Symbol
-7 Speed Grade
-8 Speed Grade
-9 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tF1-4
0.19
0.21
0.25
ns
tF5-20
0.65
0.75
0.86
ns
tF20+
1.11
1.27
1.46
ns
Altera Corporation
87
APEX II Programmable Logic Device Family Data Sheet
Table 59. EP2A25 Minimum Pulse Width Timing Parameters
Symbol
-7 Speed Grade
-8 Speed Grade
-9 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tCH
1.00
1.50
2.12
ns
tCL
1.00
1.50
2.12
ns
tCLRP
0.13
0.15
0.17
ns
tPREP
0.13
0.15
0.17
ns
tESBCH
1.00
1.50
2.12
ns
tESBCL
1.00
1.50
2.12
ns
tESBWP
1.12
1.28
1.48
ns
tESBRP
0.88
1.02
1.17
ns
Table 60. EP2A40 fMAX LE Timing Parameters
Symbol
-7 Speed Grade
-8 Speed Grade
-9 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tSU
0.22
0.26
0.29
ns
tH
0.22
0.26
0.29
ns
tCO
0.16
0.18
0.21
ns
tLUT
0.48
0.55
0.63
ns
88
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Table 61. EP2A40 fMAX ESB Timing Parameters
Symbol
-7 Speed Grade
-8 Speed Grade
-9 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tESBARC
2.28
2.62
3.01
ns
tESBSRC
2.23
2.56
2.95
ns
tESBAWC
3.13
3.60
4.13
ns
3.65
ns
2.76
tESBSWC
3.18
tESBWASU
1.19
1.37
1.57
tESBWAH
0.00
0.00
0.00
ns
ns
tESBWDSU
1.44
1.66
1.91
ns
tESBWDH
0.00
0.00
0.00
ns
tESBRASU
1.88
2.17
2.49
ns
tESBRAH
0.00
0.00
0.00
ns
tESBWESU
1.60
1.85
2.12
ns
tESBDATASU
0.74
0.85
0.98
ns
tESBWADDRSU
0.82
0.94
1.08
ns
tESBRADDRSU
0.73
0.84
.97
ns
tESBDATACO1
1.09
1.25
1.44
ns
tESBDATACO2
1.73
1.99
2.29
ns
tESBDD
3.26
3.75
4.32
ns
tPD
1.55
1.78
2.05
ns
tPTERMSU
0.99
1.13
0.79
tPTERMCO
1.30
0.90
ns
1.04
ns
Table 62. EP2A40 fMAX Routing Delays
Symbol
-7 Speed Grade
-8 Speed Grade
-9 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tF1-4
0.17
0.19
0.22
ns
tF5-20
1.12
1.28
1.48
ns
tF20+
1.49
1.72
1.98
ns
Altera Corporation
89
APEX II Programmable Logic Device Family Data Sheet
Table 63. EP2A40 Minimum Pulse Width Timing Parameters
Symbol
-7 Speed Grade
-8 Speed Grade
-9 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tCH
0.89
1.33
1.88
ns
tCL
0.89
1.33
1.88
ns
tCLRP
0.12
0.14
0.16
ns
tPREP
0.12
0.14
0.16
ns
tESBCH
0.89
1.33
1.88
ns
tESBCL
0.89
1.33
1.88
ns
tESBWP
1.05
1.20
1.38
ns
tESBRP
0.78
0.90
1.03
ns
Table 64. EP2A70 fMAX LE Timing Parameters
Symbol
-7 Speed Grade
-8 Speed Grade
-9 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tSU
0.30
0.34
0.39
ns
tH
0.30
0.34
0.39
ns
tCO
0.22
0.25
0.29
ns
tLUT
0.66
0.76
0.87
ns
90
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Table 65. EP2A70 fMAX ESB Timing Parameters
Symbol
-7 Speed Grade
-8 Speed Grade
-9 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tESBARC
3.12
3.58
4.12
ns
tESBSRC
3.11
3.58
4.11
ns
tESBAWC
4.41
5.07
5.83
ns
3.82
tESBSWC
4.39
1.99
5.05
2.28
ns
tESBWASU
1.73
ns
tESBWAH
0.00
0.00
0.00
ns
tESBWDSU
1.87
2.15
2.47
ns
tESBWDH
0.00
0.00
0.00
ns
tESBRASU
2.76
3.17
3.65
ns
tESBRAH
0.00
0.00
0.00
ns
tESBWESU
1.98
2.27
2.61
ns
tESBDATASU
1.06
1.22
1.40
ns
tESBWADDRSU
1.17
1.34
1.54
ns
tESBRADDRSU
1.02
1.17
1.35
ns
tESBDATACO1
1.52
1.75
2.01
ns
tESBDATACO2
2.35
2.71
3.11
ns
tESBDD
4.43
5.10
5.87
ns
tPD
2.17
2.49
2.87
tPTERMSU
1.40
1.62
1.08
tPTERMCO
1.86
1.24
ns
ns
1.42
ns
Table 66. EP2A70 fMAX Routing Delays
Symbol
-7 Speed Grade
-8 Speed Grade
-9 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tF1-4
0.15
0.18
0.20
ns
tF5-20
1.21
1.39
1.60
ns
tF20+
1.87
2.15
2.55
ns
Altera Corporation
91
APEX II Programmable Logic Device Family Data Sheet
Table 67. EP2A70 Minimum Pulse Width Timing Parameters
Symbol
-7 Speed Grade
-8 Speed Grade
-9 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tCH
1.19
1.78
2.53
ns
tCL
1.19
1.78
2.53
ns
tCLRP
0.16
0.19
0.21
ns
tPREP
0.16
0.19
0.21
ns
tESBCH
1.19
1.78
2.53
ns
tESBCL
1.19
1.78
2.53
ns
tESBWP
1.35
1.56
1.79
ns
tESBRP
1.13
1.30
1.50
ns
Tables 68 through 77 show the IOE external timing parameter values for
APEX II devices.
Table 68. EP2A15 External Timing Parameters for Row I/O Pins
Symbol
-7 Speed Grade
Min
Max
-8 Speed Grade
Min
Max
-9 Speed Grade
Min
tINSU
2.06
2.25
2.46
tINH
0.00
0.00
0.00
tOUTCO
2.00
4.05
2.00
4.45
2.00
Unit
Max
ns
ns
4.90
ns
tXZ
4.98
5.59
6.26
ns
tZX
4.98
5.59
6.26
ns
tINSUPLL
1.15
1.28
1.42
tINHPLL
0.00
0.00
0.00
tOUTCOPLL
0.50
2.60
0.50
2.87
0.50
ns
ns
3.16
ns
tXZPLL
3.53
4.00
4.52
ns
tZXPLL
3.53
4.00
4.52
ns
92
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Table 69. EP2A15 External Timing Parameters for Column I/O Pins
Symbol
-7 Speed Grade
Min
Max
-8 Speed Grade
Min
Max
-9 Speed Grade
Min
tINSU
2.16
2.34
2.53
tINH
0.00
0.00
0.00
tOUTCO
2.00
4.36
2.00
4.75
2.00
Unit
Max
ns
ns
5.18
ns
tXZ
5.57
6.24
6.97
ns
tZX
5.57
6.24
6.97
ns
tINSUPLL
1.24
1.37
1.52
tINHPLL
0.00
0.00
0.00
tOUTCOPLL
0.50
2.90
0.50
3.16
0.50
ns
ns
3.45
ns
tXZPLL
4.12
4.65
5.23
ns
tZXPLL
4.12
4.65
5.23
ns
Table 70. EP2A25 External Timing Parameters for Row I/O Pins
Symbol
-7 Speed Grade
Min
tINSU
1.92
tINH
0.00
tOUTCO
2.00
Max
-8 Speed Grade
Min
Max
2.08
2.00
Min
ns
0.00
4.62
2.00
Unit
Max
2.26
0.00
4.29
-9 Speed Grade
ns
4.98
ns
tXZ
5.24
5.73
6.26
ns
tZX
5.24
5.73
6.26
ns
tINSUPLL
1.17
1.27
1.40
ns
tINHPLL
0.00
0.00
0.00
ns
tOUTCOPLL
0.50
3.07
ns
tXZPLL
3.55
3.93
4.35
ns
tZXPLL
3.55
3.93
4.35
ns
Altera Corporation
2.61
0.50
2.83
0.50
93
APEX II Programmable Logic Device Family Data Sheet
Table 71. EP2A25 External Timing Parameters for Column I/O Pins
Symbol
-7 Speed Grade
Min
Max
-8 Speed Grade
Min
Max
-9 Speed Grade
Min
tINSU
2.27
2.45
2.64
tINH
0.00
0.00
0.00
tOUTCO
2.00
4.57
2.00
4.89
2.00
Unit
Max
ns
ns
5.24
ns
tXZ
5.87
6.42
7.01
ns
tZX
5.87
6.42
7.01
ns
tINSUPLL
1.23
1.35
1.47
tINHPLL
0.00
0.00
0.00
tOUTCOPLL
0.50
2.89
0.50
3.10
0.50
ns
ns
3.33
ns
tXZPLL
4.18
4.62
5.09
ns
tZXPLL
4.18
4.62
5.09
ns
Table 72. EP2A40 External Timing Parameters for Row I/O Pins
Symbol
-7 Speed Grade
Min
tINSU
1.57
tINH
0.00
tOUTCO
2.00
Max
-8 Speed Grade
Min
Max
1.72
2.00
Min
ns
0.00
5.24
2.00
Unit
Max
1.88
0.00
4.90
-9 Speed Grade
ns
5.61
ns
tXZ
6.47
6.98
7.53
ns
tZX
6.47
6.98
7.53
ns
tINSUPLL
1.15
1.26
1.38
ns
tINHPLL
0.00
0.00
0.00
ns
tOUTCOPLL
0.50
3.06
ns
tXZPLL
4.17
4.56
4.97
ns
tZXPLL
4.17
4.56
4.97
ns
94
2.60
0.50
2.82
0.50
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Table 73. EP2A40 External Timing Parameters for Column I/O Pins
Symbol
-7 Speed Grade
Min
Max
-8 Speed Grade
Min
Max
-9 Speed Grade
Min
tINSU
2.00
2.16
2.33
tINH
0.00
0.00
0.00
tOUTCO
2.00
4.96
2.00
5.29
2.00
Unit
Max
ns
ns
5.64
ns
tXZ
7.04
7.59
8.19
ns
tZX
7.04
7.59
8.19
ns
tINSUPLL
1.20
1.31
1.43
tINHPLL
0.00
0.00
0.00
tOUTCOPLL
0.50
2.66
0.50
2.87
0.50
ns
ns
3.09
ns
tXZPLL
4.74
5.17
5.64
ns
tZXPLL
4.74
5.17
5.64
ns
Table 74. EP2A70 External Timing Parameters for Row I/O Pins
Symbol
-7 Speed Grade
Min
tINSU
2.48
tINH
0.00
tOUTCO
2.00
Max
-8 Speed Grade
Min
Max
2.68
2.00
Min
ns
0.00
5.12
2.00
Unit
Max
2.90
0.00
4.76
-9 Speed Grade
ns
5.51
ns
tXZ
5.68
6.19
6.76
ns
tZX
5.68
6.19
6.76
ns
tINSUPLL
1.19
1.30
1.43
ns
tINHPLL
0.00
0.00
0.00
ns
tOUTCOPLL
0.50
2.98
ns
tXZPLL
3.44
3.82
4.23
ns
tZXPLL
3.44
3.82
4.23
ns
Altera Corporation
2.52
0.50
2.74
0.50
95
APEX II Programmable Logic Device Family Data Sheet
Table 75. EP2A70 External Timing Parameters for Column I/O Pins
Symbol
-7 Speed Grade
Min
Max
-8 Speed Grade
Min
Max
-9 Speed Grade
Min
tINSU
2.79
2.99
3.22
tINH
0.00
0.00
0.00
tOUTCO
2.00
4.91
2.00
5.24
2.00
Unit
Max
ns
ns
5.60
ns
tXZ
6.16
6.71
7.32
ns
tZX
6.16
6.71
7.32
ns
tINSUPLL
1.19
1.30
1.43
tINHPLL
0.00
0.00
0.00
tOUTCOPLL
0.50
2.67
0.50
2.86
0.50
ns
ns
3.08
ns
tXZPLL
3.92
4.34
4.79
ns
tZXPLL
3.92
4.34
4.79
ns
96
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Table 76. APEX II Selectable I/O Standards Input Adder Delays
Symbol
-7 Speed Grade
Min
Max
-8 Speed Grade
Min
Max
-9 Speed Grade
Min
Unit
Max
LVCMOS
0.00
0.00
0.00
ns
LVTTL
0.00
0.00
0.00
ns
1.5 V
0.10
0.11
0.12
ns
1.8 V
0.00
0.00
0.00
ns
2.5 V
0.00
0.00
0.00
ns
3.3-V PCI
0.00
0.00
0.00
ns
3.3-V PCI-X
0.00
0.00
0.00
ns
GTL+
− 0.20
− 0.22
− 0.24
ns
SSTL-3 Class I
− 0.17
− 0.19
− 0.20
ns
SSTL-3 Class II
− 0.17
− 0.19
− 0.20
ns
SSTL-2 Class I
− 0.24
− 0.26
− 0.29
ns
SSTL-2 Class II
− 0.24
− 0.26
− 0.29
ns
HSTL Class I
− 0.03
− 0.03
− 0.03
ns
HSTL Class II
− 0.03
− 0.03
− 0.03
ns
LVDS
− 0.23
− 0.26
− 0.28
ns
LVPECL
− 0.23
− 0.26
− 0.28
ns
PCML
ns
− 0.23
− 0.26
− 0.28
CTT
0.00
0.00
0.00
ns
3.3-V AGP 1×
0.00
0.00
0.00
ns
3.3-V AGP 2×
0.00
0.00
0.00
ns
HyperTransport
− 0.23
− 0.26
− 0.28
ns
Differential
HSTL
− 0.23
− 0.26
− 0.28
ns
Altera Corporation
97
APEX II Programmable Logic Device Family Data Sheet
Table 77. APEX II Selectable I/O Standards Output Adder Delays
Symbol
-7 Speed Grade
Min
Max
-8 Speed Grade
Min
Max
-9 Speed Grade
Min
Unit
Max
LVCMOS
0.00
0.00
0.00
LVTTL
0.00
0.00
0.00
ns
1.5 V
3.32
3.82
4.20
ns
1.8 V
2.65
3.05
3.36
ns
2.5 V
1.20
1.38
1.52
ns
− 0.68
− 0.78
− 0.85
ns
3.3-V PCI
ns
3.3-V PCI-X
− 0.68
− 0.78
− 0.85
ns
GTL+
− 0.45
− 0.52
− 0.57
ns
SSTL-3 Class I
− 0.52
− 0.60
− 0.66
ns
SSTL-3 Class II
− 0.52
− 0.60
− 0.66
ns
SSTL-2 Class I
− 0.68
− 0.78
− 0.86
ns
SSTL-2 Class II
− 0.81
− 0.93
− 1.02
ns
HSTL Class I
− 0.08
− 0.09
− 0.10
ns
HSTL Class II
− 0.23
− 0.27
− 0.30
ns
LVDS
− 1.41
− 1.62
− 1.79
ns
LVPECL
− 1.38
− 1.58
− 1.74
ns
PCML
− 1.30
− 1.50
− 1.65
ns
CTT
0.00
0.00
0.00
ns
3.3-V AGP 1×
0.00
0.00
0.00
ns
ns
0.00
0.00
0.00
HyperTransport
3.3-V AGP 2×
− 1.22
− 1.41
− 1.55
ns
Differential
HSTL
− 1.41
− 1.62
− 1.79
ns
Power
Consumption
Detailed power consumption information for APEX II devices will be
released via a future interactive power estimator on the Altera web site.
Device PinOuts
See the Altera web site (http://www.altera.com) or the Altera Digital
Library for pin-out information.
98
Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Revision
History
The information contained in the APEX II Programmable Logic Device
Family Data Sheet version 3.0 supersedes information published in
previous versions. The following changes were made to the APEX II
Programmable Logic Device Family Data Sheet version 3.0:
■
■
■
■
■
■
■
■
Changed the value from 624 to 400 Mbps throughout the document.
Deleted the pin count (612) for the EP2A25 device in the 1,020-pin
FineLine BGA package (see Table 3).
Added Table 13.
Changed the maximum value of 3.6 to 2.4 in Table 20.
Updated Tables 60 through 67 and Tables 72 through 75.
Updated Figures 25, 28, and 30.
Added Note (1) to Figure 13.
Added Figure 43.
®
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
Applications Hotline:
(800) 800-EPLD
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