AMCC PPC405CR

Part Number PPC405CR
Revision 1.02 – January 11, 2005
PPC405CR
Data Sheet
PowerPC 405CR Embedded Processor
Features
•
•
•
PowerPC® 405 32-bit RISC processor core
operating up to 266MHz
- Memory Management Unit
- 16KB instruction and 8KB data caches
- Multiply-Accumulate (MAC) function,
including fast multiply unit
- Programmable Timers
Synchronous DRAM (SDRAM) interface operating up to 133MHz
- 32-bit interface for non-ECC applications
- 40-bit interface serves 32 bits of data plus 8
check bits for ECC applications
External Peripheral Bus
- Flash ROM/Boot ROM interface
- Direct support for 8-, 16-, or 32-bit SRAM and
external peripherals
- Up to eight devices
- External Mastering supported
•
•
•
•
•
•
•
DMA support for external peripherals, internal
UART and memory
- Scatter-gather chaining supported
- Four channels
Programmable Interrupt Controller supports
interrupts from a variety of sources
- Supports 7 external and 10 internal interrupts
- Edge triggered or level-sensitive
- Positive or negative active
- Non-critical or critical interrupt to processor
core
- Programmable critical interrupt priority
ordering
Two serial ports (16550 compatible UART)
One IIC interface
General Purpose I/O (GPIO) available
Supports JTAG for board level testing
Internal Processor Local Bus (PLB) runs at
SDRAM interface frequency
Description
The PowerPC 405CR (PPC405CR) is a 32-bit RISC
embedded controller. High performance, peripheral
integration, and low cost make the device ideal for
wired communications, network printers, and other
computing applications.
This device is an easy upgrade for systems based on
PowerPC 403xx embedded processors, while providing a base for custom chip designs.
The controller is powered by a PPC405 embedded
core. This core tightly couples a 266 MHz CPU, MMU,
instruction and data caches, and debug logic. Finetuning of the core reduces data transfer overhead,
minimizes pipeline stalls, and improves performance.
AMCC
The PPC405CR employs the IBM CoreConnect™ bus
architecture. This architecture, as implemented on the
PPC405CR, consists of a 64-bit, 133-MHz Processor
Local Bus (PLB) and a 32-bit, 66-MHz On-Chip
Peripheral Bus (OPB). High-performance peripherals
attach to the PLB and less performance-critical peripherals attach to the OPB.
Technology: CMOS SA-12E 0.25 µm (0.18 µm Leff)
Package: 27 mm, 316-ball enhanced plastic ball grid
array (E-PBGA)
Power (estimated): Typical 0.8 W, Maximum 2.0 W at
200MHz.
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PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Address Map Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intialization Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pull-Up and Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unused I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
21
21
22
22
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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AMCC
PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
List of Figures
Figure 1. PPC405CR Embedded Controller Functional Block Diagram .................................................................. 5
Figure 2. 27mm, 316-Ball E-PBGA Package ......................................................................................................... 10
Figure 3. Package Thermal Specifications ............................................................................................................ 28
Figure 4. 5V-Tolerant I/O Input Current ................................................................................................................. 30
Figure 5. Timing Waveform .................................................................................................................................... 32
Figure 6. Input Setup and Hold Waveform ............................................................................................................. 35
Figure 7. Output Delay and Float Timing Waveform .............................................................................................. 35
List of Tables
Table 1. System Memory Address Map 4GB System Memory ................................................................................ 6
Table 2. DCR Address Map 4KB Device Configuration Register ............................................................................. 6
Table 3. Signals Listed Alphabetically ................................................................................................................... 11
Table 4. Signals Listed by Ball Assignment ........................................................................................................... 18
Table 5. Pin Summary ........................................................................................................................................... 21
Table 6. Signal Functional Description .................................................................................................................. 23
Table 7. Absolute Maximum Ratings ..................................................................................................................... 28
Table 8. Recommended DC Operating Conditions ................................................................................................ 29
Table 9. Input Capacitance .................................................................................................................................... 30
Table 10. Clocking Specifications .......................................................................................................................... 32
Table 11. Peripheral Interface Clock Timings ........................................................................................................ 34
Table 12. I/O Specifications—All speeds ............................................................................................................... 36
Table 13. I/O Specifications—133 and 200MHz .................................................................................................... 37
Table 14. I/O Specifications—266MHz .................................................................................................................. 38
Table 15. Strapping Pin Assignments .................................................................................................................... 39
AMCC
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Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Ordering, PVR, and JTAG Information
Product Name
Order Part Number1, 2
Processor
Frequency
Package
Rev
Level
PVR Value
JTAG ID
PPC405CR
PPC405CR-3BC133C
133MHz
27mm, 316 ball E-PBGA
C
0x40110145
0x42051049
PPC405CR
PPC405CR-3BC133CZ
133MHz
27mm, 316 ball E-PBGA
C
0x40110145
0x42051049
PPC405CR
PPC405CR-3KC133C
133MHz
27mm, 316 ball E-PBGA
C
0x40110145
0x42051049
PPC405CR
PPC405CR-3KC133CZ
133MHz
27mm, 316 ball E-PBGA
C
0x40110145
0x42051049
PPC405CR
PPC405CR-3BC200C
200MHz
27mm, 316 ball E-PBGA
C
0x40110145
0x42051049
PPC405CR
PPC405CR-3BC200CZ
200MHz
27mm, 316 ball E-PBGA
C
0x40110145
0x42051049
PPC405CR
PPC405CR-3KC200C
200MHz
27mm, 316 ball E-PBGA
C
0x40110145
0x42051049
PPC405CR
PPC405CR-3KC200CZ
200MHz
27mm, 316 ball E-PBGA
C
0x40110145
0x42051049
PPC405CR
PPC405CR-3BC266C
266MHz
27mm, 316 ball E-PBGA
C
0x40110145
0x42051049
PPC405CR
PPC405CR-3BC266CZ
266MHz
27mm, 316 ball E-PBGA
C
0x40110145
0x42051049
PPC405CR
PPC405CR-3KC266C
266MHz
27mm, 316 ball E-PBGA
C
0x40110145
0x42051049
PPC405CR
PPC405CR-3KC266CZ
266MHz
27mm, 316 ball E-PBGA
C
0x40110145
0x42051049
Notes: 1. Z at the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray.
2. Package type B contains lead; package type K is lead-free.
This section provides the part numbering nomenclature for the PPC405CR. For availability, contact your local
AMCC sales office.
Each part number contains a revision code. This refers to the die mask revision number and is specified in the part
numbering scheme for identification purposes only.
The PVR (Processor Version Register) is software accessible and contains additional information about the revision level of the part. Refer to the PPC405CR Embedded Processor User’s Manual for details on the register
content.
Part Number Key
PPC405CR-3BC266Cx
Part Number
Grade 3 Reliability
Package (E-PBGA)
4
Shipping Package
Blank = Tray
Z = Tape and reel
Operational Case Temperature
Range (-40°C to +85°C)
Processor Speed
133MHz
200MHz
266MHz
Revision Level
AMCC
Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Figure 1. PPC405CR Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
Clock
Control
Reset
Power
Mgmt
DCRs
Timers
MMU
PPC405
Processor Core
8KB
D-Cache
JTAG
Trace
DCU
ICU
GPIO
DCR Bus
16KB
I-Cache
UART
UART
On-chip Peripheral Bus (OPB)
Arb
DMA
Controller
(4-Channel)
Arb
IIC
OPB
Bridge
Processor Local Bus (PLB)
Code
Decompression
(CodePack™)
SDRAM
Controller
13-bit addr
32-bit data
External
Bus
Controller
External
Bus Master
Controller
32-bit addr
32-bit data
The PPC405CR is designed using the IBM Microelectronics Blue Logic® methodology in which major functional
blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent
way to create complex ASICs using IBM CoreConnect™ Bus Architecture.
AMCC
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Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Address Map Support
The PPC405CR incorporates two simple and separate address maps. The first address map defines the possible
use of address regions that the processor can access. The second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC405CR processor through the use of mtdcr
and mfdcr instructions.
Table 1. System Memory Address Map (4GB System Memory)
Function
Subfunction
Start Address
End Address
Size
0x00000000
0xEF5FFFFF
3830MB
0xF0000000
0xFFFFFFFF
256MB
General Use
SDRAM and External Peripherals
Note: Any of the address ranges listed at
right may be use for any of the above
functions.
Boot-up
Peripheral Bus Boot 1
0xFFE00000
0xFFFFFFFF
2MB
UART0
0xEF600300
0xEF600307
8B
UART1
0xEF600400
0xEF600407
8B
IIC0
0xEF600500
0xEF60051F
32B
OPB Arbiter
0xEF600600
0xEF60063F
64B
GPIO Controller Registers
0xEF600700
0xEF60077F
128B
Internal Peripherals
Notes:
1. When peripheral bus boot is selected, Peripheral bank 0 is automatically configured at reset to the address range listed above.
2. After the boot process, software may reassign the boot memory region for other uses.
3. All address ranges not listed above are reserved.
Table 2. DCR Address Map
Function
Total DCR Address
Space1
Reserved
Start Address
End Address
Size
0x000
0x3FF
1KW (4KB)1
0x000
0x00F
16W
Memory Controller Registers
0x010
0x011
2W
External Bus Controller Registers
0x012
0x013
2W
Decompression Controller Registers
0x014
0x015
2W
Reserved
0x016
0x07F
106W
PLB Registers
0x080
0x08F
16W
Reserved
0x090
0x09F
16W
OPB Bridge Out Registers
0x0A0
0x0A7
8W
Reserved
0x0A8
0x0AF
8W
Clock, Control, and Reset
0x0B0
0x0B7
8W
Power Management
0x0B8
0x0BF
8W
Interrupt Controller
0x0C0
0x0CF
16W
Reserved
0x0D0
0x0FF
48W
DMA Controller Registers
0x100
0x13F
64W
Reserved
0x140
0x3FF
704W
Notes:
1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit
(word) register, or 1 kiloword (KW) (which equals 4 KB).
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AMCC
PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
SDRAM Memory Controller
The PPC405CR Memory Controller core provides a low latency access path to SDRAM memory. A variety of system memory configurations are supported. The memory controller supports up to four logical banks. Up to 256MB
per bank are supported, up to a maximum of 1 GB. Memory timings, address and bank sizes, and memory
addressing modes are programmable.
Features include:
•
•
•
•
•
•
•
•
•
•
11x8 to 13x11 addressing for SDRAM (2- and 4-bank)
32-bit memory interface support
Programmable address compare for each bank of memory
Industry standard 168-pin DIMMS are supported (some configurations)
4MB to 256MB per bank
Programmable address mapping and timing
Auto refresh
Page mode accesses with up to 4 open pages
Power Management (self-refresh)
Error Checking and Correction (ECC) support
- Standard SEC/DED coverage
- Aligned nibble error detect
- Address error logging
External Peripheral Bus Controller (EBC)
•
•
•
•
•
•
•
•
•
Supports eight banks of ROM, EPROM, SRAM, Flash memory, or slave peripheral I/O
Up to 66MHz operation
Burst and non-burst devices
8-, 16-, 32-bit byte-addressable data bus width support
Programmable 2K clock time-out counter with disable for Ready
Programmable access timing per device
- 0–255 wait states for non-burst devices
- 0–31 burst wait states for first access and up to 7 wait states for subsequent accesses
- Programmable CSon, CSoff relative to address
- Programmable OEon, WEon, WEoff (0 to 3 clock cycles) relative to CS
Programmable address mapping
Peripheral device pacing with external “Ready”
External master interface
- Write posting from external master
- Read prefetching on PLB for external master reads
- Bursting capable from external master
- Allows external master access to all non-EBC PLB slaves
- External master can control EBC slaves for own access and control
DMA Controller
•
AMCC
Supports the following transfers:
- Memory-to-memory transfers
- Buffered peripheral to memory transfers
7
PPC405CR – PowerPC 405CR Embedded Processor
•
•
•
•
•
•
•
•
•
Revision 1.02 – January 11, 2005
Data Sheet
- Buffered memory to peripheral transfers
Four channels
Scatter/Gather capability for programming multiple DMA operations
8-, 16-, 32-bit peripheral support (OPB and external)
32-bit addressing
Address increment or decrement
Internal 32-byte data buffering capability
Supports internal and external peripherals
Support for memory mapped peripherals
Support for peripherals running on slower frequency buses
UART
•
•
•
•
•
•
•
One 8-pin UART and one 4-pin UART interface provided
Selectable internal or external serial clock to allow wide range of baud rates
Register compatibility with NS16550 register set
Complete status reporting capability
Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode
Fully programmable serial-interface characteristics
Supports DMA using internal DMA engine
IIC Bus Interface
•
•
•
•
•
•
•
•
Compliant with Phillips® Semiconductors I2C Specification, dated 1995
Operation at 100kHz or 400kHz
8-bit data
10- or 7-bit address
Slave transmitter and receiver
Master transmitter and receiver
Multiple bus masters
Supports fixed VDD IIC interface
•
•
•
•
•
Two independent 4 x 1 byte data buffers
Twelve memory-mapped, fully programmable configuration registers
One programmable interrupt request signal
Provides full management of all IIC bus protocol
Programmable error recovery
General Purpose IO (GPIO) Controller
•
•
•
8
Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus
master accesses.
All GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose. The 23 GPIOs are multiplexed with:
- 7 of 8 chip selects.
- All seven external interrupts.
- All nine instruction trace pins.
Each GPIO output is separately programmable to emulate an open-drain driver (two states, drive to zero or
open circuit).
AMCC
PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the
various sources of interrupts and the local PowerPC processor.
Features include:
•
•
•
•
•
•
Supports 7 external and 10 internal interrupts
Edge triggered or level-sensitive
Positive or negative active
Non-critical or critical interrupt to PPC405 processor core
Programmable critical interrupt priority ordering
Programmable critical interrupt vector for faster vector processing
JTAG
•
•
•
AMCC
IEEE 1149.1 test access port
IBM RISCWatch debugger support
JTAG Boundary Scan Description Language (BSDL)
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Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Figure 2. 27mm, 316-Ball E-PBGA Package
Reserved Area for Ejector Pin Mark x 4 TYP
Corner Shape is Chamferred or Rounded
Top View
Gold Gate Release
Corresponds to
A1 Ball Location
15.0 TYP
27.0 REF
7.5 TYP
27.0
Notes: 1. All dimensions are in mm.
C
2. Package available in leaded and lead-free configurations.
0.20 C
0.20
27.0
Bottom View
0.25 C
24.13
27.0
B
A
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
0.35 C
1.27 TYP
Mold
Compound
Thermal Balls
PCB
Substrate
1
2
3
4
5
6
7
8
9
11 13 15 17 19
10 12 14 16 18 20
0.6 ± 0.1
2.65 MAX
0.75 ± 0.15 SOLDERBALL x 316
∅ 0.30 M C A B
∅ 0.15 M C
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AMCC
PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
Pin Lists
In this section there are two tables that correlate the external signals to the physical package pin (ball) on which
they appear.
The following table lists all the external signals in alphabetical order and shows the ball number on which the signal
appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate
signal in brackets. The page number listed gives the page in “Signal Functional Description” on page 23 where the
signals in the indicated interface group begin.
Table 3. Signals Listed Alphabetically (Sheet 1 of 7)
Signal Name
Ball
Interface Group
Page
AVDD
E20
Power
27
BA0
BA1
J17
H18
SDRAM
23
BankSel0
BankSel1
BankSel2
BankSel3
L19
N17
P17
U19
SDRAM
23
BusReq
P2
External Master Peripheral
25
CAS
K17
SDRAM
23
ClkEn0
ClkEn1
J19
G20
SDRAM
23
DMAAck0
DMAAck1
DMAAck2
DMAAck3
C16
B17
B16
A14
External Slave Peripheral
23
DMAReq0
DMAReq1
DMAReq2
DMAReq3
A19
C15
B15
A8
External Slave Peripheral
23
DQM0
DQM1
DQM2
DQM3
U18
W14
Y10
U8
SDRAM
23
DQMCB
V19
SDRAM
23
DrvrInh1
DrvrInh2
F17
C19
System
26
ECC0
ECC1
ECC2
ECC3
ECC4
ECC5
ECC6
ECC7
V17
Y18
U14
V13
Y13
V12
W11
V11
SDRAM
23
EOT0/TC0
EOT1/TC1
EOT2/TC2
EOT3/TC3
G4
F2
W1
Y2
External Slave Peripheral
23
ExtAck
ExtReq
ExtReset
U5
Y3
P4
External Master Peripheral
25
AMCC
11
PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 2 of 7)
Signal Name
Ball
GND
A1
A6
A10
A15
A20
B2
B19
C3
C18
D4
D17
E5
E10
E11
E16
F1
F20
J9
J10
J11
J12
K5
K9
K10
K11
K12
K16
K20
L1
L5
L9
L10
L11
L12
L16
M9
M10
M11
M12
R1
R20
GND (cont)
T5
T10
T11
T16
U4
U17
V3
V18
W2
W19
Y1
Y6
Y11
Y15
Y20
12
Interface Group
Page
Power
Note: J9–J12, K9–K12, L9–L12, and M9–M12 are also thermal balls.
27
Power
27
AMCC
PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 3 of 7)
Signal Name
Ball
Interface Group
Page
GPIO1[TS1E]
GPIO2[TS2E]
GPIO3[TS1O]
GPIO4[TS2O]
GPIO5[TS3]
GPIO6[TS4]
GPIO7[TS5]
GPIO8[TS6]
GPIO9[TrcClk]
B18
D16
C17
P18
T17
W18
Y19
W13
V6
System
26
Halt
E19
System
26
HoldAck
HoldPri
HoldReq
T4
T3
V2
External Master Peripheral
25
IICSCL
U15
Internal Peripheral
25
IICSDA
W17
Internal Peripheral
25
IRQ0[GPIO17]
IRQ1[GPIO18]
IRQ2[GPIO19]
IRQ3[GPIO20]
IRQ4[GPIO21]
IRQ5[GPIO22]
IRQ6[GPIO23]
D18
C20
E18
D20
G17
F18
W20
Interrupts
26
MemAddr0
MemAddr1
MemAddr2
MemAddr3
MemAddr4
MemAddr5
MemAddr6
MemAddr7
MemAddr8
MemAddr9
MemAddr10
MemAddr11
MemAddr12
Y7
W7
V8
U7
Y4
U6
W4
V5
W3
V4
U3
V1
T2
SDRAM
Note: During a CAS cycle MemAddr0 is the least significant bit (lsb) on this
bus.
23
MemClkOut0
MemClkOut1
H20
G18
SDRAM
23
AMCC
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PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 4 of 7)
Signal Name
Ball
MemData0
MemData1
MemData2
MemData3
MemData4
MemData5
MemData6
MemData7
MemData8
MemData9
MemData10
MemData11
MemData12
MemData13
MemData14
MemData15
MemData16
MemData17
MemData18
MemData19
MemData20
MemData21
MemData22
MemData23
MemData24
MemData25
MemData26
MemData27
MemData28
MemData29
MemData30
MemData31
J18
K19
L20
M20
M19
L18
L17
N20
N19
M18
M17
P20
P19
N18
U20
T18
W16
Y17
Y16
V14
Y14
U12
W12
Y12
Y9
W9
V10
U10
Y8
W8
V9
U9
OVDD
F5
G5
P5
R5
T6
T7
T14
T15
F16
G16
P16
R16
E6
E7
E14
E15
14
Interface Group
Page
SDRAM
Note: MemData0 is the most significant bit (msb) on this bus.
23
Power
27
AMCC
PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 5 of 7)
Signal Name
PerAddr0
PerAddr1
PerAddr2
PerAddr3
PerAddr4
PerAddr5
PerAddr6
PerAddr7
PerAddr8
PerAddr9
PerAddr10
PerAddr11
PerAddr12
PerAddr13
PerAddr14
PerAddr15
PerAddr16
PerAddr17
PerAddr18
PerAddr19
PerAddr20
PerAddr21
PerAddr22
PerAddr23
PerAddr24
PerAddr25
PerAddr26
PerAddr27
PerAddr28
PerAddr29
PerAddr30
PerAddr31
Ball
A3
A4
B6
D7
C6
B7
D8
C7
B8
A7
D9
C8
B9
D10
C9
A9
B11
A11
B12
D11
A13
B13
C12
D12
B14
C13
D13
A16
C14
D14
A17
D15
Interface Group
External Slave Peripheral
Note: PerAddr0 is the most significant bit (msb) on this bus.
Page
23
PerBLast
E2
External Slave Peripheral
23
PerClk
D3
External Master Peripheral
25
PerCS0
PerCS1[GPIO10]
PerCS2[GPIO11]
PerCS3[GPIO12]
PerCS4[GPIO13]
PerCS5[GPIO14]
PerCS6[GPIO15]
PerCS7[GPIO16]
D6
B5
C5
A5
B10
C10
A12
C11
External Slave Peripheral
23
AMCC
15
PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 6 of 7)
Signal Name
PerData0
PerData1
PerData2
PerData3
PerData4
PerData5
PerData6
PerData7
PerData8
PerData9
PerData10
PerData11
PerData12
PerData13
PerData14
PerData15
PerData16
PerData17
PerData18
PerData19
PerData20
PerData21
PerData22
PerData23
PerData24
PerData25
PerData26
PerData27
PerData28
PerData29
PerData30
PerData31
Ball
U2
R4
U1
R2
R3
T1
N4
P3
N2
P1
M4
N3
M2
N1
L4
M3
L2
M1
K2
L3
K1
J1
J2
K3
K4
H1
H2
J3
J4
G1
G2
H3
Interface Group
Page
External Slave Peripheral
Note: PerData0 is the most significant bit (msb) on this bus.
23
PerErr
B1
External Master Peripheral
25
PerOE
E4
External Slave Peripheral
23
PerPar0
PerPar1
PerPar2
PerPar3
C2
G3
E1
H4
External Slave Peripheral
23
PerReady
E3
External Slave Peripheral
23
PerR/W
C1
External Slave Peripheral
23
PerWBE0
PerWBE1
PerWBE2
PerWBE3
D2
F4
F3
D1
External Slave Peripheral
23
PerWE
C4
External Slave Peripheral
23
RAS
K18
SDRAM
23
RcvrInh
E17
System
26
Reserved
J20
G19
R17
T20
V16
Other pins
Notes:
1. Connect G19 to ground.
2. Other reserved pins are not connected internally within the chip and
should not have signals, voltage, or ground applied to them.
27
16
AMCC
PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 7 of 7)
Signal Name
Ball
Interface Group
Page
SysClk
SysErr
SysReset
H17
A18
D19
System
26
TCK
TDI
TDO
B4
A2
D5
JTAG
26
TestEn
F19
System
26
TmrClk
B20
System
26
TMS
B3
JTAG
26
TRST
H19
JTAG
26
UART0_CTS
UART0_DCD
UART0_DSR
UART0_DTR
UART0_RI
UART0_RTS
UART0_Rx
UART0_Tx
W10
R18
U16
U13
V15
V20
T19
W15
Internal Peripheral
25
UART1_DSR[UART1_CTS]
UART1_RTS[UART1_DTR]
UART1_Rx
UART1_Tx
V7
W6
W5
Y5
Internal Peripheral
25
UARTSerClk
R19
Internal Peripheral
25
VDD
E8
E9
E12
E13
H5
H16
J5
J16
M5
M16
N5
N16
T8
T9
T12
T13
Power
27
WE
U11
SDRAM
23
AMCC
17
Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 1 of 3)
Ball
18
Signal Name
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
A1
GND
B10
PerCS4[GPIO13]
C19
DrvrInh2
E8
VDD
A2
TDI
B11
PerAddr16
C20
IRQ1[GPIO18]
E9
VDD
A3
PerAddr0
B12
PerAddr18
D1
PerWBE3
E10
GND
A4
PerAddr1
B13
PerAddr21
D2
PerWBE0
E11
GND
A5
PerCS3[GPIO12]
B14
PerAddr24
D3
PerClk
E12
VDD
A6
Gnd
B15
DMAReq2
D4
GND
E13
VDD
A7
PerAddr9
B16
DMAAck2
D5
TDO
E14
OVDD
A8
DMAReq3
B17
DMAAck1
D6
PerCS0
E15
OVDD
A9
PerAddr15
B18
GPIO1[TS1E]
D7
PerAddr3
E16
GND
A10
GND
B19
GND
D8
PerAddr6
E17
Rcrvinh
A11
PerAddr17
B20
TmrClk
D9
PerAddr10
E18
IRQ2[GPIO19]
A12
PerCS6[GPIO15]
C1
PerR/W
D10
PerAddr13
E19
Halt
A13
PerAddr20
C2
PerPar0
D11
PerAddr19
E20
AVDD
A14
DMAAck3
C3
GND
D12
PerAddr23
F1
GND
A15
GND
C4
PerWE
D13
PerAdd26
F2
EOT1/TC1
A16
PerAddr27
C5
PerCS2[GPIO11]
D14
PerAddr29
F3
PerWBE2
A17
PerAddr30
C6
PerAddr4
D15
PerAddr31
F4
PerWBE1
A18
SysErr
C7
PerAddr7
D16
GPIO2[TS2E]
F5
OVDD
A19
DMAReq0
C8
PerAddr11
D17
GND
F16
OVDD
A20
GND
C9
PerAddr14
D18
IRQ0[GPIO17]
F17
DrvrInh1
B1
PerErr
C10
PerCS5[GPIO14]
D19
SysReset
F18
IRQ5[GPIO22]
B2
GND
C11
PerCS7[GPIO16]
D20
IRQ3[GPIO20]
F19
TestEn
B3
TMS
C12
PerAddr22
E1
PerPar2
F20
GND
B4
TCK
C13
PerAddr25
E2
PerBLast
G1
PerData29
B5
PerCS1[GPIO10]
C14
PerAddr28
E3
PerReady
G2
PerData30
B6
PerAddr2
C15
DMAReq1
E4
PerOE
G3
PerPar1
B7
PerAddr5
C16
DMAAck0
E5
GND
G4
EOT0/TC0
B8
PerAddr8
C17
GPIO3[TS1O]
E6
OVDD
G5
OVDD
B9
PerAddr12
C18
GND
E7
OVDD
G16
OVDD
AMCC
Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 2 of 3)
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
Ball
Signal Name
G17
IRQ4[GPIO21]
K2
PerData18
M3
PerData15
P18
GPIO4[TS2O]
G18
MemClkOut1
K3
PerData23
M4
PerData10
P19
MemData12
G19
Reserved
K4
PerData24
M5
VDD
P20
MemData11
G20
ClkEn1
K5
GND
M9
Thermal Ball
R1
GND
H1
PerData25
K9
Thermal Ball
M10
Thermal Ball
R2
PerData3
H2
PerData26
K10
Thermal Ball
M11
Thermal Ball
R3
PerData4
H3
PerData31
K11
Thermal Ball
M12
Thermal Ball
R4
PerData1
H4
PerPar3
K12
Thermal Ball
M16
VDD
R5
OVDD
H5
VDD
K16
GND
M17
MemData10
R16
OVDD
H16
VDD
K17
CAS
M18
MemData9
R17
Reserved
H17
SysClk
K18
RAS
M19
MemData4
R18
UART0_DCD
H18
BA1
K19
MemData1
M20
MemData3
R19
UARTSerClk
H19
TRST
K20
GND
N1
PerData13
R20
GND
H20
MemClkOut0
L1
GND
N2
PerData8
T1
PerData5
J1
PerData21
L2
PerData16
N3
PerData11
T2
MemAddr12
J2
PerData22
L3
PerData19
N4
PerData6
T3
HoldPri
J3
PerData27
L4
PerData14
N5
VDD
T4
HoldAck
J4
PerData28
L5
GND
N16
VDD
T5
GND
J5
VDD
L9
Thermal Ball
N17
BankSel1
T6
OVDD
J9
Thermal Ball
L10
Thermal Ball
N18
MemData13
T7
OVDD
J10
Thermal Ball
L11
Thermal Ball
N19
MemData8
T8
VDD
J11
Thermal Ball
L12
Thermal Ball
N20
MemData7
T9
VDD
J12
Thermal Ball
L16
GND
P1
PerData9
T10
GND
J16
VDD
L17
MemData6
P2
BusReq
T11
GND
J17
BA0
L18
MemData5
P3
PerData7
T12
VDD
J18
MemData0
L19
BankSel0
P4
ExtReset
T13
VDD
J19
ClkEn0
L20
MemData2
P5
OVDD
T14
OVDD
J20
Reserved
M1
PerData17
P16
OVDD
T15
OVDD
K1
PerData20
M2
PerData12
P17
BankSel2
T16
GND
AMCC
19
Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 3 of 3)
Ball
20
Signal Name
Ball
Signal Name
Ball
Signal Name
Ball
W20
Signal Name
T17
GPIO5[TS3]
U18
DQM0
V19
DQMCB
IRQ6[GPIO23]
T18
MemData15
U19
BankSel3
V20
UART0_RTS
Y1
GND
T19
UART0_RX
U20
MemData14
W1
EOT2/TC2
Y2
EOT3/TC3
T20
Reserved
V1
MemAddr11
W2
GND
Y3
ExtReq
U1
PerData2
V2
HoldReq
W3
MemAddr8
Y4
MemAddr4
U2
PerData0
V3
GND
W4
MemAddr6
Y5
UART1_TX
U3
MemAddr10
V4
MemAddr9
W5
UART1_RX
Y6
GND
U4
GND
V5
MemAddr7
W6
UART1_RTS
[UART1_DTR]
Y7
MemAddr0
U5
ExtAck
V6
GPIO9[TrcClk]
W7
MemAddr1
Y8
MemData28
U6
MemAddr5
V7
UART1_DSR
[UART1_CTS]
W8
MemData29
Y9
MemData24
U7
MemAddr3
V8
MemAddr2
W9
MemData25
Y10
DQM2
U8
DQM3
V9
MemData30
W10
UART0_CTS
Y11
GND
U9
MemData31
V10
MemData26
W11
ECC6
Y12
MemData23
U10
MemData27
V11
ECC7
W12
MemData22
Y13
ECC4
U11
WE
V12
ECC5
W13
GPIO8[TS6]
Y14
MemData20
U12
MemData21
V13
ECC3
W14
DQM1
Y15
GND
U13
UART0_DTR
V14
MemData19
W15
UART0_TX
Y16
MemData18
U14
ECC2
V15
UART0_RI
W16
MemData16
Y17
MemData17
U15
IICSCL
V16
Reserved
W17
IICSDA
Y18
ECC1
U16
UART0_DSR
V17
ECC0
W18
GPIO6[TS4]
Y19
GPIO7[TS5]
U17
GND
V18
GND
W19
GND
Y20
GND
AMCC
PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
Signal Descriptions
The PPC405CR embedded controller is packaged in a 316-ball enhanced plastic ball grid array (E-PBGA). The following table provides a summary of the number of package pins associated with each functional interface group.
Table 5. Pin Summary
Group
No. of Pins
SDRAM
71
External Peripheral
97
External Master
9
Internal Peripheral
15
Interrupts
7
JTAG
5
System
18
Total Signal Pins
222
AVDD
1
OVDD
16
VDD
16
Gnd
40
Thermal (and Gnd)
16
Reserved
5
Total Pins
316
Multiplexed Pins
In the table “Signal Functional Description” on page 23, each I/O signal is listed along with a short description of the
signal function. Some signals are multiplexed onto the same package pin (ball) so that the pin can be used for different functions. Multiplexed signals are shown as a default signal with a secondary signal in square brackets (for
example, GPIO1[TS1E]). Active-low signals (for example, RAS) are marked with an overline.
It is expected that in any single application a particular pin will always be programmed to serve the same function.
The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible.
In addition to multiplexing, many pins are also multi-purpose. For example, the EBC peripheral controller address
pins are used as outputs by the PPC405CR to broadcast an address to external slave devices when the
PPC405CR has control of the external bus. When during the course of normal chip operation an external master
gains ownership of the external bus, these same pins are used as inputs which are driven by the external master
and received by the EBC in the PPC405CR.
Intialization Strapping
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see “Strapping” on page 39). Note that these
are not multiplexed pins since the function of the pins is not programmable.
Pull-Up and Pull-Down Resistors
Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an
appropriate state. The recommended pull-up value of 3kΩ to +3.3V (10kΩ to +5V can be used on 5V tolerant I/Os)
and pull-down value of 1kΩ to GND, applies only to individually terminated signals. To prevent possible damage to
the device, I/Os capable of becoming outputs must never be tied together and terminated through a common
resistor.
AMCC
21
PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
If your system-level test methodology permits, input-only signals can be connected together and terminated
through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure that
the grouped I/Os reach a valid logic zero or logic one state when accounting for the total input current into the
PPC405CR.
Unused I/Os
Strapping of some pins may be necessary when they are unused. Although the PPC405CR requires only the pullup and pull-down terminations as specified in the “Signal Functional Description” on page 23, good design practice
is to terminate all unused inputs or to configure I/Os such that they always drive. If unused, the peripheral and
SDRAM buses should be configured and terminated as follows:
•
•
Peripheral interface—PerAddr0:31, PerData0:31, and all of the control signals are driven by default. Terminate PerReady high and PerError low.
SDRAM—Program SDRAM0_CFG[EMDULR]=1 and SDRAM0_CFG[DCE]=1. This causes the PPC405CR
to actively drive all of the SDRAM address, data, and control signals.
External Bus Control Signals
All peripheral bus control signals (PerCS0:7, PerR/W, PerWBE0:3, PerOE, PerWE, PerBLast, HoldAck, ExtAck)
are set to the high-impedance state when ExtReset=0. In addition, as detailed in the PowerPC 405CR Embedded
Processor User’s Manual, the peripheral bus controller can be programmed via EBC0_CFG to float some of these
control signals between transactions and/or when an external master owns the peripheral bus. As a result, a pullup resistor should be added to those control signals where an undriven state may affect any devices receiving that
particular signal.
The following table lists all of the I/O signals provided by the PPC405CR. Please refer to “Signals Listed Alphabetically” on page 11 for the pin number to which each signal is assigned.
22
AMCC
PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
Table 6. Signal Functional Description (Sheet 1 of 5)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull-up or pull-down required.
7. Pull-up may be required. See “External Bus Control Signals” on page 22.
Signal Name
Description
I/O
Type
MemData0:31
Memory Data bus.
Notes:
1. MemData0 is the most significant bit (msb).
2. MemData31 is the least significant bit (lsb).
I/O
3.3V LVTTL
MemAddr12:0
Memory Address bus.
Notes:
1. MemAddr12 is the most significant bit (msb).
2. MemAddr0 is the least significant bit (lsb).
O
3.3V LVTTL
Bank Address supporting up to four internal banks.
O
3.3V LVTTL
RAS
Row Address Strobe.
O
3.3V LVTTL
CAS
Column Address Strobe.
O
3.3V LVTTL
DQM0:3
DQM for byte lanes 0 (MemData0:7),
1 (MemData8:15),
2 (MemData16:23), and
3 (MemData24:31).
O
3.3V LVTTL
DQMCB
DQM for ECC check bits.
O
3.3V LVTTL
ECC0:7
ECC check bits 0:7.
I/O
3.3V LVTTL
Notes
SDRAM Interface
BA0:1
BankSel0:3
WE
ClkEn0:1
MemClkOut0:1
Select up to four external SDRAM banks.
O
3.3V LVTTL
Write Enable.
O
3.3V LVTTL
SDRAM Clock Enable.
O
3.3V LVTTL
Two copies of an SDRAM clock allows, in some cases, glueless
SDRAM attach without requiring this signal to be repowered by a PLL
or zero-delay buffer.
O
3.3V LVTTL
External Slave Peripheral Interface
PerData0:31
Peripheral data bus used by PPC405CR when not in external master
mode, otherwise used by external master.
Note: PerData0 is the most significant bit (msb) on this bus.
I/O
5V tolerant
3.3V LVTTL
1
PerAddr0:31
Peripheral address bus used by PPC405CR when not in external
master mode, otherwise used by external master.
Note: PerAddr0 is the most significant bit (msb) on this bus.
I/O
5V tolerant
3.3V LVTTL
1
Peripheral byte parity signals.
I/O
5V tolerant
3.3V LVTTL
1
As outputs, these pins can act as byte-enables which are valid for an
entire cycle or as write-byte-enables which are valid for each byte on
each data transfer, allowing partial word transactions. As outputs,
pins are used by either peripheral controller or the DMA controller
depending upon the type of transfer involved. Used as inputs when
external bus master owns the external interface.
I/O
5V tolerant
3.3V LVTTL
1, 7
Peripheral write enable. Active when any of the four PerWBE0:3
signals are active.
O
5V tolerant
3.3V LVTTL
PerPar0:3
PerWBE0:3
PerWE
AMCC
23
PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
Table 6. Signal Functional Description (Sheet 2 of 5)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull-up or pull-down required.
7. Pull-up may be required. See “External Bus Control Signals” on page 22.
Signal Name
PerCS0
PerCS1:7[GPIO10:16]
Peripheral chip select bank 0.
Seven additional peripheral chip selects
or
General Purpose I/O. To access this function, software must toggle a
DCR register bit.
I/O
Type
Notes
O
5V tolerant
3.3V LVTTL
7
O[I/O]
5V tolerant
3.3V LVTTL
1, 7
PerOE
Used by either peripheral controller or DMA controller depending
upon the type of transfer involved. When the PPC405CR is the bus
master, it enables the selected device to drive the bus.
O
5V tolerant
3.3V LVTTL
7
PerR/W
Used by the PPC405CR when not in external master mode, as output
by either the peripheral controller or DMA controller depending upon
the type of transfer involved. High indicates a read from memory, low
indicates a write to memory.
Otherwise it used by the external master as an input to indicate the
direction of transfer.
I/O
5V tolerant
3.3V LVTTL
1
PerReady
Used by a peripheral slave to indicate it is ready to transfer data.
I
5V tolerant
3.3V LVTTL
1
PerBLast
Used by the PPC405CR when not in external master mode,
otherwise used by external master. Indicates the last transfer of a
memory access.
I/O
5V tolerant
3.3V LVTTL
1, 7
DMAReq0:3
DMAReq0:3 are used by slave peripherals to indicate they are
prepared to transfer data.
I
5V tolerant
3.3V LVTTL
1
DMAAck0:3
DMAAck0:3 are used by the PPC405CR to indicate that data
transfers have occurred.
O
5V tolerant
3.3V LVTTL
6
End Of Transfer/Terminal Count.
I/O
5V tolerant
3.3V LVTTL
1
EOT0:3/TC0:3
24
Description
AMCC
PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
Table 6. Signal Functional Description (Sheet 3 of 5)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull-up or pull-down required.
7. Pull-up may be required. See “External Bus Control Signals” on page 22.
Signal Name
Description
I/O
Type
Notes
External Master Peripheral Interface
PerClk
Peripheral clock to be used by an external master and by
synchronous peripheral slaves.
O
5V tolerant
3.3V LVTTL
ExtReset
Peripheral reset to be used by an external master and by
synchronous peripheral slaves.
O
5V tolerant
3.3V LVTTL
HoldReq
Hold Request, used by an external master to request ownership of
the peripheral bus.
I
5V tolerant
3.3V LVTTL
1, 5
HoldAck
Hold Acknowledge, used by the PPC405CR to transfer ownership of
peripheral bus to an external master.
O
5V tolerant
3.3V LVTTL
6
ExtReq
ExtReq is used by an external master to indicate it is prepared to
transfer data.
I
5V tolerant
3.3V LVTTL
1
ExtAck
ExtAck is used by the PPC405CR to indicate a data transfer cycle.
O
5V tolerant
3.3V LVTTL
6
HoldPri
Used by an external master to indicate the priority of a given external
master tenure.
I
5V tolerant
3.3V LVTTL
1
BusReq
Used when the PPC405CR needs to regain control of the peripheral
interface from an external master.
O
5V tolerant
3.3V LVTTL
Used as an input to indicate that an external slave peripheral error
has occurred.
I
5V tolerant
3.3V LVTTL
1, 5
Serial clock. Used to provide an alternate clock to the internally
generated serial clock. Used in cases where the allowable internally
generated baud rates are not satisfactory. This input can be
individually connected to either UART.
I
5V tolerant
3.3V LVTTL
1
UART0_Rx
UART0 Receive (serial data in).
I
5V tolerant
3.3V LVTTL
1
UART0_Tx
UART0 Transmit (serial data out).
O
5V tolerant
3.3V LVTTL
6
UART0_DCD
UART0 Data Carrier Detect.
I
5V tolerant
3.3V LVTTL
1
UART0_DSR
UART0 Data Set Ready.
I
5V tolerant
3.3V LVTTL
1
UART0_CTS
UART0 Clear To Send.
I
5V tolerant
3.3V LVTTL
1
UART0_DTR
UART0 Data Terminal Ready.
O
5V tolerant
3.3V LVTTL
6
UART0_RTS
UART0 Request To Send.
O
5V tolerant
3.3V LVTTL
6
UART0_RI
UART0 Ring Indicator.
I
5V tolerant
3.3V LVTTL
1
UART1_Rx
UART1 Receive (serial data in).
I
5V tolerant
3.3V LVTTL
1
PerErr
Internal Peripheral Interface
UARTSerClk
AMCC
25
PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
Table 6. Signal Functional Description (Sheet 4 of 5)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull-up or pull-down required.
7. Pull-up may be required. See “External Bus Control Signals” on page 22.
I/O
Type
Notes
UART1 Transmit (serial data out).
O
5V tolerant
3.3V LVTTL
6
UART1_DSR/
[UART1_CTS]
UART1 Data Set Ready
or
UART1 Clear To Send. To access this function, software must toggle
a DCR register bit.
I
5V tolerant
3.3V LVTTL
1
UART1_RTS/
[UART1_DTR]
UART1 Request To Send
or
UART1 Data Terminal Ready. To access this function, software must
toggle a DCR register bit.
O
5V tolerant
3.3V LVTTL
6
IICSCL
IIC serial clock.
I/O
5V tolerant
3.3V LVTTL
1, 2
IICSDA
IIC serial data.
I/O
5V tolerant
3.3V LVTTL
1, 2
I[I/O]
5V tolerant
3.3V LVTTL
1
Signal Name
UART1_Tx
Description
Interrupts Interface
IRQ0:6[GPIO17:23]
Interrupt requests
or
General Purpose I/O. To access this function, software must toggle a
DCR register bit.
JTAG Interface
TDI
Test data in.
I
5V tolerant
3.3V LVTTL
1, 4
TMS
JTAG test mode select.
I
5V tolerant
3.3V LVTTL
1, 4
TDO
Test data out.
O
5V tolerant
3.3V LVTTL
TCK
JTAG test clock. The frequency of this input can range from DC to
25MHz.
I
5V tolerant
3.3V LVTTL
1, 4
TRST
JTAG reset. TRST must be low at power-on to initialize the JTAG
controller and for normal operation of the PPC405CR.
I
5V tolerant
3.3V LVTTL
5
Main system clock input.
I
5V tolerant
3.3V LVTTL
Main system reset. External logic can drive this bidirectional pin low
(minimum of 16 cycles) to initiate a system reset. A system reset can
also be initiated by software. Implemented as an open-drain output
(two states, 0 or open circuit).
I/O
5V tolerant
3.3V LVTTL
Set to 1 when a Machine Check is generated.
O
5V tolerant
3.3V LVTTL
Halt from external debugger.
I
5V tolerant
3.3V LVTTL
System Interface
SysClk
SysReset
SysErr
Halt
26
1, 2
1, 2
AMCC
PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
Table 6. Signal Functional Description (Sheet 5 of 5)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull-up or pull-down required.
7. Pull-up may be required. See “External Bus Control Signals” on page 22.
Signal Name
Description
I/O
Type
Notes
GPIO1[TS1E]
GPIO2[TS2E]
General Purpose I/O
or
Even Trace execution status. To access this function, software must
toggle a DCR register bit.
I/O[O]
5V tolerant
3.3V LVTTL
1, 6
GPIO3[TS1O]
GPIO4[TS2O]
General Purpose I/O
or
Odd Trace execution status. To access this function, software must
toggle a DCR register bit.
I/O[O]
5V tolerant
3.3V LVTTL
1, 6
I/O[O]
5V tolerant
3.3V LVTTL
1
I/O[O]
5V tolerant
3.3V LVTTL
1
General Purpose I/O
GPIO5:8[TS3:6]
GPIO9[TrcClk]
Trace status. To access this function, software must toggle a DCR
register bit.
General Purpose I/O
or
Trace interface clock. A toggling signal that is always half of the CPU
core frequency. To access this function, software must toggle a DCR
register bit.
TestEn
Test Enable.
I
2.5V CMOS
w/pull-down
RcvrInh
Receiver Inhibit. Used only for manufacturing tests. Pull up for normal
operation.
I
5V tolerant
3.3V LVTTL
2
DrvrInh1:2
Driver Inhibit 1 and 2. Used only for manufacturing tests. Pull up for
normal operation.
I
5V tolerant
3.3V LVTTL
2
TmrClk
An external clock input than can be used as an alternative to SysClk
to run the CPU core. Which clock input is used is determined by
software settings.
I
5V tolerant
3.3V LVTTL
1
GND
Ground
Note: Pins J9–J12, K9–K12, L9–L12, and M9–M12 are also thermal
balls.
AVDD
Filtered voltage input for PLL (analog) circuits
OVDD
Output driver voltage—3.3V
Power
VDD
Logic voltage—2.5V
Other pins
Reserved
AMCC
Connect G19 to GND. Do not connect signals, voltage, or ground to
any other reserved pins.
27
Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Table 7. Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to the device
Characteristic
Symbol
Value
Unit
Supply Voltage (Internal Logic)
VDD
0 to +2.7
V
Supply Voltage (I/O Interface)
OVDD
0 to +3.6
V
PLL Supply Voltage
AVDD
0 to +2.7
V
VIN
-0.6 to VDD+0.6
V
Input Voltage (3.3V LVTTL receivers)
VIN
-0.6 to OVDD+0.6
V
Input Voltage (5.0V LVTTL receivers)
VIN
-0.6 to OVDD+2.4
V
Storage Temperature Range
TSTG
-55 to +150
°C
Case temperature under bias
TC
-40 to +120
°C
Input Voltage (2.5V CMOS receivers)
Note: All specified voltages are with respect to GND.
Figure 3. Package Thermal Specifications
The PPC405CR is designed to operate within a case temperature range of -40°C to +85°C. Thermal resistance values for the EPBGA package in a convection environment are as follows:
Thermal Resistance
Junction-to-case
Case-to-ambient
1
Airflow
ft/min (m/sec)
Symbol
Unit
0 (0)
100 (0.51)
200 (1.02)
θJC
2
2
2
°C/W
θCA
18
16
15
°C/W
Notes:
1. For a chip mounted on a JEDEC 2S2P card without a heat sink.
2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist:
a. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board.
b. TA = TC – P×θ CA, where TA is ambient temperature and P is power consumption.
c. TCMax = TJMax – P×θJC, where TJMax is maximum junction temperature and P is power consumption.
28
AMCC
PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
Table 8. Recommended DC Operating Conditions
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Symbol
Minimum
Typical
Maximum
Unit
VDD
+2.3
+2.5
+2.7
V
I/O Supply Voltage
OVDD
+3.0
+3.3
+3.6
V
PLL Supply Voltage
AVDD
+2.3
+2.5
+2.7
V
Input Logic High
(2.5V CMOS receivers)
VIH
+1.7
VDD
V
Input Logic High
(3.3V LVTTL receivers)
VIH
+2.0
OVDD
V
Input Logic High
(5.0V LVTTL receivers)
VIH
+2.0
+5.0
V
Input Logic Low
(2.5V CMOS receivers)
VIL
0
+0.7
V
Input Logic Low
(3.3/5.0V LVTTL receivers)
VIL
0
+0.8
V
Output Logic High
VOH
+2.4
OVDD
V
Output Logic Low
VOL
0
+0.4
V
3.3V I/O Input Current (no pull-up or
pull-down)
IIL1
±10
µA
Input Current (with internal pull-down)
IIL2
±10 (@ 0V)
+400 (@ VDD)
µA
5V Tolerant I/O Input Current 1
IIL4
±10
-650
µA
Input Max Allowable Overshoot
(2.5V CMOS receivers)
VIMAO25
VDD + 0.6
V
Input Max Allowable Overshoot
(3.3V LVTTL receivers)
VIMAO3
OVDD + 0.6
V
Input Max Allowable Overshoot
(5.0V LVTTL receivers)
VIMAO5
+5.5
V
Input Max Allowable Undershoot
VIMAU
Output Max Allowable Overshoot
VOMAO
Output Max Allowable Undershoot
VOMAU3
-0.6
TC
-40
Logic Supply Voltage
Case Temperature
-0.6
Notes
V
OVDD + 0.3
V
V
+85
°C
Notes:
1. See “5V-Tolerant I/O Input Current” on page 30
AMCC
29
Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Figure 4. 5V-Tolerant I/O Input Current
100
0
Input Current (µA)
-100
-200
-300
-400
-500
-600
-700
0.0
1.0
2.0
3.0
4.0
5.0
Input Voltage (V)
Table 9. Input Capacitance
Parameter
Symbol
Maximum
Unit
3.3V LVTTL I/O
CIN1
5.4
pF
5V tolerant LVTTL I/O
CIN2
4.4
pF
RX only pins
CIN4
3.4
pF
30
Notes
AMCC
Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Table 10. DC Electrical Characteristics
Parameter
Symbol
Active Operating Current (VDD)—133MHz
Active Operating Current (OVDD)—133MHz
Active Operating Current (VDD)—200MHz
Typical
Maximum
Unit
IDD
Minimum
TBD
TBD
mA
IODD
TBD
TBD
mA
IDD
400
610
mA
IODD
35
40
mA
IDD
TBD
TBD
mA
Active Operating Current (OVDD)—266MHz
IODD
TBD
TBD
mA
PLL VDD Input current
IPLL
16
23
mA
Active Operating Current (OVDD)—200MHz
Active Operating Current (VDD)—266MHz
Note:
1. Maximum power is characterized at VDD = 2.7V, OVDD = 3.6V, TC = 85 °C, across the silicon process (worse case to best case), while
running an application designed to maximize power consumption. The specification at 200MHz corresponds to CPU = 200 MHz, PLB =
100MHz, OPB = EBC = 50MHz. The 266MHz maximum power was measured with CPU = 266.6MHz, PLB =133.3MHz, OPB = EBC =
66.6MHz.
2. AVDD should be derived from VDD using the following circuit:
AVDD
VDD
L1
+
C1
C2
C1 – 3.3 µF SMT tantalum
C3
AGND
GND
L1 – 2.2 µH SMT inductor (equivalent to MuRata
LQH3C2R2M34) or SMT chip ferrite bead (equivalent
to MuRata BLM31A700S)
C2 – 0.1 µF SMT monolithic ceramic capacitor with X7R
dielectric or equivalent
C3 – 0.01 µF SMT monolithic ceramic capacitor with X7R
dielectric or equivalent
Test Conditions
Clock timing and switching characteristics are specified in accordance with
operating conditions shown in the table “Recommended DC Operating
Conditions.” AC specifications are characterized at OVDD = 3 V and TJ =
+85°C with the 50pF test load shown in the figure at right.
AMCC
Output
Pin
50pF
31
Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Table 11. Clocking Specifications
Symbol
Parameter
Min
Max
Units
CPU
PFC
Processor clock frequency
PTC
Processor clock period
133.33/200/266.66
MHz
7.5/5/3.75
ns
SysClk Input
SCFC
Clock input frequency
25
66.66
MHz
SCTC
Clock period
15
40
ns
SCTCS
Clock edge stability (phase jitter, cycle to cycle)
± 0.15
ns
SCTCH
Clock input high time
40% of nominal period
60% of nominal period
ns
SCTCL
Clock input low time
40% of nominal period
60% of nominal period
ns
66.66
MHz
100
MHz
Note: Input slew rate > 2V/ns
MemClkOut Output
MCOFC
Clock output frequency @ PFC = 133MHz
MCOTC
Clock period @ PFC = 133MHz
MCOFC
Clock output frequency @ PFC = 200MHz
MCOTC
Clock period @ PFC = 200MHz
15
ns
10
MCOFC
Clock output frequency @ PFC = 266MHz
MCOTC
Clock period @ PFC = 266MHz
MCOTCS
Clock edge stability (phase jitter, cycle to cycle)
MCOTCH
Clock output high time
MCOTCL
Clock output low time
ns
133.33
7.5
MHz
ns
± 0.2
ns
45% of nominal period
55% of nominal period
ns
45% of nominal period
55% of nominal period
ns
400
800
MHz
Other Clocks
VCOFC
VCO frequency
PLBFC
PLB frequency @ PFC = 133MHz
66.66
MHz
PLBFC
PLB frequency @ PFC = 200MHz
100
MHz
PLBFC
PLB frequency @ PFC = 266MHz
133.33
MHz
OPBFC
OPB frequency @ PFC = 133MHz
33.33
MHz
OPBFC
OPB frequency @ PFC = 200MHz
50
MHz
OPBFC
OPB frequency @ PFC = 266MHz
66.66
MHz
Figure 5. Timing Waveform
2.0V
1.5V
0.8V
TCH
TCL
TC
32
AMCC
PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC405CR. This controller
uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to
as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the
SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the
PPC405CR the following conditions must be met:
•
•
•
•
The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the
PPC405CR with one or more internal clocks at their maximum supported frequency, the SSCG can only
lower the frequency.
The maximum frequency deviation cannot exceed −3%, and the modulation frequency cannot exceed
40kHz. In some cases, on-board PPC405CR peripherals impose more stringent requirements (see Note 1).
Use the peripheral bus clock (PerClk) for logic that is synchronous to the peripheral bus since this clock
tracks the modulation.
Use the SDRAM MemClkOut since it also tracks the modulation.
Notes:
1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that the
connected device is running at precise baud rates. If an external serial clock is used the baud rate is unaffected by the modulation.
2. IIC operation is unaffected.
Caution: It is up to the system designer to ensure that any SSCG used with the PPC405CR meets the above
requirements and does not adversely affect other aspects of the system.
AMCC
33
Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Table 12. Peripheral Interface Clock Timings
Min
Max
Units
PerClk output frequency—133MHz
Parameter
–
33.33
MHz
PerClk period—133MHz
30
–
ns
PerClk output frequency—200MHz
–
50
MHz
PerClk period—200MHz
20
–
ns
PerClk output frequency—266MHz
–
66.66
MHz
PerClk period—266MHz
15
–
ns
PerClk output high time
45% of nominal period
55% of nominal period
ns
PerClk output low time
45% of nominal period
55% of nominal period
ns
± 0.3
ns
PerClk clock edge stability (phase jitter, cycle to cycle)
–
1000/(2TOPB+2ns)
MHz
UARTSerClk period
2TOPB+2
–
ns
UARTSerClk input high time
TOPB+1
–
ns
UARTSerClk input low time
TOPB+1
–
ns
TmrClk input frequency—133MHz
–
33.33
MHz
TmrClk period—133MHz
30
–
ns
TmrClk input frequency—200MHz
–
50
MHz
TmrClk period—200MHz
20
–
ns
TmrClk input frequency—266MHz
–
66.66
MHz
TmrClk period—266MHz
15
–
ns
TmrClk input high time
40% of nominal period
60% of nominal period
ns
TmrClk input low time
40% of nominal period
60% of nominal period
ns
UARTSerClk input frequency (Note 1)
Notes:
1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maximum OPB clock
frequency is 50MHz for 200MHz parts and 66.66MHz.for 266MHz parts.
34
AMCC
Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Figure 6. Input Setup and Hold Waveform
Clock
TIS min
TIH min
Inputs
Valid
Figure 7. Output Delay and Float Timing Waveform
Clock
Outputs
TOV max
TOV max
TOV max
TOH min
TOH min
TOH min
High (Drive)
Float (High-Z)
Valid
Valid
Low (Drive)
AMCC
35
Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Notes: 1. In all of the following I/O Specifications tables a timing value of na means “not applicable” and dc means
“don’t care.”
2. See “Test Conditions” on page 31 for output capacitive loading.
3. I/O H is specified at 2.4V; I/O L is specified at 0.4V
Table 13. I/O Specifications—All speeds
Input (ns)
Signal
Setup Time
(TIS min)
Output (ns)
Output Current (mA)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(min)
I/O L
(min)
Clock
Notes
Internal Peripheral Interface
IICSCL
n/a
n/a
n/a
n/a
19
12
IICSDA
n/a
n/a
n/a
n/a
19
12
UART0_CTS
n/a
n/a
12
8
UART0_DCD
n/a
n/a
12
8
UART0_DSR
n/a
n/a
12
8
UART0_DTR
UART0_RI
n/a
n/a
n/a
n/a
n/a
UART0_RTS
UART0_Rx
n/a
12
8
12
8
12
8
12
8
UART0_Tx
n/a
n/a
12
8
UART1_RTS
[UART1_DTR]
n/a
n/a
12
8
n/a
n/a
n/a
n/a
UART1_DSR
[UART1_CTS]
n/a
n/a
UART1_Rx
n/a
n/a
UART1_Tx
12
8
n/a
n/a
12
8
TCK
n/a
n/a
TDI
n/a
n/a
async
TDO
12
8
async
TMS
n/a
n/a
async
TRST
n/a
n/a
async
n/a
n/a
12
8
UARTSerClk
n/a
n/a
n/a
n/a
Interrupts Interface
IRQ0:6[GPIO17:23]
JTAG Interface
async
System Interface
DrvrInh1:2
dc
dc
n/a
n/a
GPIO1[TS1E]
GPIO2[TS2E]
GPIO3[TS1O]
GPIO4[TS2O]
GPIO5[TS3]
GPIO6[TS4]
GPIO7[TS5]
GPIO8[TS6]
GPIO9[TrcClk]
Halt
dc
dc
n/a
n/a
n/a
n/a
RcvrInh
dc
dc
n/a
n/a
n/a
n/a
async
SysClk
n/a
n/a
n/a
n/a
SysErr
n/a
n/a
12
8
async
SysReset
10
1
12
8
async
TestEn
dc
dc
n/a
n/a
n/a
n/a
async
TmrClk
dc
dc
n/a
n/a
n/a
n/a
async
36
AMCC
Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Table 14. I/O Specifications—133 and 200MHz
Notes:
1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM.
2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.
3. SDRAM interface hold times are guaranteed at the PPC405CR package pin. System designers must use the PPC405CR
IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections,
and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
5. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns)
Signal
Output (ns)
Output Current (mA)
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(min)
I/O L
(min)
Clock
Notes
BA1:0
n/a
n/a
7.3
1
19
12
MemClkOut
1, 2
BankSel0:3
n/a
n/a
5.8
1
19
12
MemClkOut
2
CAS
n/a
n/a
7.3
1
19
12
MemClkOut
1, 2
2
SDRAM Interface
ClkEn0:1
n/a
n/a
4.7
1
40
25
MemClkOut
DQM0:3
n/a
n/a
6.2
1
19
12
MemClkOut
2
DQMCB
n/a
n/a
6
1
19
12
MemClkOut
2
ECC0:7
MemAddr12:0
MemData0:31
2
1
6
1
19
12
MemClkOut
2
n/a
n/a
7.8
1
19
12
MemClkOut
1, 2
2
1
6.2
1
19
12
MemClkOut
2
RAS
n/a
n/a
7.4
1
19
12
MemClkOut
1, 2
WE
n/a
n/a
7.4
1
19
12
MemClkOut
1, 2
External Slave Peripheral Interface
DMAAck0:3
n/a
n/a
8
0
12
8
PerClk
DMAReq0:3
dc
dc
n/a
n/a
n/a
n/a
PerClk
EOT0:3/TC0:3
dc
dc
9
0
12
8
PerClk
PerAddr0:31
4
1
10
0
19
12
PerClk
PerBLast
4
1
8
0
12
8
PerClk
n/a
n/a
9
0
12
8
PerClk
PerClk
PerCS0
PerCS1:7[GPIO10:16]
PerData0:31
PerOE
PerPar0:3
6
1
10
0
19
12
n/a
n/a
8
0
12
8
PerClk
4
1
10.5
0
19
12
PerClk
PerR/W
5
1
8
0
12
8
PerClk
PerReady
9
1
n/a
n/a
n/a
n/a
PerClk
PerWBE0:3
4
1
8
0
12
8
PerClk
PerClk
External Master Peripheral Interface
BusReq
n/a
n/a
8
0
12
8
ExtAck
n/a
n/a
8
0
12
8
PerClk
ExtReq
6
1
n/a
n/a
n/a
n/a
PerClk
PerClk
ExtReset
n/a
n/a
8
0
19
12
HoldAck
n/a
n/a
8
0
12
8
PerClk
HoldPri
4
1
n/a
n/a
n/a
n/a
PerClk
HoldReq
6
1
n/a
n/a
n/a
n/a
PerClk
PerClk
n/a
n/a
0.9
0.9
19
12
PLB Clk
PerErr
4
1
n/a
n/a
n/a
n/a
PerClk
AMCC
4
37
Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Table 15. I/O Specifications—266MHz
Notes:
1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM.
2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.
3. SDRAM interface hold times are guaranteed at the PPC405CR package pin. System designers must use the PPC405CR
IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections,
and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
5. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns)
Signal
Output (ns)
Output Current (mA)
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(min)
I/O L
(min)
Clock
Notes
BA1:0
n/a
n/a
5.5
1
19
12
MemClkOut
1, 2
BankSel0:3
n/a
n/a
4.5
1
19
12
MemClkOut
2
CAS
n/a
n/a
5.5
1
19
12
MemClkOut
1, 2
SDRAM Interface
ClkEn0:1
n/a
n/a
3.9
1
40
25
MemClkOut
2
DQM0:3
n/a
n/a
4.9
1
19
12
MemClkOut
2
DQMCB
n/a
n/a
4.7
1
19
12
MemClkOut
2
ECC0:7
1.5
1
4.7
1
19
12
MemClkOut
2
MemAddr12:0
n/a
n/a
5.9
1
19
12
MemClkOut
1, 2
MemData0:31
1.5
1
4.8
1
19
12
MemClkOut
2
RAS
n/a
n/a
5.6
1
19
12
MemClkOut
1, 2
WE
n/a
n/a
5.6
1
19
12
MemClkOut
1, 2
External Slave Peripheral Interface
DMAAck0:3
n/a
n/a
6
0
12
8
PerClk
DMAReq0:3
dc
dc
n/a
n/a
n/a
n/a
PerClk
EOT0:3/TC0:3
dc
dc
8
0
12
8
PerClk
PerAddr0:31
3
1
8
0
19
12
PerClk
PerBLast
3.5
1
6
0
12
8
PerClk
PerCS0
PerCS1:7[GPIO10:16]
n/a
n/a
6
0
12
8
PerClk
PerClk
PerData0:31
5
1
8
0
19
12
PerOE
n/a
n/a
6
0
12
8
PerClk
PerPar0:3
3.5
1
8
0
19
12
PerClk
PerClk
PerR/W
PerReady
PerWBE0:3
4
1
6
0
12
8
6.5
1
n/a
n/a
n/a
n/a
PerClk
3
1
6
0
12
8
PerClk
External Master Peripheral Interface
BusReq
n/a
n/a
6
0
12
8
PerClk
ExtAck
n/a
n/a
6
0
12
8
PerClk
ExtReq
5
1
n/a
n/a
n/a
n/a
PerClk
ExtReset
n/a
n/a
6
0
19
12
PerClk
HoldAck
n/a
n/a
6
0
12
8
PerClk
HoldPri
3
1
n/a
n/a
n/a
n/a
PerClk
HoldReq
5
1
n/a
n/a
n/a
n/a
PerClk
PerClk
n/a
n/a
0.9
0.9
19
12
PLB Clk
PerErr
3
1
n/a
n/a
n/a
n/a
PerClk
38
4
AMCC
PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
Strapping
When the SysReset input is driven low by an external device (system reset), the state of certain I/O pins is read to
enable default initial conditions prior to PPC405CR start-up. The actual capture instant is the nearest SysClk edge
before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down
(logical 0) resistors to select the desired default conditions. The recommended pull-up is 3kΩ to +3.3V or 10kΩ to
+5V. The recommended pull-down is 1KΩ to GND. These pins are use for strap functions only during reset. They
are used for other signals during normal operation. The following table lists the strapping pins along with their functions and strapping options. The signal names assigned to the pins for normal operation follow the pin number.
Table 16. Strapping Pin Assignments (Sheet 1 of 2)
Function
PLL Tuning
Option
for 6 ≤ M ≤ 7 use choice 3
for 7 < M ≤ 12 use choice 5
for 12 < M ≤ 32 use choice 6
See Note.
U13
UART0_DTR
V20
UART0_RTS
Choice 1; TUNE[5:0] = 010001
0
0
0
Choice 2; TUNE[5:0] = 010010
0
0
1
Choice 3; TUNE[5:0] = 010011
0
1
0
Choice 4; TUNE[5:0] = 010100
0
1
1
Choice 5; TUNE[5:0] = 010101
1
0
0
Choice 6; TUNE[5:0] = 010110
1
0
1
Choice 7; TUNE[5:0] = 010111
1
1
0
1
1
1
C16
DMAAck0
B17
DMAAck1
Choice 8; TUNE[5:0] = 100100
PLL Forward Divider
2
PLL Feedback Divider
PLB Divider from
OPB Divider from
AMCC
Ball Strapping
W15
UART0_Tx
1
Bypass mode
0
0
Divide by 3
0
1
Divide by 4
1
0
Divide by 6
1
1
B16
DMAAck2
A14
DMAAck3
Divide by 1
0
0
Divide by 2
0
1
Divide by 3
1
0
Divide by 4
1
1
B18
GPIO1[TS1E]
D16
GPIO2[TS2E]
Divide by 1
0
0
Divide by 2
0
1
Divide by 3
1
0
Divide by 4
1
1
T4
HoldAck
U5
ExtAck
Divide by 1
0
0
Divide by 2
0
1
Divide by 3
1
0
Divide by 4
1
1
2
CPU2, 3
PLB2
39
PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
Table 16. Strapping Pin Assignments (Sheet 2 of 2)
Function
External Bus Divider from PLB
Option
Ball Strapping
C17
GPIO3[TS1O]
P18
GPIO4[TS2O]
Divide by 2
0
0
Divide by 3
0
1
Divide by 4
1
0
Divide by 5
1
1
Y5
UART1_Tx
W6
UART1_RTS/
UART1_DTR
2, 3
ROM Width
8-bit ROM
0
0
16-bit ROM
0
1
32-bit ROM
1
0
Reserved
1
1
Note:
1. The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the
PPC405CR. These bits are shown for information only; and do not require modification except in special clocking circumstances such as
spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405CR, visit the technical
documents area of the AMCC PowerPC web site.
2. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in “Clocking
Specifications” on page 32. Further requirements are detailed in the Clocking chapter of the PowerPC 405CR Embedded Processor
User’s Manual.
3. Additional consideration must be given to pins that normally function as Trace signals. Improved design margin can be gained by using
three-state buffers instead of strapping resistors, and minimizing trace lengths and stubs.
40
AMCC
Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Document Revision History
Revision
Date
1.01
08/05/04
Initial release
1.02
01/11/05
Add lead-free part numbers.
AMCC
Description
41
PPC405CR – PowerPC 405CR Embedded Processor
Revision 1.02 – January 11, 2005
Data Sheet
Applied Micro Circuits Corporation
6290 Sequence Dr., San Diego, CA 92121
Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885
http://www.amcc.com
AMCC reserves the right to make changes to its products, its data sheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available data
sheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions and limitations.
AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under
its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower
grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE
SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL
APPLICATIONS.
AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2005 Applied Micro Circuits Corporation.
42
AMCC