AMSCO AS1529-BTDT

Da t as heet
AS1528/AS1529
M i c r o - P o w e r, 1 0 - B i t , 1 5 0 k s ps , A D C , S i n g l e E n d e d
or Differential
1 General Description
2 Key Features
The AS1528/AS1529 are low-power, 10-bit analog-todigital converters (ADCs) designed to operate with a single +2.7V to +5.25V supply. Excellent dynamic performance, low power consumption, and simplicity make
these devices perfect for portable battery-powered dataacquisition applications.
!
Single-Supply Operation: +2.7V to +5.25V
!
Automatic Shutdown Between Conversions
!
Low Power Consumption
- 350µA @ 150ksps
The devices are available as the standard products
listed in Table 1.
- 245µA @ 100ksps
- 24µA @ 10ksps
Table 1. Standard Products
Model
Input Type
Input Voltage
AS1528
1-Channel, Pseudo /
True-Differential
0 to VREF /
-VREF/2 to VREF/2
AS1529
2-Channel, SingleEnded
0 to VREF
The devices feature a successive-approximation register (SAR), automatic shutdown, fast wakeup (1.4µs),
and low-power consumption at the maximum sampling
rate of 150ksps.
Automatic shutdown (0.2µA) between conversions
results in reduced power consumption (at slower
throughput rates).
Data access are made via an external clock through the
SPI-/QSPI-/MICROWIRE-compatible 3-wire high-speed
serial interface.
The AS1529/AS1528 are available in a 8-pin TDFN
(3x3mm) package.
- 2.5µA @ 1ksps
- 200nA in Automatic Shutdown Mode
!
True-Differential Track/Hold, 150kHz Sampling Rate
Software-Configurable Unipolar/Bipolar Conversion
(AS1528)
!
Input Common Mode Range from GND to VDD
!
3-Wire SPI-/QSPI-/MICROWIRE-Compatible Serial
Interface
!
Internal Conversion Clock
!
8-pin TDFN (3x3mm) Package
3 Applications
The devices are ideal for remote sensors, data-acquisition, data logging devices, lab instruments, or for any
other space-limited A/D devices with low power consumption and single-supply requirements.
Figure 1. AS1528/AS1529 - Block Diagram
1
AS1528/AS1529
VDD
7
CNVST
8
Osc
Input
Shift
Register
SCLK
Control
Logic
2
AIN1/AIN+
2
Track/
Hold
10-Bit
SAR
6
DOUT
AIN2/AIN4
5
REF
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GND
Revision 1.02
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AS1528/AS1529
Datasheet
Contents
1 General Description
............................................................................................................................. 1
2 Key Features
........................................................................................................................................ 1
3 Applications
.......................................................................................................................................... 1
4 Pinout
................................................................................................................................................... 3
Pin Assignment
................................................................................................................................................... 3
Pin Description
..................................................................................................................................................... 3
5 Absolute Maximum Ratings
6 Electrical Characteristics
Timing Characteristics
................................................................................................................. 4
...................................................................................................................... 5
......................................................................................................................................... 7
7 Typical Operating Characteristics
8 Detailed Description
........................................................................................................ 8
........................................................................................................................... 11
True Differential Analog Input Track/Hold
Selecting AIN1 or AIN2 (AS1529)
.......................................................................................................... 11
...................................................................................................................... 11
Selecting Unipolar or Bipolar Conversions (AS1528)
Input Bandwidth
Analog Input Protection
Internal Clock
.........................................................................................12
..................................................................................................................................................13
......................................................................................................................................13
......................................................................................................................................................13
Output Data Format
Transfer Function
............................................................................................................................................13
................................................................................................................................................13
9 Application Information
....................................................................................................................... 15
Automatic Shutdown Mode
External Reference
.................................................................................................................................15
.............................................................................................................................................15
Performing a Conversion
....................................................................................................................................15
Standard Interface Connections ..........................................................................................................................15
SPI and Microwire Interface ........................................................................................................................... 15
QSPI Interface ................................................................................................................................................16
PIC16 and SSP Module and PIC17 Interface ................................................................................................17
Layout and Grounding Considerations
10 Package Drawings and Markings
11 Ordering Information
.............................................................................................................. 19
.................................................................................................... 20
........................................................................................................................ 21
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AS1528/AS1529
Datasheet - P i n o u t
4 Pinout
Pin Assignment
Figure 2. Pin Assignments (Top View)
VDD 1
AIN1/AIN+ 2
AIN2/AIN- 3
8 SCLK
AS1528/
AS1529
GND 4
7 DOUT
6 CNVST
5 REF
Pin Description
Table 2. Pin Description
Pin Number
Pin Name
Description
Positive Supply Voltage. +2.7V to +5.25V.
Note: Bypass with a 0.1µF capacitor to GND.
1
VDD
2
AIN1/AIN+
Analog Input Channel 1 (AS1529) or Positive Analog Input (AS1528)
3
AIN2/AIN-
Analog Input Channel 2 (AS1529) or Negative Analog Input (AS1528)
4
GND
Ground
5
REF
External Reference Voltage Input. Sets the analog voltage range.
Note: Bypass with a 4.7µF capacitor to GND.
CNVST
Conversion Start. A rising edge powers up the device and puts the track/
hold circuitry in track mode. At the falling edge of this pin, the device enters
hold mode and begins a conversion.
Note: This pin also selects the input channel (AS1529) or input polarity
(AS1528).
7
DOUT
Serial Data Output. This pin transitions the falling edge of SCLK and goes
low at the start of a conversion and delivers the MSB at the completion of a
conversion.
Note: This pin goes high impedance once data has been fully clocked out.
8
SCLK
Serial Clock Input. Clocks out data at DOUT with the MSB first.
6
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AS1528/AS1529
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 5 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 3. Absolute Maximum Ratings
Parameter
Min
Max
Units
VDD to GND
-0.3
+6
V
CNVST, SCLK, DOUT, REF, AIN1/
AIN+, AIN2/AIN- to GND
-0.3
VDD +
0.3
V
Current into Any Pin
50
mA
Continuous Power Dissipation
1491
Operating Temperature Range
-40
+85
ºC
Storage Temperature Range
-60
+150
ºC
Package Body Temperature
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mW
+260
Comments
ºC
Revision 1.02
TAMB = +70ºC; derate 19.5mW/ºC above +70ºC
The reflow peak soldering temperature (body
temperature) specified is in accordance with
IPC/JEDEC J-STD-020D “Moisture/Reflow
Sensitivity Classification for Non-Hermetic Solid
State Surface Mount Devices”.
The lead finish for Pb-free leaded packages is
matte tin (100% Sn).
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AS1528/AS1529
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
VDD = +2.7 to +5.25V, VREF = +2.5V, 4.7µF Capacitor at REF; fSCLK = 8MHz (50% Duty Cycle); AIN- = GND (AS1528)
TAMB = TMIN to TMAX (unless otherwise specified). Typical Values at TAMB = +25ºC. Unipolar Mode (AS1528).
Table 4. Electrical Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
DC Accuracy
Resolution
INL
Relative Accuracy
DNL
Differential Non-Lineraity
10
Bits
No Missing Codes Over Temperature
±0.275
LSB
±0.275
LSB
Offset Error
±0.25
±2
LSB
1
±0.25
±2
LSB
Gain Error
Gain Temp Coefficient
±0.3
ppm/ºC
Offset Temp Coefficient
±0.3
ppm/ºC
Channel-to-Channel Offset
Match
±0.025
LSB
Channel-to-Channel Gain
Match
±0.025
LSB
Dynamic Specifications – (fIN (sinewave) = 10kHz, VIN = 2.5VP-P, 150ksps, fSCLK = 8MHz (50% duty cycle), AIN- =
GND (AS1528)
SINAD
Signal-to-Noise Plus Distortion
61.5
dB
THD
Total Harmonic Distortion (to
the 5th Harmonic)
-79.5
dB
SFDR
Spurious-Free Dynamic Range
84
dB
Full Power Bandwidth
-3dB Point
20
MHz
Full Linear Bandwidth
-0.1dB Point
400
kHz
Exclusive of tACQ
3.3
Conversion Rate
tCONV
Conversion Time
tACQ
Track/Hold Acquisition Time
Aperture Delay
fSCLK
3.7
µs
1.4
µs
30
Max Serial Clock Frequency
ns
8
MHz
30
70
%
Unipolar
0
VREF
Bipolar
-VREF/2
VREF/2
Serial Clock Duty Cycle
Analog Input
VIN Range
2
Input Leakage Current
Input Capacitance
V
No Channel Selected or Conversion
Halted
±0.01
Track Mode
20
pF
Hold Mode
5
pF
±1
µA
External Reference Input
VREF
VIN Range
IREF
Input Current
VREF = +2.5V @ 150ksps
11
VREF = +4.096V @ 150ksps
19
Acquisition Between Conversions
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VDD +
50mV
1.0
Revision 1.02
0
+2
V
25
µA
+5
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AS1528/AS1529
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 4. Electrical Characteristics (Continued)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
0.3VDD
V
Digital Inputs/Outputs (CNVST, SCLK, DOUT)
VIL
Input Low Voltage
VIH
Input High Voltage
ILEAK
Input Leakage Current
±0.01
CIN
Input Capacitance
15
VOL
Output Low Voltage
VOH
Output High Voltage
ISOURCE = 1.5mA
Tri-State Leakage Current
CNVST = GND
±0.05
Tri-State Output Capacitance
CNVST = GND
15
0.7VDD
V
±1.0
µA
pF
ISINK = 2mA
0.4
ISINK = 4mA
0.8
0.7VDD
V
V
±5
µA
pF
Power Requirements
VDD
IDD
PSR
Positive Supply Voltage
Positive Supply Current
Power Supply Rejection
2.7
5.25
VDD = +3V, fSAMPLE = 150ksps
350
VDD = +3V, fSAMPLE = 100ksps
245
VDD = +3V, fSAMPLE = 10ksps
24
VDD = +3V, fSAMPLE = 1ksps
2.5
VDD = +5V, fSAMPLE = 150ksps
485
VDD = +5V, fSAMPLE = 100ksps
330
VDD = +5V, fSAMPLE = 10ksps
33
VDD = +5V, fSAMPLE = 1ksps
3.7
Automatic Shutdown Mode
0.2
VDD = +5V ±5%, Full Scale Input
±0.3
VDD = +2.7V to 3.6V, Full Scale Input
±0.4
V
400
550
µA
1
mV
1. Offset nulled.
2. The absolute input voltage range for the analog inputs is from GND to VDD.
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AS1528/AS1529
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Timing Characteristics
VDD = +2.7 to +5.25V, VREF = +2.5V, 4.7µF Capacitor at REF; fSCLK = 8MHz (50% Duty Cycle); AIN- = GND (AS1528)
TAMB = TMIN to TMAX (unless otherwise specified). Typical Values at TAMB = +25ºC.
Table 5. Timing Characteristics
Parameter
Symbol
SCLK Pulse Width High
tCH
38
ns
SCLK Pulse Width Low
tCL
38
ns
SCLK Falling-to-DOUT
Transition
tDOT
CLOAD = 30pF (see Figure 3, Figure 4,
Figure 18 on page 11, Figure 19 on
page 11)
tDOD
CLOAD = 30pF (see Figure 3, Figure 4,
Figure 18 on page 11, Figure 19 on
page 11)
CNVST Falling-to-MSB Vlid
tCONV
CLOAD = 30pF (see Figure 3, Figure 4,
Figure 18 on page 11, Figure 19 on
page 11)
CNVST Pulse Width
tCSW
SCLK Rising-to-DOUT
Disable
1
Conditions
Min
Typ
100
Max
Units
28
60
ns
200
500
ns
3.3
3.7
µs
30
ns
1. Guaranteed by Design and Characterisation.
Figure 3. DOUT Enable/Disable Time Load Circuits
VDD
DOUT
6kΩ
6kΩ
CLOAD
DOUT
GND
GND
CLOAD
High-impedance to VOH, VOL to VOH, and VOH to High-impedance
GND
Figure 4. Detailed Serial Interface Timing Diagram
CNVST
tCL
tCH
tCSW
SCLK
tDOT
High Z
DOUT
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tDOD
Revision 1.02
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AS1528/AS1529
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
7 Typical Operating Characteristics
VDD = 5V; VREF = 2.5V, fSCLK = 8MHz(50% duty), CREF = 4.7µF, TAMB = +25ºC (unless otherwise specified).
Figure 5. Integral Nonlinearity vs. Digital Output Code
Figure 6. Differential Nonlinearity vs. Digital Output Code
0.25
fSAMPLE = 150ksps
0.2
0.2
0.15
0.15
0.1
0.1
DNL (LSB) .
INL (LSB) .
0.25
0.05
0
-0.05
fSAMPLE = 150ksps
0.05
0
-0.05
-0.1
-0.1
-0.15
-0.15
-0.2
-0.2
-0.25
-0.25
0
256
512
768
0
1024
Figure 7. Supply Current vs. Supply Voltage
512
768
1024
Figure 8. Supply Current vs. Temperature
600
500
450
500
fSAMPLE = 150ksps
Supply Current (µA) .
Supply Current (µA) .
256
Digital Output Code
Digital Output Code
400
300
200
100
150ksps
400
350
300
100ksps
250
200
150
100
50
10ksps
1ksps
0
2.7
3.2
3.7
4.2
4.7
0
-45 -30 -15 0
5.2
Supply Voltage (V)
15 30 45 60 75 90
Temperature (°C)
Figure 9. Supply Current vs. Temperature, VDD = 3V
Figure 10. Supply Current vs. Sampling Rate
360
1000
150ksps
280
240
100ksps
200
160
120
80
Supply Current (µA) .
Supply Current (µA) .
320
100
10
1
0.1
10ksps
40
1ksps
0
-45 -30 -15 0
15 30 45 60 75 90
0.01
0.01
Temperature (°C)
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0.1
1
10
100
1000
Sampling Rate (ksps)
Revision 1.02
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AS1528/AS1529
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 11. Shutdown Current vs. Supply Voltage
100
9
90
.
.
8
Shutdown Current (nA)
Shutdown Current (nA)
Figure 12. Shutdown Current vs. Temperature
10
7
6
5
4
3
2
1
80
70
60
50
40
30
20
10
0
2.7
3.2
3.7
4.2
4.7
0
-45 -30 -15 0
5.2
Supply Voltage (V)
Figure 13. Offset Error vs. Supply Voltage
Figure 14. Offset Error vs. Temperature
1
Gain Error (LSB) .
Offset Error (LSB)
.
1
0.5
0
-0.5
2.7
3.2
3.7
4.2
4.7
0.5
0
-0.5
-1
-45 -30 -15
-1
5.2
0
15 30 45 60 75 90
Temperature (°C)
Supply Voltage (V)
Figure 15. Gain Error vs. Supply Voltage
Figure 16. Gain Error vs. Temperature
1
Gain Error (LSB) .
1
Gain Error (LSB) .
15 30 45 60 75 90
Temperature (°C)
0.5
0
-0.5
-1
2.7
3.2
3.7
4.2
4.7
5.2
0.5
0
-0.5
-1
-45 -30 -15
Supply Voltage (V)
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0
15
30 45 60 75 90
Temperature (°C)
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AS1528/AS1529
Datasheet - D e t a i l e d D e s c r i p t i o n
8 Detailed Description
The AS1528/AS1529 employ a successive approximation conversion (SAR) technique and integrated track/hold circuitry to convert analog signals into 10-bit digital output. The serial interface provides easy interfacing to microprocessors. Figure 17 shows the simplified internal structure for the AS1529 (2-channels, single ended) and the AS1528
(1-channel, true differential).
True Differential Analog Input Track/Hold
The equivalent circuit of Figure 17 shows the device input architecture which is composed of track/hold circuitry, input
multiplexer, comparator, and switched-capacitor DAC. The track/hold circuitry enters its tracking mode on the rising
edge of CNVST. The positive input capacitor is connected to AIN1 or AIN2 (AS1529) or AIN+ (AS1528). The negative
input capacitor is connected to GND (AS1529) or AIN- (AS1528).
Figure 17. Equivalent Input Circuit
REF
10-Bit Capacitive DAC
GND
AIN2
AIN1/AIN+
CIN+
+
Hold
CIN–
GND/AIN-
RIN-
RIN+
Hold
VDD/2
Comparator
Hold
Track
The track/hold circuitry enters its hold mode on the falling edge of CNVST and the difference between the sampled
positive and negative input voltages is converted. The time required for the track/hold to acquire an input signal is
determined by how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens, and CNVST must be held high for a longer period of time. The acquisition time (tACQ) is the maximum time needed for the signal to be acquired, plus the power-up time. tACQ is calculated by:
tACQ = 9 x (RS + RIN) x 20pF + tPWR
(EQ 1)
Where:
RS is the source impedance of the input signal;
RIN = 1.5kΩ;
tPWR of 1µs is the power-up time of the device.
Note:
tACQ is never less than 1.4µs and any source impedance below 300. does not significantly affect the AS1528/
AS1529 AC performance. A high-impedance source can be accommodated either by lengthening tACQ or by
placing a 1µF capacitor between the positive and negative analog inputs.
Selecting AIN1 or AIN2 (AS1529)
Select one of the AS1529 two positive input channels using the CNVST pin (see page 3). If AIN1 is selected (see Figure 18), drive CNVST high to power up the AS1529 and place the track/hold circuitry in track mode with AIN1 connected to the positive input capacitor. Hold CNVST high for tACQ to fully acquire the signal. Drive CNVST low to place
the track/hold circuitry in hold mode. The AS1529 then performs a conversion and shutdown automatically. The MSB is
available at DOUT after 3.7µs. Data can then be clocked out using SCLK. Clock out all 12 bits of data before driving
CNVST high for the next conversion. If all 12 bits of data are not clocked out before CNVST is driven high, AIN2 is
selected for the next conversion.
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AS1528/AS1529
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 18. Single Conversion – AIN1 vs. GND (AS1529), Unipolar Mode AIN+ vs. AIN- (AS1528)
Sampling Instant
tCONV
tACQ
CNVST
SCLK
DOUT
1
High Z
B9
MSB
4
B8
B7
B6
8
B5
B4
B3
B2
12
B1
B0
LSB
ZERO ZERO
High Z
If AIN2 is selected (see Figure 19), drive CNVST high for at least 30ns. Next, drive CNVST low for at least 30ns, and
then high again. This powers up the AS1529 and places the track/hold circuitry in track mode with AIN2 connected to
the positive input capacitor. Next hold CNVST high for tACQ to fully acquire the signal. Drive CNVST low to place the
track/hold circuitry in hold mode. The AS1529 then performs a conversion and shuts down automatically. The MSB is
available at DOUT after 3.7µs. Data can then be clocked out using SCLK.
Note: If all 12 bits of data are not clocked out before CNVST is driven high, AIN2 is selected for the next conversion.
Selecting Unipolar or Bipolar Conversions (AS1528)
True-differential conversion (with the AS1528 unipolar and bipolar modes) is selected using pin CNVST (see page 3).
AIN+ and AIN- are sampled at the falling edge of CNVST. In unipolar mode, AIN+ can exceed AIN- by up to VREF. The
output format is straight binary. In bipolar mode, either input can exceed the other by up to VREF/2. The output format is
two’s complement. In both modes, the input common mode range can go from GND to VDD.
Figure 19. Single Conversion – AIN2 vs. GND (AS1529), Bipolar Mode AIN+ vs. AIN- (AS1528)
Sampling Instant
tCONV
tACQ
CNVST
SCLK
DOUT
1
High Z
B9
MSB
4
B8
B7
B6
8
B5
B4
B3
B2
12
B1
B0
LSB
ZERO ZERO
High Z
Note: In unipolar and bipolar modes, AIN+ and AIN- must not exceed VDD by more than 50mV or be lower than GND
by more than 50mV.
If unipolar mode is selected (see Figure 18), drive CNVST high to power up the AS1528 and place the track/hold circuitry in track mode with AIN+ and AIN- connected to the input capacitors. Hold CNVST high for tACQ to fully acquire
the signal. Drive CNVST low to place the track/hold circuitry in hold mode. The AS1528 then performs a conversion
and shutdown automatically. The MSB is available at DOUT after 3.7µs. Data can then be clocked out using SCLK.
Clock out all 12 bits of data before driving CNVST high for the next conversion. If all 12 bits of data are not clocked out
before CNVST is driven high, bipolar mode is selected for the next conversion.
If bipolar mode is selected (see Figure 19), drive CNVST high for at least 30ns. Next, drive CNVST low for at least
30ns and then high again. This places the track/hold circuitry in track mode with AIN+ and AIN- connected to the input
capacitors.
Next hold CNVST high for tACQ to fully acquire the signal. Drive CNVST low to place the track/hold circuitry in hold
mode. The AS1528 then performs a conversion and shuts down automatically. The MSB is available at DOUT after
3.7µs. Data can then be clocked out using SCLK.
Note: If all 12 bits of data are not clocked out before CNVST is driven high, bipolar mode is selected for the next conversion.
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AS1528/AS1529
Datasheet - D e t a i l e d D e s c r i p t i o n
Input Bandwidth
The AS1528/AS1529 input tracking circuitry has a 20MHz small signal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the AS1528/AS1529 sampling rate
by using undersampling techniques.
Note: To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes that clamp the analog input to VDD and GND allow the analog input pins to swing from GND
- 0.3V to VDD + 0.3V without damage. Both inputs must not exceed VDD by more than 50mV or be lower than GND by
more than 50mV for accurate conversions.
Note: If an off-channel analog input voltage exceeds the supply voltages, the input current should be limited to 2mA.
Internal Clock
The AS1528/AS1529 operate from an internal clock, which is accurate within 5% of the 4MHz clock rate. This results in
a worst-case conversion time of 3.7µs. The internal clock releases the system microprocessor from running the SAR
conversion clock and allows the conversion results to be read back at the processor’s convenience, at any clock rate
from 0 to 8MHz.
Output Data Format
Figure 18 on page 11 and Figure 19 on page 11 illustrate the conversion timing for the AS1528/AS1529. The 10-bit
conversion result is output in MSB-first format. Data on DOUT transitions on the falling edge of SCLK. All 10 bits must
be clocked out before CNVST transitions again.
For the AS1528, data is straight binary for unipolar mode and two’s complement for bipolar mode. For the AS1529,
data is always straight binary.
Transfer Function
Figure 20 on page 12 shows the unipolar transfer function for the AS1528/AS1529. Figure 21 on page 13 shows the
bipolar transfer function for the AS1528. Code transitions occur halfway between successive-integer LSB values.
Figure 20. AS1528/AS1529 Unipolar Transfer Function
Full Scale = VREF
Zero Scale = GND
1 LSB = VREF/4096
Full-Scale
Transition
11...111
11...110
Output Code
11....101
00...011
00...010
00...001
00...000
0
1
2
3
FS-3/2 LSB FS
Input Voltage (LSB)
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AS1528/AS1529
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 21. AS1528 Bipolar Transfer Function
Full Scale = VREF/2
-Full Scale = -VREF/2
Zero Scale = 0
1 LSB = VREF/4096
011...111
011...110
Output Code
000...010
000...001
000...000
111...111
111...110
111...101
100...001
100...000
-FS
0
+FS-1 LSB
Input Voltage (LSB)
VCOM ≥ VREF /2
VIN = AIN+ - AIN-
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AS1528/AS1529
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
9 Application Information
Automatic Shutdown Mode
With CNVST low, the AS1528/AS1529 default to automatic shutdown (< 0.2µA) mode after power-up and between
conversions. After detecting a rising edge of CNVST, the AS1528/AS1529 powers up, sets DOUT low, and enters
track mode.
After detecting a falling edge of CNVST, the device enters hold mode and begins the conversion. A maximum of 3.7µs
later, the device completes conversion, enters shutdown, and MSB is available at DOUT.
External Reference
An external reference is required for the AS1528/AS1529. Use a 4.7µF bypass capacitor for best performance. The
reference input structure allows a voltage range of +1V to VDD + 50mV.
Performing a Conversion
1. Use a general-purpose I/O line on the CPU to hold CNVST low between conversions.
2. Drive CNVST high to acquire AIN1(AS1529) or unipolar mode (AS1528). To acquire AIN2 (AS1529) or bipolar
mode (AS1528), drive CNVST low and high again.
3. Hold CNVST high for 1.4µs.
4. Drive CNVST low and wait approximately 3.7µs for conversion to complete. After 3.7µs, the MSB is available
at DOUT.
5. Activate SCLK for a minimum of 12 rising clock edges. DOUT transitions on SCLK’s falling edge and is available in MSB-first format. Observe the SCLK to DOUT valid timing characteristic. Clock data into the µP on
SCLK’s rising edge.
Standard Interface Connections
The AS1528/AS1529 serial interface is fully compatible with SPI, QSPI, and MICROWIRE. If a serial interface is available, establish the processor’s serial interface as a master so that the CPU generates the serial clock for the AS1528/
AS1529 and select a clock frequency up to 8MHz.
SPI and Microwire Interface
When using an SPI (Figure 22) or Microwire interface (Figure 23), set CPOL = CPHA = 0. Two 8-bit readings are necessary to obtain the entire 10-bit result from the AS1528/AS1529. DOUT data transitions on the serial clock’s falling
edge and is clocked into the processor on SCLK’s rising edge. The first 8-bit data stream contains the first 8-bits of
DOUT starting with the MSB. The second 8-bit data stream contains the remaining four result bits. DOUT then goes
high impedance.
Figure 22. SPI Serial Interface Connections
8
SCK
SSM
CPU
SCLK
6
I/O
CNVST
AS1528/
AS1529
7
MISO
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Revision 1.02
DOUT
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AS1528/AS1529
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 23. Microwire Serial Interface Connections
8
SK
SCLK
I/O
CNVST
AS1528/
AS1529
6
CPU
7
SI
DOUT
Figure 24. SPI/Microwire Interface Timing Diagram (CPOL = CPHA = 0)
Sampling Instant
1st Byte Read
CNVST
SCLK
1
DOUT
B9
MSB
2nd Byte Read
4
B8
B7
B6
8
B5
B4
B3
12
B2
B0
LSB
B1
ZERO ZERO
16
High Z
QSPI Interface
Using the high-speed QSPI interface (Figure 25) with CPOL = 0 and CPHA = 0, the AS1528/AS1529 support a maximum fSCLK of 8MHz. One 12- to 16-bit reads are necessary to obtain the entire 10-bit result from the AS1528/AS1529.
DOUT data transitions on the serial clock’s falling edge and is clocked into the processor on SCLK’s rising edge. The
first 10 bits are the data. DOUT then goes high impedance (see Figure 23).
Figure 25. QSPI Serial Interface Connections
8
SSM
CPU
SCK
SCLK
CSM
CNVST
MISO
DOUT
6
AS1528/
AS1529
7
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AS1528/AS1529
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 26. QSPI Serial Interface Timing (CPOL = CPHA = 0)
Sampling Instant
CNVST
SCLK
1
DOUT
B9
MSB
4
B8
B7
8
B6
B5
B4
B3
12
B2
B1
B0
LSB
ZERO ZERO
16
High Z
PIC16 and SSP Module and PIC17 Interface
The AS1528/AS1529 are compatible with a PIC16/PIC17 controllers, using the synchronous serial port (SSP) module
To establish SPI communication, connect the PIC16/PIC17 controllers as shown in Figure 27 and configure the PIC16/
PIC17 as system master. This is done by initializing its synchronous serial port control register (SSPCON) and synchronous serial port status register (SSPSTAT) to the bit patterns shown in Table 6 on page 17 and Table 7 on
page 17.
Figure 27. SPI Interface Connections for PIC16/PIC17 Controller
8
SCLK
PIC16/
PIC17
SCLK
6
CNVST
CNVST
AS1528/
AS1529
7
DOUT
DOUT
In SPI mode, the PIC16/PIC17 processor allow 8 bits of data to be synchronously transmitted and received simultaneously. Two consecutive 8-bit readings (see Figure 28) are necessary to obtain the entire 10-bit result from the AS1528/
AS1529. DOUT data transitions on the serial clock’s falling edge and is clocked into the processor on SCLK’s rising
edge.
The first 8-bit data stream contains the first 8 data bits starting with the MSB. The second data stream contains the
remaining bits, D3 through D0.
Figure 28. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1. CKP = 0. SMP = 0, SSPM3:SSPM0
= 0001)
Sampling Instant
1st Byte Read
CNVST
SCLK
1
DOUT
B9
MSB
2nd Byte Read
4
B8
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B7
B6
8
B5
B4
B3
B2
Revision 1.02
12
B1
B0
LSB
ZERO ZERO
16
High Z
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AS1528/AS1529
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Table 6. SSPCON Register Settings
Control Bit
AS1528/AS1529
Setting
Synchronous Serial Port Control Register (SSPCON)
WCOL
Bit 7
X
Write Collision Detection Bit
SSPOV
Bit 6
X
Receive Overflow Detect Bit
SSPEN
Bit 5
1
Synchronous Serial Port Enable
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial port
pins.
CKP
Bit 4
0
Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
SSPM3:1
Bit 3:1
0
SSPM0
Bit 0
1
Synchronous Serial Port Mode Select Bit. Sets SPI master mode and
selects FCLK = fOSC / 16.
Table 7. SSPSTAT Register Settings
Control Bit
AS1528/AS1529
Setting
Synchronous Serial Status Register (SSPSTAT)
SMP
Bit 7
0
SPI Data Input Sample Phase. Input data is sampled at the middle of the
data output time.
CKE
Bit 6
1
SPI Clock Edge Select Bit. Data is transmitted on the rising edge of the
serial clock.
D/A
Bit 5
X
Data Address Bit
P
Bit 4
X
Stop Bit
S
Bit 3
X
Start Bit
R/W
Bit 2
X
Read/Write Bit Information
UA
Bit 1
X
Update Address
BF
Bit 0
X
Buffer Full Status Bit
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AS1528/AS1529
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Layout and Grounding Considerations
The AS1528/AS1529 require proper layout and design procedures for optimum performance.
!
Use printed circuit boards; wirewrap boards should not be used.
!
Separate analog and digital traces from each other. Analog and digital traces should not run parallel to each other
(especially clock traces).
!
Digital traces should not run beneath the AS1528/AS1529.
!
Use a single-point analog ground at GND, separate from the digital ground (see Figure 29). Connect all other analog grounds and DGND to this star ground point for further noise reduction. No other digital system ground should
be connected to this single-point analog ground. The ground return to the power supply for this ground should be
low impedance and as short as possible for noise-free operation.
!
High-frequency noise in the VDD power supply may affect the AS1528/AS1529 high-speed comparator. Bypass
this supply to the single-point analog ground with 0.1µF and 4.7µF bypass capacitors (see Figure 29). The bypass
capacitors should be placed as close to the device as possible for optimum power supply noise-rejection. If the
power supply is very noisy, a 10Ω resistor can be connected as a low-pass filter to attenuate supply noise
!
Power components such as the inductor, converter IC, filter capacitors, and output diode should be placed as close
together as possible, and their traces should be kept short, direct, and wide.
!
Keep the voltage feedback network very close to the device, within 5mm (0.2”) of the pin.
!
Keep noisy traces, such as those from the pin LX, away from the voltage feedback network and guarded from
them using grounded copper traces.
Figure 29. Recommended Ground Design
+5 or +3V
Power
Supplies
+5 or +3V
GND
DGND
GND
GND
4
5Ω
(Optional)
0.1µF
+5 or +3V
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Digital
Circuitry
AS1528/
AS1529
1
VDD
Revision 1.02
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AS1528/AS1529
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
10 Package Drawings and Markings
The devices are available in a 8-pin TDFN (3x3mm) package.
Figure 30. 8-pin TDFN (3x3mm) Packagee
D2
SEE
DETAIL B
A
D
D2/2
B
aaa C 2x
E
E2
E2/2
L
PIN 1 INDEX AREA
(D/2 xE/2)
K
PIN 1 INDEX AREA
(D/2 xE/2)
aaa C
N N-1
2x
b
e
TOP VIEW
(ND-1) X e
e
BTM VIEW
Terminal Tip
ddd
bbb
C
C A B
DETAIL B
e/2
A3
ccc C
A
C
SIDE VIEW
A1
0.08 C
SEATING
PLANE
Datum A or B
EVEN TERMINAL SIDE
Symbol
A
A1
A3
L1
L2
aaa
bbb
ccc
ddd
eee
ggg
Min
0.70
0.00
Typ
0.75
0.02
0.20 REF
Max
0.80
0.05
0.15
0.13
0.15
0.10
0.10
0.05
0.08
0.10
Notes
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
Symbol
D BSC
E BSC
D2
E2
L
θ
K
b
e
N
ND
Min
1.60
1.35
0.30
0º
0.20
0.25
Typ
3.00
3.00
0.40
0.30
0.65
8
4
Max
2.50
1.75
0.50
14º
0.35
Notes
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2, 5
1, 2
1, 2, 5
Notes:
1. Figure 30 is shown for illustration only.
2. All dimensions are in millimeters; angles in degrees.
3. Dimensioning and tolerancing conform to ASME Y14.5 M-1994.
4. N is the total number of terminals.
5. The terminal #1 identifier and terminal numbering convention shall conform to JEDEC 95-1, SPP-012. Details of terminal #1 identifier are optional, but must be located within the zone indicated. The terminal #1 identifier may be either
a mold or marked feature.
6. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.
7. ND refers to the maximum number of terminals on side D.
8. Unilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals
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AS1528/AS1529
Datasheet - O r d e r i n g I n f o r m a t i o n
11 Ordering Information
The devices are available as the standard products shown in Table 8.
Table 8. Ordering Information
Ordering Code
Description
Delivery Form
Package
AS1528-BTDT
150ksps, 10-Bit, 1-Channel True-Differential ADC
Tape & Reel
8-pin TDFN (3x3mm)
AS1528-BTDR
150ksps, 10-Bit, 1-Channel True-Differential ADC
Tray
8-pin TDFN (3x3mm)
AS1529-BTDT
150ksps, 10-Bit, 2-Channel Single-Ended ADC
Tape & Reel
8-pin TDFN (3x3mm)
AS1529-BTDR
150ksps, 10-Bit, 2-Channel Single-Ended ADC
Tray
8-pin TDFN (3x3mm)
Note: All products are RoHS compliant and Pb-free.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
For further information and requests, please contact us mailto:sales@austriamicrosystems.com
or find your local distributor at http://www.austriamicrosystems.com/distributor
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AS1528/AS1529
Datasheet
Copyrights
Copyright © 1997-2009, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged,
translated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing
in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding
the information set forth herein or regarding the freedom of the described devices from patent infringement.
austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice.
Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for
current information. This product is intended for use in normal commercial applications. Applications requiring
extended temperature range, unusual environmental requirements, or high reliability applications, such as military,
medical life-support or life-sustaining equipment are specifically not recommended without additional processing by
austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show
deviations from the standard production flow, such as test flow or test location.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However,
austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to
personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or
consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the
technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters
austriamicrosystems AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
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