AS8202NF
D a ta S he e t
TTP-C2NF Communication Controller
1 General Description
40 MHz main clock with support for 10 MHz crystal,
10 MHz oscillator or 40 MHz oscillator
The AS8202NF communication controller is an
integrated device supporting serial communication
according to the TTP specification version 1.1. It
performs all communication tasks such as reception and
transmission of messages in a TTP cluster without
interaction of the host CPU. TTP provides mechanisms
that allow the deployment in high-dependability
distributed real-time systems. It provides the following
services:
16 MHz bus guardian clock with support for 16 MHz
crystal or 16 MHz oscillator
Single power supply 3.3V, 0.35µm CMOS process
Full automotive temperature range (-40ºC to 125ºC)
16k x 16 SRAM for message, status, control area
(communication network interface) and for
scheduling information (MEDL)
4k x 16 (plus parity) instruction code RAM for
protocol execution code
Predictable transmission of messages with minimal
jitter
Data sheet conforms to protocol revision 2.04
Fault-tolerant distributed clock synchronization
16k x 16 instruction code ROM containing startup
execution code and deprecated protocol code
revision 1.00
Consistent membership service with small delay
Masking of single faults
16 Bit non-multiplexed asynchronous host CPU
interface
2 Key Features
16 Bit RISC architecture
Software tools, design support, development boards
available (www.tttech.com)
Dual-channel controller for redundant data transfers
Dedicated controller supporting TTP (time-triggered
protocol class C)
Certification support package according to RTCA/
DO-254 DAL A available (www.tttech.com)
Suited for dependable distributed real-time systems
with guaranteed response time
Asynchronous data rate up to 5 Mbit/s (MFM/
Manchester)
80 pin LQFP80 Package
3 Applications
Synchronous data rate 5 to 25 Mbit/s
Bus interface (speed, encoding) for each channel
selectable independently
Application fields: automotive (by-wire braking, steering,
vehicle dynamics control, drive train control), aerospace
(aircraft electronic systems), industrial systems, railway
systems.
Figure 1. Block Diagram
D[15:0]
A[11:0]
CEB
OEB
WEB
READYB
INTB
LED[2:0]
RAM_CLK_TESTSE
USE_RAM_CLK
Receiver
Host
Processor
Interface
Communication
network
interface
(CNI)
TTP
Protocol
processor core
AS8202NF
Quartz or
Oscillator
XIN0
XOUT0
PLLOFF
RESETB
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Bus guardian
Transmitter
Instruction
memory
RAM & ROM
Revision 2.1
Test
Interface
RxD[1:0]
RXCLK[1:0]
RxDV[1:0]
RXER[1:0]
XIN1
XOUT1
TTP Bus
Media
Drivers
TxD[1:0]
CTS[1:0]
TxCLK[1:0]
RAM_CLK_TESTSE
FTEST
Test
STEST
Interface
FIDIS
TTEST
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AS8202NF TTP-C2NF
Data Sheet - A p p l i c a t i o n s
Contents
1 General Description ...............................................................................................................................1
2 Key Features ...........................................................................................................................................1
3 Applications ............................................................................................................................................1
4 Pin Assignments ....................................................................................................................................3
4.1 Pin Descriptions ................................................................................................................................................3
5 Absolute Maximum Ratings ..................................................................................................................6
6 Electrical Characteristics.......................................................................................................................7
7 Detailed Description ...............................................................................................................................9
7.1 Host CPU Interface ...........................................................................................................................................9
7.1.1 Synchronous READYB Generation.......................................................................................................12
7.2 Reset and Oscillator ........................................................................................................................................13
7.2.1
7.2.2
7.2.3
7.2.4
External Reset Signal............................................................................................................................13
Integrated Power-On Reset ..................................................................................................................13
Oscillator Circuitry .................................................................................................................................13
Build-up Characteristics ........................................................................................................................14
7.3 TTP Bus Interface ...........................................................................................................................................15
7.4 TTP Asynchronous Bus Interface....................................................................................................................15
7.5 TTP Synchronous Bus Interface .....................................................................................................................16
7.6 Test Interface ...................................................................................................................................................16
7.7 LED Signals.....................................................................................................................................................17
8 Package Drawings and Markings........................................................................................................ 18
9 Ordering Information............................................................................................................................19
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AS8202NF TTP-C2NF
Data Sheet - P i n A s s i g n m e n t s
4 Pin Assignments
VSSPLL
READYB
WEB
OEB
CEB
VSS
VDD
VSSBG
XIN1
XOUT1
VDDBG
D15
D14
D13
D12
D11
D10
D9
D8
TTEST
Figure 2. Pin Assignments LQFP80 Package
80
61
60
1
nc
XIN0
XOUT0
VDDPLL
TXD0
CTS0
TXCLK0
RXER0
RXCLK0
RXDV0
RXD0
VDD
VSS
TXD1
CTS1
TXCLK1
RXER1
RXCLK1
RXDV1
RXD1
20
VSS
VDD
D7
D6
D5
D4
D3
D2
D1
D0
VSS
VDD
A11
A10
A9
A8
A7
A6
A5
VSS
AS8202NF
TTP
Communications
Controller
(TOP VIEW)
RAM_CLK_TESTSE
STEST
PLLOFF
FTEST
FIDIS
RESETB
nc
INTB
VDD
VSS
LED0
LED1
LED2
USE_RAM_CLK
A0
A1
A2
A3
A4
nc
41
21
40
Pin Descriptions
Table 1. Pin Descriptions
Pin Name
VDDBG
Pin Number
12,29,49,59,
74
13,30,41,50,
60,75
70
VDD
VSS
Dir
Description
P
Positive Power Supply
P
Negative Power Supply
P
Positive Power Supply for Bus Guardian (connect to VDD)
VSSBG
73
P
Negative Power Supply for Bus Guardian (connect to VSS)
VDDPLL
4
P
Positive Power Supply for Main Clock PLL (connect to VDD)
VSSPLL
80
P
RAM_CLK_T
ESTSE
STEST
21
IPD
22
IPD
Negative Power Supply for Main Clock PLL (connect to VSS)
RAM_CLK when STEST=0 and USE_RAM_CLK=1, else Test Input,
connect to VSS if not used
Test Input, connect to VSS
FTEST
24
IPD
Test Input, connect to VSS
FIDIS
25
IPD
Test Input, connect to VSS
TTEST
USE_RAM_C
LK
61
IPU
Test Input, connect to VDD
34
IPD
RAM_CLK Pin Enable, connect to VSS if not used
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AS8202NF TTP-C2NF
Data Sheet - P i n A s s i g n m e n t s
Table 1. Pin Descriptions
Pin Name
Pin Number
Dir
Description
Main Clock: Analog CMOS Oscillator Input, use as input when
providing external clock
Main Clock: Analog CMOS Oscillator Output, leave open when
providing external clock
Main Clock PLL Disable Pin, connect to VSS when providing 10 MHz
crystal for enabling the internal PLL
Bus Guardian Clock: Analog CMOS Oscillator Input, use as input
when providing external clock
Bus Guardian Clock: Analog CMOS Oscillator Output, leave open
when providing external clock
Main Reset Input, active low
XIN0
2
A
XOUT0
3
A
PLLOFF
23
IPD
XIN1
72
A
XOUT1
71
A
RESETB
26
IPU
TTP Bus Channel 0: Transmit Data
TxD0
5
OPU
CTS0
6
OPD
TTP Bus Channel 0: Transmit Enable
RxD0
11
IPU
TTP Bus Channel 0: Receive Data
TxCLK0
7
IPD
TTP Bus Channel 0: Transmit Clock (MII mode)
RxER0
8
IPU
TTP Bus Channel 0: Receive Error (MII mode)
RxCLK0
9
IPD
TTP Bus Channel 0: Receive Clock (MII mode)
RxDV0
10
IPU
TTP Bus Channel 0: Receive Data Valid (MII mode)
TxD1
14
OPU
TTP Bus Channel 1: Transmit Data
CTS1
15
OPD
TTP Bus Channel 1: Transmit Enable
RxD1
20
IPU
TTP Bus Channel 1: Receive Data
TxCLK1
16
IPD
TTP Bus Channel 1: Transmit Clock (MII mode)
RXER1
17
IPU
TTP Bus Channel 1: Receive Error (MII mode)
RXCLK1
18
IPD
TTP Bus Channel 1: Receive Clock (MII mode)
RxDV1
19
IPU
TTP Bus Channel 1: Receive Data Valid (MII mode)
A[11:0]
48-42, 39-35
I
D[15:0]
CEB
69-62, 58-51
76
I/O
IPU
Host Interface (CNI) Address Bus
Host Interface (CNI) Data Bus, tristate
Host Interface (CNI) Chip Enable, active low
1
OEB
77
IPU
Host interface (CNI) output enable, active low
WEB
78
IPU
Host interface (CNI) write enable, active low
READYB
79
OPU
INTB
28
OPU
Host interface (CNI) transfer finish signal, active low, open drain
Host interface (CNI) time signal (interrupt), active low, open drain
LED[2:0]
nc
33-31
1, 27, 40
OPD
2
Configurable generic output port
Not connected, leave open
1. The device is addressed at 16-bit data word boundaries. If the device is connected to a CPU with a bytegranular address bus, remember that A[11:0] of the AS8202NF device has to be connected to A[12:1] of the
CPU (considering a little endian CPU address bus)
2. At de-assertion READYB is driven to the inactive value (high) for a configurable time.
Table 2. Pin Directions
Dir
Description
I
TTL Input
IPU
TTL Input with Internal Weak Pull-Up
IPD
TTL Input with Internal Weak Pull-Down
I/O
TTL Input/Output with Tristate
OPU
TTL Output with Internal Weak Pull-Up at Tristate
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AS8202NF TTP-C2NF
Data Sheet - P i n A s s i g n m e n t s
Table 2. Pin Directions
Dir
Description
OPD
TTL Output with Internal Weak Pull-Down at Tristate
A
Analog CMOS Pin
P
Power Pin
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Data Sheet - A b s o l u t e M a x i m u m
Ratings
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions beyond those indicated in Section 6 Electrical
Characteristics on page 7 is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Table 3. Absolute Maximum Ratings
Parameter
Min
Max
Units
DC Supply Voltage (VDD)
-0.3
5.0
V
Input Voltage (VIN)
-0.3
VDD+0.3
V
any pin
Input Current (lIN)
-100
100
mA
any pin, TAMB=25ºC
Storage Temperature (TSTRG)
-55
150
ºC
Soldering Temperature (TSOLD)
235
ºC
Package body temperature (Tbody)
240
ºC
85
%
Humidity (H)
5
Electrostatic Discharge (ESD)
1000
V
Notes
t=10 sec, Reflow and Wave
1
HBM: 1KV Mil.std.883, Method 3015.7
1. The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD020C “Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”. The lead
finish for packages is (85%/15% Sn/Pb).
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Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
TAMB = -40 to +125 ºC, VDD = 3V to +3.6V, VSS = 0V unless otherwise specified.
Table 4. Electrical Characteristics
Symbol
Parameter
Conditions
Min
IDDs
Static Supply Current
all inputs tied to VDD/VSS,
clocks stopped, exclusive of
I/O drive requirements,
VDD=3.6V
5
IDD
Operating Supply Current
CLK0_EXT_PLL
Clock Period of Main Clock
Typ
Max
Units
900
µA
100
mA
Operating Conditions
(external)
CLK0_EXT
CLK1
1
VDD=3.3V, PLL active,
exclusive of I/O drive
requirements
2
PLL active
100
ns
PLL inactive
25
ns
62.5
ns
1
Clock Period of Bus
Guardian Clock
1
TTL Input Pins and TTL Bidirectional Pins in Input/Tristate Model
VIL
Input Low Voltage
VIH
Input High Voltage
IINleak
Input Leakage Current
IIL
IIH
CIN
Input Low Current
Input High Current
0.8
2.0
Pins without pad resistors,
VDD=3.6V
V
V
-1
1
µA
3
Pins with pulldown resistors
VDD=3.0V
VIN=0.4V
4.9
VIN=0.8V
8.8
Pins with pull-up
resistors
VDD=3.6V
VIN=0V
-15
-75
Pins with pulldown resistors
VDD=3.6V
VIN=3.6V
15
75
Pins with pull-up
resistors
VDD=3.0V
VIN=2.0V
-10.7
VIN=2.5V
-6
3
µA
µA
3
3
4
Input Capacitance
pF
4.5
RxD Pin
tASYM_Rx
t(VIN=0.5*VDD)
Asymmetric Receiver
Delay RxD
T = 125 ºC,
VDD=3.0V,
CLOAD=35pF
RxD[1,0]
4
4
-2
2
ns
2.5
pF
±1
4
µA
CMOS Inputs (XIN), drive from external clock generator
Drive at XIN (XOUT = open)
CXIN
Input Capacitance
IXIN
Input Current
VIL_XIN
Input Low Voltage
0
0.3*
VDD
V
VIH_XIN
Input High Voltage
0.7*
VDD
VDD
V
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Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 4. Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
mA
Outputs and TTL Bidirectional Pins in Output Mode
IOL
Output Low Current
VDD=3.0V, Vo = 0.4V
-4
IOH
Output High Current
VDD=3.0V, Vo = 2.5V
4
IOZ
tRISE
t(VOUT=0.1*VDD) to
t(VOUT=0.9*VDD)
tFALL
t(VOUT=0.9*VDD) to
t(VOUT=0.1*VDD)
Output Tristate Current
Transition Time – Rise
Transition Time – Fall
VDD=3.6V
T = 125 ºC,
VDD=3.0V,
CLOAD=35pF
T = 125 ºC,
VDD=3.0V,
CLOAD=35pF
mA
4
±10
CTS[1,0],
LED[2:0],
INTB
8.1
D[15:0],
READYB
8.9
CTS[1,0],
LED[2:0],
INTB
6
µA
3
ns
3
3
ns
D[15:0],
READYB
7
3
TxD Pins
tRISE
t(VOUT=0.3*VDD) to Transition Time – Rise TxD
t(VOUT=0.7*VDD)
T = 125 ºC,
VDD=3.0V,
CLOAD=35pF
TxD[1,0]
4.5
tFALL
t(VOUT=0.7*VDD) to
t(VOUT=0.3*VDD)
Transition Time – Fall TxD
T = 125 ºC,
VDD=3.0V,
CLOAD=35pF
TxD[1,0]
3
tASYM_Rx
t(VOUT=0.5*VDD)
Asymmetric Driver Delay
TxD
T = 125 ºC,
VDD=3.0V,
CLOAD=35pF
TxD[1,0]
1.
2.
3.
4.
4
-3
4
ns
4
ns
4
ns
3
Typical values: CLK0=40 MHz, CLK1=16 MHz
Using the internal PLL multiplies the main clock frequency by 4
Implicitly tested.
Guaranteed by design; not tested during production
Note: If Min/Max values are both negative, they are ordered according to their absolute value.
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AS8202NF TTP-C2NF
Data Sheet - D e t a i l e d D e s c r i p t i o n
7 Detailed Description
The AS8202NF is the first TTP controller to support both MFM and Manchester coding. Manchester coding is
important for DC-free data transmission, which allows the use of transformers in the data stream. The AS8202NF is
pin-compatible with its predecessor, the AS8202. The AS8202NF provides support for fault-tolerant, high-speed bus
systems in a single device. The communication controller is qualified for the full temperature range required for
automotive applications and is certifiable according to RTCA standards. It offers superior reliability and supports data
transfer rates of 25 Mbit/s with MII and up to 5 Mbit/s with MFM/Manchester.
The CNI (communication network interface) forms a temporal firewall. It decouples the controller network from the host
subsystem by use of a dual ported RAM (CNI). This prevents the propagation of control errors. The interface to the
host CPU is implemented as a 16-bit wide non-multiplexed asynchronous bus interface.
The TTP follows a conflict-free media access strategy called time division multiple access (TDMA). This means, TTP
deploys a time slot technique based on a global time that is permanently synchronized. Each node is assigned a time
slot in which it is allowed to perform transmit operation. The sequence of time slots is called TDMA round, a set of
TDMA rounds forms a cluster cycle. The operation of the network is repeated after one cluster cycle. The sequence of
interactions forming the cluster cycle is defined in a static time schedule, called message descriptor list (MEDL). The
definition of the MEDL in conjunction with the global time determines the response time for a service request.
The membership of all nodes in the network is evaluated by the communications controller. This information is
presented to all correct cluster members in a consistent fashion. During operation, the status of all other nodes is
propagated within one TDMA round. Please read more about TTP and request the TTP specification at
www.tttech.com.
Host CPU Interface
The host CPU interface, also referred to as CNI (Communication Network Interface), connects the application circuitry
to the AS8202NF TTP controller. All related signal pins provide an asynchronous read/write access to a dual ported
RAM located in the AS8202NF. There are no setup/hold constraints referring to the microtick (main clock “CLK0”).
All accesses have to be executed on a granularity of 16 bit (2 byte), the device does not support byte-wide accesses.
The pin A0 (LSB) of the device differentiates even and odd 16 bit word addresses and is typically connected to A1 of a
little-endian host CPU. The A0 of host CPU is not connected to the device, and the application/driver on the host CPU
should force all accesses to be 16 bit. For efficiency reasons, the host CPU application/driver may access some
memory locations of the AS8202NF using wider accesses (e.g. 32 bit), and the bus interface of the host CPU will
automatically split the access into two consecutive 16-bit wide accesses to the TTP controller. Note that particularly in
such a setup all timing parameters of the host CPU interface must be met, especially the inactivity timeouts described
as symbols 16–19.
The host interface features an interrupt or time signal INTB to notify the application circuitry of programmed and
protocol-specific, synchronous and asynchronous events.
The host CPU interface allows access to the internal instruction code memory. This is required for proper loading of the
protocol execution code into the internal instruction code RAM, for extensive testing of the instruction code RAM and
for verifying the instruction code ROM contents.
INTB is an open-drain output, i.e. the output is only driven to '0' and is weak-pull-up at any other time, so external pullup resistors or transistors may be necessary depending on the application.
READYB is also an open-drain output, but with a possibility to be driven to ‘1’ for a defined time (selectable by register)
before weak-pull-up at any other time.
The LED port is software-configurable to automatically show some protocol-related states and events, see below for
the LED port configuration.
Table 5. Host Interface Ports
Pin Name
Mode
Width
Comment
A[11:0]
in
12
CNI address bus, 12 bit (A0 is LSB)
D[15:0]
inout (tri)
16
CNI data bus, 16 bit (D0 is LSB)
CEB
in
1
CNI chip enable, active low
WEB
in
1
CNI write enable, active low
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AS8202NF TTP-C2NF
Data Sheet - D e t a i l e d D e s c r i p t i o n
Table 5. Host Interface Ports
Pin Name
Mode
Width
Comment
OEB
In
1
CNI output enable, active low
READYB
out (open drain)
1
CNI ready, active low
INTB
out (open drain)
1
CNI interrupt, time signal, active low
RAM_CLK_TESTSE
in
1
HOST clock
USE_RAM_CLK
in
1
HOST clock pin enable
Asynchronous READYB permits the shortest possible bus cycle but eventually requires signal synchronization in the
application. Connect USE_RAM_CLK to VSS to enable this mode of operation.
Synchronous READYB uses an external clock (usually the host processor’s bus clock) for synchronization of the
signal, eliminating external synchronization logic. Connect USE_RAM_CLK to VDD and RAM_CLK_TESTSE to the
host processor's bus clock to enable this mode of operation.
Note: Due to possible metastability occurrence, it is not recommended to be used in safety critical systems.
Table 6. Asynchronous DPRAM interface
Symbol
Parameter
Tc
Controller Cycle Time
1a
Input Valid to CEB, WEB
(Setup Time)
2a
1b
Conditions
Min
Typ
Max
25
A[11:0]
D[15:0]
Units
ns
5
ns
A[11:0]
3
2b
CEB, WEB to Input Invalid
(Hold Time)
D[15:0]
4
3
Input Rising to CEB, WEB
Falling
CEB, WEB, OEB
5
4
CEB, WEB Rising to Input
Falling
CEB, WEB, OEB
5
Write Access Time (CEB,
WEB to READYB)
min = 1 Tc, max = 4 Tc
6
CEB, WEB de-asserted to
READYB de-asserted
7a
Input Valid to CEB, OEB
(Setup Time)
A[11:0]
5
ns
7b
CEB, OEB to Input Invalid
(Hold Time)
A[11:0]
2
ns
8
Input Rising to CEB, OEB
Falling
CEB, WEB, OEB
5
1
ns
9
CEB, OEB Rising to Input
Falling
CEB, WEB, OEB
5
1
ns
10
Read Access Time (CEB,
OEB to READYB)
min = 1.5 Tc, max = 8 Tc
37.5
200
ns
11a
CEB, OEB asserted to
signal asserted
D[15:0]
4.0
8.4
ns
11b
D[15:0]
3.8
8
11c
CEB, OEB de-asserted to
signal de-asserted
12
READYB, D skew
13
RAM_CLK_TESTSE
Rising to READYB Falling
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1
ns
1,2
ns
5
25
READYB
USE_RAM_CLK=1
Revision 2.1
ns
100
ns
9.4
ns
8.8
3.7
ns
±2
ns
13.5
ns
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AS8202NF TTP-C2NF
Data Sheet - D e t a i l e d D e s c r i p t i o n
Table 6. Asynchronous DPRAM interface
Symbol
Parameter
Conditions
Min
14
RAM_CLK_TESTSE
Rising to READYB Rising
USE_RAM_CLK=1
RAM_CLK_TESTSE
Rising to READYB
Deactivated 1->Z
15
USE_RAM_CLK
=1
Typ
Max
Units
3
9.7
ns
Ready
delay='00'
3.6
12.9
Ready
delay=01
4.5
15.4
Ready
delay=10
5.4
18.8
Ready
delay=11
6.4
22.2
ns
16
Read to Read Access
Inactivity Time (CEB, OEB
low to CEB, OEB low)
17
Read to Write Access
Inactivity Time (CEB, OEB
low to CEB, WEB low)
18
Write to Write Access
Inactivity Time (CEB, WEB
low to CEB, WEB low)
5
19
Write to Read Access
Inactivity Time (CEB, WEB
low to CEB, OEB low)
5
1
min = 1.5 Tc
ns
37.5
1
ns
1,2
ns
1,2
ns
5
1. Prior to starting a read or write access, CEB, WEB and OEB have to be stable for at least 5 ns (see symbol 3, 4,
8, 9). In addition the designer has to consider the minimum inactivity time according to symbols 16, 17, 18, 19.
For more information on the inactivity times (see Figure 3).
2. To allow proper internal initialization, after finishing any write access (CEB or WEB is high) to the internal
CONTROLLER_ON register, CEB OEB and WEB have to be stable high within 200 ns (min = 8 Tc).
Note: All values not tested during production, guaranteed by design.
Figure 3. Read/Write Access Inactivity Time
Read
16
Read
17
Write
18
Write
19
Read
CEB
OEB
WEB
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AS8202NF TTP-C2NF
Data Sheet - D e t a i l e d D e s c r i p t i o n
Figure 4. Write Access Timing (CEB Controlled)
1a
A
1a
A
Valid
Valid
WEB
WEB
2a
D
2a
2b
D
Valid
3
4
5
2b
Valid
3
OEB
4
5
6
6
READYB
READYB
Figure 6. Read Access Timing (CEB Controlled)
7a
A
1b
CEB
CEB
OEB
Figure 5. Write Access Timing (WEB Controlled)
1b
Figure 7. Read Access Timing (OEB Controlled)
7b
7a
A
Valid
CEB
7b
Valid
CEB
WEB
WEB
11a
12
Invalid
D
11a
11b
11b
12
Valid
8
Invalid
D
9
Valid
8
9
OEB
OEB
10
10
11c
READYB
11c
READYB
Synchronous READYB Generation
Figure 8. Synchronous READYB Timing
asynchronous READYB
RAM_CLK_TESTSE
15
synchronous READYB
13
14
Synchronous READYB is aligned to host clock (with pulse duration of one host clock cycle) to fulfill the required host
timing constraints for input setup and input hold time to/after host clock rising edge.
Note: Connect USE_RAM_CLK to VDD and RAM_CLK_TESTSE to the host processor's bus clock to enable this
mode of operation. Due to possible metastability occurrence, it is not recommended to be used in safety critical
systems.
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Data Sheet - D e ta i l e d D e s c r i p t i o n
Reset and Oscillator
Table 7. Pin mode
Pin Name
Mode
Comment
XIN0
analog
main oscillator input (external clock input)
XOUT0
analog
main oscillator output
XIN1
analog
bus guardian oscillator input (external clock input)
XOUT1
analog
bus guardian oscillator output
PLLOFF
in
PLL disable
RESETB
in
external reset
External Reset Signal
To issue a reset of the chip the RESETB port has to be driven low for at least 1 us. Pulses under 50 ns duration are
discarded. At power-up the reset must overlap the build-up time of the power supply.
Integrated Power-On Reset
The Device has an internal Power-On Reset generator. When supply voltage ramps up, the internal reset signal is kept
active (low) for 33 µs typical.
Table 8. Parameters
Symbol
Parameter
Min
Typ
Max
Unit
dV/dt
supply voltage slope
551
-
-
V/ms
tpores
power on reset active time after VDD > 1,0V
25
33
49
µs
Note: In case of non-compliance keep the external reset (RESETB) active for min. 5 ms after supply voltage is valid
and oscillator inputs active.
Oscillator Circuitry
The internal oscillators for main and bus guardian clock require external quartzes or external oscillators. The main
clock features a PLL multiplying a 10 MHz XIN0/XOUT0 oscillation to an internal frequency of 40 MHz when enabled.
Figure 9. Main clock setup
Enabled PLL, external quartz
Cext
10 M Hz
Disabled PLL, external oscillator
40 MHz
square
wave
10 MHz
square
wave
VDD
VSS
XOUT0
XIN0
PLLOFF
XOUT0
XIN0
XOUT0
XIN0
VSS
PLLOFF
Rd
Rf
PLLOFF
Cext
Enabled PLL, external oscillator
Rf will normally not be soldered, it is only provided to get maximum flexibility.
Cext, typ = 15/18 pF. Rd has to be calculated, if the measured drive level will be too high; if drive level is ok, Rd = 0.
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Data Sheet - D e ta i l e d D e s c r i p t i o n
If using an external oscillator at 10 MHz with enabled internal PLL, the oscillator must have a period of 100 ns with low
jitter. Note that a crystal-based clock is recommended over a derived clock (i.e., PLL-based) to allow best internal PLL
performance.
Table 9. Parameters
Parameter
Condition
Min
R_osc10
Oscillation margin @ 10 MHz, CLOAD = 18 pF
0.95
R_osc16
Oscillation margin @ 16 MHz, CLOAD = 18 pF
0.37
R_osc20
Oscillation margin @ 20 MHz, CLOAD = 18 pF
0.24
Typ
1
1.62
1
0.64
1
0.41
Max
Unit
1
kΩ
1
kΩ
1
kΩ
1. Not tested during production.
Note: CLOAD is the value of the external load capacitors towards ground. The total load capacitance seen by the
quartz will be CLOAD_tot = (CLOAD + Cpar)/2. Cpar is the equivalent parasitic capacitance of the oscillator cell
inputs and the PCB and is derived from measurements to be about 3.5 … 4.0 pF.
Figure 10. Bus Guardian clock setup
External quartz
16 M H z
s q u a re
w ave
C ext
XIN1
16 M H z
Rd
XIN1
XOUT1
Rf
XOUT1
C ext
External oscillator
Both the XIN0/XOUT0 (main clock) and the XIN1/XOUT1 (bus guardian clock) cells support driving a quartz crystal
oscillation as well as clock input by an external oscillator.
Build-up Characteristics
Table 10. Characteristics
Symbol
Pin
Parameter
Tosc_startup0
XIN0/
XOUT0
Tosc_startup1
Tpll_startup0
Max
Unit
Note
Oscillator startup time
(Main clock)
20
ms
Quartz frequency:
10 MHz
XIN1/
XOUT1
Oscillator startup time
(Bus Guardian clock)
20 ms
ms
Quartz frequency:
16 MHz
XIN0/
XOUT0
PLL startup time
(Main clock)
20 ms
ms
Quartz frequency:
10 MHz
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Min
Typ
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AS8202NF TTP-C2NF
Data Sheet - D e ta i l e d D e s c r i p t i o n
TTP Bus Interface
The AS8202NF contains two TTP bus units, one for each TTP channel, building the TTP bus interface. Each TTP bus
channel contains a transmitter and a receiver and can be configured to be either in the asynchronous or synchronous
mode of operation. Note that the two channels (channel 0 and channel 1) can be configured independently for either of
these modes.
The drivers of the TxD and CTS pins are actively driven only during a transmission window, all the other time the
drivers are switched off and the weak pull resistors are active. External pull resistors must be used to define the signal
levels during idle phases.
Note: The transmission window may be different for each channel.
Table 11. Bus Interface Connections
Pin Name
Tx inactive
TxD[0]
weak pull-up
CTS[0]
weak pull-down
TxD[1]
weak pull-up
CTS[1]
weak pull-down
TTP Asynchronous Bus Interface
When in asynchronous mode of operation the channel's bus unit uses a self-clocking transmission encoding which can
be either MFM or Manchester at a maximum data rate of 5 Mbit/s on a shared media (physical bus). The pins can
either be connected to drivers using recessive/dominant states on the wire as well as drivers using active push/pull
functionality.
The RxD signal uses '1' as the inactivity level. In the so-called RS485 compatible mode longer periods of '0' are treated
as inactivity. If the RS485 compatible mode is not used, the application must care to drive RxD to '1' during inactivity on
the bus.
Table 12. Asynchronous Bus Interface Connections
Pin Name
Mode
Connect to PHY
Note
TxD[0]
out
TxD
Transmit data channel 0
CTS[0]
out
CTS
Transmit enable channel 0
TxCLK[0]
in
No function (do not connect)
RXER[0]
in
No function (do not connect)
RXCLK[0]
in
No function (do not connect)
RxDV[0]
in
No function (do not connect)
RxD[0]
in
RxD
Receive data channel 0
TxD[1]
out
TxD
Transmit data channel 1
CTS[1]
out
CTS
Transmit enable channel 1
TxCLK[1]
in
No function (do not connect)
RXER[1]
in
No function (do not connect)
RXCLK[1]
in
No function (do not connect)
RxDV[1]
in
No function (do not connect)
RxD[1]
in
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RxD
Receive data channel 1
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AS8202NF TTP-C2NF
Data Sheet - D e ta i l e d D e s c r i p t i o n
TTP Synchronous Bus Interface
When in synchronous mode of operation, the bus unit uses a synchronous transfer method to transfer data at a rate
between 5 and 25 Mbit/s. The interface is designed to run at 25 Mbit/s and to be gluelessly compatible with the
commercial 100 Mbit/s Ethernet MII (Media Independent Interface) according to IEEE standard 802.3 (Ethernet CSMA/
CD).
Connecting the synchronous TTP bus unit to a 100 Mbit/s Ethernet PHY is done by connecting TxD, CTS, TxCLK,
RXER, RXCLK, RxDV and RxD of any channel to TxD0TxD0, TxEN, TxCLK, RXER, RXCLK, RxDV and RxD0 of the
PHY's MII. The pins TxD1, TxD2 and TxD3 of the PHY's MII should be linked to VSS. The signals RxD1, RxD2, RxD3,
COL and CRS as well as the MMII (Management Interface) should be left open or can be used for diagnostic purposes
by the application.
Note that the frames sent by the AS8202NF are not Ethernet compatible and that an Ethernet Hub (not a Switch) can
be used as a 'star coupler' for proper operation. Also note that the Ethernet PHY must be configured for Full Duplex
operation (even though the Hub does not support full duplex), because TTP has its own collision management that
should not interfere with the PHY's Half-Duplex collision management. In general, the PHY must not be configured for
automatic configuration ('Auto negotiation') but be hard-configured for 100 Mbit/s, Full Duplex operation.
Note: To run the interface at a rate other than 25 Mbit/s other transceiver PHY components have to be used.
Table 13. Synchronous Bus Interface Connections
Pin Name
Mode
Connect to PHY
Note
TxD[0]
out
TxD0TxD0
Transmit data channel 0
CTS[0]
out
TxEN
Transmit enable channel 0
TxCLK[0]
in
TxCLK
Transmit clock channel 0
RXER[0]
in
RXER
Receive error channel 0
RXCLK[0]
in
RXCLK
Receive clock channel 0
RxDV[0]
in
RxDV
Receive data valid channel 0
RxD[0]
in
RxD0
Receive data channel 0
TxD[1]
out
TxD0
Transmit data channel 1
CTS[1]
out
TxEN
Transmit enable channel 1
TxCLK[1]
in
TxCLK
Transmit clock channel 1
RXER[1]
in
RXER
Receive error channel 1
RXCLK[1]
in
RXCLK
Receive clock channel 1
RxDV[1]
in
RxDV
Receive data valid channel 1
RxD[1]
in
RxD0
Receive data channel 1
Test Interface
The Test Interface supports the manufacturing test and characterization of the chip. In the application environment test
pins have to be connected as following:
STEST, FTEST, FIDIS: connect to VSS
TTEST: connect to VDD
Warning: Any other connection of these pins may cause permanent damage to the device and to additional devices
of the application.
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Data Sheet - D e ta i l e d D e s c r i p t i o n
LED Signals
The LED port consists of three pins. Via the MEDL each of these pins can be independently configured for any of the
three modes of operation. At Power-Up and after Reset the LED port is inactive and only weak pull-down resistors are
connected. After the controller is switched on by the host and when it is processing its initialization, the LED port is
initialized to the selected mode of operation.
Table 14. LED Signals
Pin Name
Protocol Mode
LED2
RPV or
Protocol activity7
LED1
Sync Valid
LED0
Protocol activity or RPV
Timing Mode
1
6
2
Time Overflow
4
Time Tick
7
Microtick
2
8
Bus Guardian Mode
3
Action Time
5
BDE1
5
BDE0
1. RPV is Remote Pin Voting. RPV is a network-wide agreed signal used typically for agreed power-up or powerdown of the application's external drivers.
2. Time Overflow is active for one clock cycle at the event of an overflow of the internal 16-bit time counter. Time
Tick is active for one clock cycle when the internal time is counted up. Time Overflow and Time Tick can be used
to externally clone the internal time control unit (TCU). With this information the application can precisely sample
and trigger events, for example.
3. Action Time signals the start of a bus access cycle.
4. The controller sets this output when cluster synchronization is achieved (after integration from the LISTEN state,
after acknowledge in the COLDSTART state).
5. BDE0 and BDE1 show the Bus Guardian's activity, '1' signals an activated transmitter gate on the respective
channel.
6. Protocol activity is typically connected to an optical LED. The flashing frequency and rhythm give a simple view
to the internal TTP protocol state.
7. LED2's RPV mode and LED0's Protocol activity mode can be swapped with a MEDL parameter.
8. Microtick is the internal main clock signal.
Each LED pin can be configured to be either a push/pull driver (drives both LOW and HIGH) or to be only an opendrain output (drives only LOW).
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AS8202NF TTP-C2NF
Data Sheet - P a c k a g e D r a w i n g s
and Markings
8 Package Drawings and Markings
The product is available in LQFP80 package.
Figure 11. package Diagram
Table 15. package Dimensions
Symbol
Min
D
15.8
D1
13.9
E
15.8
E1
13.9
b
0.22
b1
0.22
c
0.09
Typ
16
14
16
14
0.32
0.3
Max
16.2
14.1
16.2
14.1
0.38
0.33
0.2
Symbol
c1
e
ccc
ddd
N
N/2
N/4
Min
0.09
Typ
Max
0.16
0.65
0.10
0.13
80
40
20
Note:
1. All dimensions are in millimeters, angle is in degrees.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. D1 and E1
are maximum plastic body size dimensions including mold mismatch.
3. Dimensioning and tolerancing conform to JEDEC MS-026 Rev A.
4. The top package body size may be smaller than the bottom body size by as much as 0.15 mm.
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Data Sheet - O r d e r i n g I n f o r m a t i o n
9 Ordering Information
Table 16. Ordering Information
Type
AS8202NF-ALQR
AS8202NF-ALQT
AS8202NF-ALQU
Marking
AS8202NF
Description
TTP communication controller
Delivery Form
Tray
Package
LQFP80
AS8202NF
TTP communication controller
Tape&Reel
LQFP80
AS8202NF
TTP communication controller
Tube
LQFP80
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Data Sheet - O r d e r i n g I n f o r m a t i o n
Copyrights
Copyright © 1997-2009, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged,
translated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing
in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding
the information set forth herein or regarding the freedom of the described devices from patent infringement.
austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice.
Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for
current information. This product is intended for use in normal commercial applications. Applications requiring
extended temperature range, unusual environmental requirements, or high reliability applications, such as military,
medical life-support or life-sustaining equipment are specifically not recommended without additional processing by
austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show
deviations from the standard production flow, such as test flow or test location.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However,
austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to
personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or
consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the
technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters
austriamicrosystems AG
A-8141 Schloss Premstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com/contact
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