APA2036 Stereo 2.6W Audio Power Amplifier Features • • • • • • • • • • General Description Operating Voltage: 3.0 ~ 5.5V The APA2036 is a stereo audio power amplifier in a Low Shutdown Current – IDD= 0.5µA (typical) at VDD= 5V TQFN4x4-16 package. To simplify the audio system design in notebook computer applications, the APA2036 combines a stereo bridge-tied mode for speaker drive and a stereo single-end mode for headphone drive into a Selectable Bridge-Tied Load (BTL) or SingledEnded (SE) Operation single chip, where both modes are easily switched by the SE/BTL input control pin signal. When the APA2036 is in Output Power (BTL) at 1% THD+N, VDD= 5V – 2.4W at RL = 3Ω – 2.0W at RL = 4Ω – 1.3W at RL = 8Ω the BTL mode with 5V supply voltage, it is capable of delivering 2.4W/2.0W/1.3W of continuous output power per channel into 3Ω/4Ω/8Ω load (Speaker) with less than 1% THD+N respectively. When the APA2036 operates in Output Power (SE) at 1% THD+N, VDD= 5V – 160mW at RL = 16Ω – 85mW at RL = 32Ω the single-ended mode, it is capable of delivering 160mW/ 85mW of continuous output power per channel into 16Ω/ Depop Circuitry Integrated 32Ω load (Headphone). Thermal and Over-Current Protections The APA2036 also serves low-voltage applications well. Short Circuit Protection The APA2036, with 3.3V supply voltage, provides 900mW Space Saving Packaging – 4mmx4mm 16-Lead Thin QFN Package (TQFN4X4-16) (at 1% THD+N) per channel into 4Ω load. Both of the depop circuitry and the thermal shutdown protection cir- Lead Free Available (RoHS Compliant) reduces pops and clicks noise during power on/off and enable/shutdown processes. The thermal protection pro- cuitry are integrated in the APA2036. The depop function Applications • • • tects the chip from being destroyed by over-temperature failure. For power sensitive applications, the APA2036 also Handsets features a shutdown function which reduces the supply current only 0.5µA (typical). Portable multimedia devices Notebooks THD+N vs. Output Power 10 Simplified Application Circuit 1 LOUTP LINN THD+N (%) L-CH Input VDD=5V RL=4Ω Ci=1µF BW<80KHz BTL mode LBYPASS LOUTN SE-BTL Signal APA2036 R-CH Input RINN Fin=20KHz Fin=20Hz 0.1 ROUTP Fin=1KHz RBYPASS ROUTN 0.01 10m 100m 1 2 4 Output Power (W) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 1 www.anpec.com.tw APA2036 Ordering and Marking Information Package Code QB : TQFN4x4-16 Operating Ambient Temperature Range I : - 40 to 85 ° C Handling Code TR : Tape & Reel Lead Free Code L : Lead Free Device APA2036 Lead Free Code Handling Code Temperature Range Package Code APA2036 QB : XXXXX - Date Code APA2036 XXXXX Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldering operations. ANPEC lead-free products meet or exceed the leadfree requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature. 9 GND 10 LBYPASS 11 GND 12 RBYPASS Pin Configuration RINN 13 8 LINN ROUTP 14 APA2036 TOP VIEW TQFN4x4-16 VDD 15 ROUTN 16 GND 4 SHUTDOWN 3 SE/BTL 2 GND 1 Symbol TA TJ TSTG TSDR PD =Thermal Pad (connected the Thermal Pad to GND plane for better heat dissipation) 6 VDD 5 LOUTN Absolute Maximum Ratings VDD 7 LOUTP (Note 1) Parameter Rating Unit -0.3 to 6 V Input Voltage (SE/BTL, SHUTDOWN, RINN, LINN, RBYPASS, LBYPASS) -0.3 to VDD+0.3 V Output Voltage (ROUTP, ROUTN, LOUTP, LOUTN) -0.3 to VDD+0.3 Supply Voltage Operating Ambient Temperature Range -40 to 85 Maximum Junction Temperature 150 Storage Temperature Range -65 to +150 Maximum Lead Soldering Temperature, 10 seconds Power Dissipation 260 Internally Limited V ο ο ο ο C C C C W Note 1：Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 2 www.anpec.com.tw APA2036 Thermal Characteristics (Note 2,3) Symbol θJA θJC Parameter Thermal Resistance - Junction to Ambient Junction-to-Case Resistance in free air Value (Note 2) Unit 41 (Note 3) o C/W 9 Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The thermal pad of TQFN4x4-16 is soldered directly on the PCB. Note 3: The case temperature is measured at the center of the thermal pad on the underside of the TQFN4x4-16 package. Recommended Operating Conditions Symbol VDD Parameter Range Supply Voltage VIH High level threshold voltage VIL Low level threshold voltage Unit 3.0 ~ 5.5 V SHUTDOWN 0.4 VDD ~ VDD V SE/BTL 0.8 VDD ~ VDD V SHUTDOWN SE/BTL 0 ~ 1.0 V 0 ~ 0.6VDD V VIC Common mode input voltage ~ VDD-0.5 TA Ambient Temperature Range -40 ~ 85 o V -40 ~ 125 o C TJ Junction Temperature Range RL Speaker Resistance 3~ Ω C RL Headphone Resistance 16 ~ Ω Electrical Characteristics Unless otherwise noted, these specifications apply over VDD=5V, VGND=0V, TA= -40 ~ 85OC, Typical values are at TA= 25OC Symbol Parameter VDD Supply Voltage IDD Supply Current Test Condition APA2036 Min. Typ. 3 Max. 5.5 VSE/BTL=0V 5.5 13.5 VSE/BTL=5V 3 7.5 5 Unit V mA ISD Shutdown Current VSHUTDOWN=5V 0.5 TSTART-UP Start-Up time from shutdown CB=2.2µF 700 µA ms BTL mode, VDD=5V THD+N=1%, Fin=1KHz PO THD+N=10%, Fin=1KHz THD+N Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 2.4 RL=4Ω 2.0 RL=8Ω Output Power Total Harmonic Distortion Pulse Noise RL=3Ω Fin=1KHz 3 1.1 1.3 W RL=3Ω 3.0 RL=4Ω 2.6 RL=8Ω 1.6 RL=4Ω PO=1.3W 0.06 RL=8Ω PO=0.9W 0.03 % www.anpec.com.tw APA2036 Electrical Characteristics (Cont.) Unless otherwise noted, these specifications apply over VDD=5V, VGND=0V, TA= -40 ~ 85OC, Typical values are at TA=25OC Symbol Parameter Test Condition APA2036 Min. Typ. Max. Unit Power Supply Rejection Ratio RL=8Ω, Fin=217Hz 61 dB Output Offset Voltage VIN=0V 10 mV Channel separation RL=8Ω, PO=0.9W, Fin=1KHz 100 dB S/N Signal to Noise Ratio RL=8Ω, PO=1.1W, A_weighting 93 dB Vn Noise Output Voltage RL=8Ω 22 µV(rms) PSRR VOS Crosstalk SE mode, VDD=5V 160 RL=16Ω THD+N=1%, Fin=1KHz RL=32Ω PO 70 85 Output Power mW THD+N=10%, Fin=1KHz RL=16Ω 210 RL=32Ω 110 RL=32Ω PO=60mW 0.02 % THD+N Total Harmonic Distortion Pulse Noise Fin=1KHz PSRR Power Supply Rejection Ratio RL=32Ω, Fin=217Hz 60 dB Output Offset Voltage VIN=0V 10 mV Channel separation RL=32Ω, PO=60mW, Fin=1KHz 85 dB S/N Signal to Noise Ratio RL=32Ω, PO=65mW, A_weighting 100 dB Vn Noise Output Voltage RL=32Ω 8 µV(rms) VOS Crosstalk Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 4 www.anpec.com.tw APA2036 Typical Operating Characteristics THD+N vs. Output Power THD+N vs. Output Power 10 10 VDD=5V RL=4Ω Ci=1µF BW<80KHz BTL mode 1 THD+N (%) 1 THD+N (%) VDD=5V RL=8Ω Ci=1µF BW<80KHz BTL mode Fin=20KHz Fin=20Hz 0.1 Fin=20KHz Fin=20Hz 0.1 Fin=1KHz 0.01 10m 100m 1 Fin=1KHz 2 0.01 10m 4 100m THD+N (%) THD+N (%) 1 Fin=20Hz Fin=20KHz 0.1 VDD=5V RL=32Ω Ci=1µF CC=1000µF BW<80KHz SE mode Fin=20Hz 0.1 Fin=20KHz Fin=1KHz Fin=1KHz 100m 0.01 10m 300m 10 VDD=3.3V RL=4Ω Ci=1µF BW<80KHz BTL mode 1 VDD=3.3V RL=8Ω Ci=1µF BW<80KHz BTL mode 1 THD+N (%) Fin=20KHz Fin=20Hz 0.1 Fin=20KHz 0.1 Fin=20Hz Fin=1KHz 0.01 10m 200m THD+N vs. Output Power THD+N vs. Output Power THD+N (%) 100m Output Power (W) Output Power (W) 10 3 10 VDD=5V RL=16Ω Ci=1µF Cc=1000µF BW<80KHz SE mode 0.01 10m 2 THD+N vs. Output Power THD+N vs. Output Power 10 1 1 Output Power (W) Output Power (W) 100m Fin=1KHz 1 0.01 10m 2 Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 100m 1 Output Power (W) Output Power (W) 5 www.anpec.com.tw APA2036 Typical Operating Characteristics (Cont.) THD+N vs. Output Power THD+N vs. Output Power 10 VDD=3.3V RL=16Ω Ci=1µF CC=1000µF BW<80KHz SE mode 1 Fin=20Hz THD+N (%) THD+N (%) 1 10 Fin=20KHz 0.1 VDD=3.3V RL=32Ω Ci=1µF CC=1000µF BW<80KHz SE mode 0.1 Fin=20KHz Fin=20Hz Fin=1KHz Fin=1KHz 0.01 10m 20m 50m 0.01 10m 100m Output Power (W) 10 0.1 1 THD+N (%) THD+N (%) VDD=5V RL=4Ω Ci=1µF PO=1.3W 1 BW<80KHz BTL mode Left Channel Right Channel VDD=5V RL=8Ω Ci=1µF PO=0.9W BW<80KHz BTL mode 0.1 Right Channel Left Channel 0.01 0.01 100 1K 0.001 20 10K 20K 100 10K 20K THD+N vs. Frequency THD+N vs. Frequency 10 10 VDD=5V RL=16Ω Ci=1µF CC=1000µF PO=110mW BW<80KHz SE mode 1 THD+N (%) THD+N (%) 1K Frequency (Hz) Frequency (Hz) 0.1 Right Channel 0.01 0.001 20 100m THD+N vs. Frequency THD+N vs. Frequency 1 50m Output Power (W) 10 0.001 20 20m 1K 0.001 20 10K 20K Right Channel Left Channel 100 1K 10K 20K Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 0.1 0.01 Left Channel 100 VDD=5V RL=32Ω Ci=1µF CC=1000µF PO=60mW BW<80KHz SE mode 6 www.anpec.com.tw APA2036 Typical Operating Characteristics (Cont.) Crosstalk vs. Frequency Crosstalk vs. Frequency +0 VDD=5V RL=4Ω Ci=1µF PO=1.3W BW<80KHz BTL mode -20 -30 -40 VDD=5V RL=8Ω Ci=1µF PO=0.9W BW<80KHz BTL mode -20 -30 -50 -60 -70 -80 -90 T -10 -40 Crosstalk (dB) -10 Crosstalk (dB) +0 -50 -60 -70 -80 -90 Right to Left -100 Left to Right -100 Left to Right -110 -120 20 100 -110 1K -120 20 10K 20K Right to Left 100 20K +0 VDD=5V RL=16Ω Ci=1µF Cc=1000uF PO=110mW BW<80KHz SE mode -20 -30 -40 -50 -20 -30 -40 -60 -70 Left to Right -80 -90 Right to Left -100 -50 -60 -70 -80 Left to Right -90 Right to Left -100 -110 -110 -120 20 VDD=5V RL=32Ω Ci=1µF Cc=1000uF Po=60mW BW<80KHz SE mode -10 Crosstalk (dB) -10 Crosstalk (dB) 2K Crosstalk vs. Frequency Crosstalk vs. Frequency +0 100 1K -120 20 10K 20K 100 1K 10K 20K Frequency (Hz) Frequency (Hz) Output Noise Voltage vs. Frequency Output Noise Voltage vs. Frequency 50µ 50µ Right Channel Output Noise Voltage (Vrms) Output Noise Voltage (Vrms) 1K Frequency (Hz) Frequency (Hz) 20µ Left Channel 10µ VDD=5V RL=4Ω Ci=1µF BW<80KHz A-Weighting BTL mode 100 Left Channel 10µ VDD=5V RL=8Ω Ci=1µF BW<80KHz A-Weighting BTL mode 1µ 1µ 20 Right Channel 20µ 1K 2K 20 10K 20K Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 100 1K 10K 20K Frequency (Hz) Frequency (Hz) 7 www.anpec.com.tw APA2036 Typical Operating Characteristics (Cont.) Output Noise Voltage vs. Frequency Output Noise Voltage vs. Frequency 50µ Output Noise Voltage (Vrms) 20µ Right Channel Left Channel VDD=5V RL=16Ω Ci=1µF BW<80KHz A-Weighting SE mode 1µ Left Channel VDD=5V RL=32Ω Ci=1µF BW<80KHz A-Weighting SE mode 1µ 20 50 100 200 500 1K 2K 5K Right Channel 10µ 10K 20K 20 50 100 200 +120 +8 +60 +6 VDD=5V RL=4Ω Ci=1µF PO=130mW BTL mode 10 100 Gain(dB) +0 Phase(deg) Gain(dB) Phase +4 +0 10K 20K 10K +60 Phase +4 +0 VDD=5V RL=8Ω Ci=1µF PO=90mW BTL mode +0 -120 100K 200K 10 1K 10K -120 100K 200K Frequency (Hz) Frequency Response Frequency Response -0 -60 100 Frequency (Hz) -0 +270 +270 Gain Gain -1 +240 -1 +240 -2 +210 -2 +210 -4 -5 -6 10 +180 VDD=5V RL=16Ω Ci=1µF CC=1000µF PO=11mW SE mode 100 +150 Gain(dB) Phase -3 Phase(deg) Gain(dB) 5K +120 +2 -60 1K 2K Gain Gain +6 +2 1K Frequency Response Frequency Response +8 500 Frequency (Hz) Frequency (Hz) Phase(deg) 10µ 20µ 10K VDD=5V RL=32Ω Ci=1µF CC=1000µF PO=6mW SE mode -5 -6 +90 100K 200K 10 100 +150 +120 1K 10K +90 100K 200K Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 +180 -4 +120 1K Phase -3 Phase(deg) Output Noise Voltage (Vrms) 50µ 8 www.anpec.com.tw APA2036 Typical Operating Characteristics (Cont.) PSRR vs. Frequency PSRR vs. Frequency +0 +0 VDD=5V RL=4Ω CB=2.2µF Vrr=200mVrms BTL mode -10 -20 -30 -40 -50 -30 PSRR (dB) PSRR (dB) -20 VDD=5V RL=8Ω CB=2.2µF Vrr=200mVrms BTL mode -10 Left Channel -40 -50 Left Channel -60 -60 Right Channel -70 -70 -80 20 100 1K Right Channel -80 20 10K 20K 100 1K Frequency (Hz) 20K PSRR vs. Frequency PSRR vs. Frequency +0 +0 VDD=5V RL=16Ω CB=2.2µF Vrr=200mVrms SE mode -10 -20 VDD=5V RL=32Ω CB=2.2µF Vrr=200mVrms SE mode -10 -20 -30 PSRR (dB) PSRR (dB) 10K Frequency (Hz) -40 -50 -30 -40 -50 Right Channel -60 -60 Left Channel -70 -80 20 100 Left Channel Right Channel -70 1K -80 20 10K 20K 100 Frequency (Hz) Output Power vs. Supply Voltage 2.00 RL=4Ω Ci=1µF Fin=1KHz BTL mode 3.0 1.75 1.50 Output Power (W) 3.5 Output Power (W) 10K 20K Output Power vs. Supply Voltage 4.0 2.5 THD+N=10% 2.0 1.5 THD+N=1% 1.0 0.5 0.0 1K Frequency (Hz) RL=8Ω Ci=1µF Fin=1KHz BTL mode 1.25 THD+N=10% 1.00 THD+N=1% 0.75 0.50 0.25 3.0 3.5 4.0 4.5 5.0 0.00 5.5 Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 3.0 3.5 4.0 4.5 5.0 5.5 Supply Voltage (Volt) Supply Voltage (Volt) 9 www.anpec.com.tw APA2036 Typical Operating Characteristics (Cont.) Output Power vs. Supply Voltage Output Power vs. Supply Voltage 300 200 THD+N=10% 150 RL=32Ω Ci=1µF CC=1000µF Fin=1KHz SE mode 125 Output Power (mW) 250 Output Power (mW) 150 RL=16Ω Ci=1µF CC=1000µF Fin=1KHz SE mode THD+N=1% 100 100 50 THD+N=10% 75 THD+N=1% 50 25 0 3.0 3.5 4.0 4.5 5.0 0 5.5 3.0 Supply Voltage (Volt) 3.5 4.0 4.5 5.0 5.5 Supply Voltage (Volt) Power Dissipation vs. Output Power Power Dissipation vs. Output Power 1.4 100 1.2 RL=16Ω RL=4Ω Power Dissipation(mW) Power Dissipation(W) 80 1.0 0.8 RL=8Ω 0.6 0.4 VDD=5V THD+N<1% BTL mode 0.2 0.0 0.0 0.5 1.0 1.5 2.0 60 40 VDD=5V THD+N<1% SE mode 20 0 2.5 RL=32Ω 0 Output Power (W) 50 100 150 200 Output Power (mW) Supply Current vs. Output Power Supply Current vs. Output Power 50 0.8 40 Supply Current (mA) Supply Current (A) 0.6 RL=4Ω 0.4 RL=8Ω 0.2 VDD=5V THD+N<1% BTL mode RL=16Ω 30 RL=32Ω 20 VDD=5V THD+N<1% SE mode 10 0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 0 Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 50 100 150 200 Output Power (mW) Output Power (W) 10 www.anpec.com.tw APA2036 Typical Operating Characteristics (Cont.) GSM Power Supply Rejection vs. Frequency +0 No Load 5.0 -50 4.0 -100 3.0 Output Voltage (dBV) Supply Current (mA) BTL mode SE mode 2.0 1.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -50 -100 -150 5.5 -150 +0 Supply Voltage (dBV) Supply Current vs. Supply Voltage 6.0 0 400 800 1.2K 1.6K 2K Frequency (Hz) Supply Voltage (Volt) GSM Power Supply Rejection vs. Time Output Transient at Power-On VDD 1 VDD VOUT 3 VOUT VOUTP 2 1,2 CH1: VDD, 500mV/Div, DC Voltage Offset = 5.0V CH2: VOUT (VOUTP-VOUTN), 20mV/Div, DC CH1: VDD, 1V/Div, DC CH2: VOUTP, 1V/Div, DC CH3: VOUT (VOUTP-VOUTN), 50mV/Div, DC TIME: 20ms/Div TIME: 100ms/Div Output Transient at Shutdown Active Output Transient at Shutdown Release VSHUTDOWN VOUT VOUT 3 3 VOUTP VOUTP VSHUTDOWN 1,2 1,2 CH1: VSHUTDOWN, 1V/Div, DC CH2: VOUTP, 1V/Div, DC CH1: VSHUTDOWN, 1V/Div, DC CH2: VOUTP, 1V/Div, DC CH3: VOUT(VOUTP-VOUTN), 50mV/Div, DC CH3: VOUT(VOUTP-VOUTN), 50mV/Div, DC TIME: 100ms/Div TIME: 500ms/Div Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 11 www.anpec.com.tw APA2036 Block Diagram LINN LBYPASS LOUTP Bias Voltage Generator LOUTN RINN RBYPASS ROUTP Bias Voltage Generator ROUTN SE/BTL SHUTDOWN SE/BTL Mode Selection VDD Power and Depop circuit Shutdown circuit GND Pin Description Pin Function Description NO. Name 1,4,9,11 GND 2 SE/BTL 3 SHUTDOWN 5 LOUTN 6,15 VDD 7 LOUTP 8 LINN 10 LBYPASS Bypass capacitor connection pin for the bias voltage generator. 12 RBYPASS Bypass capacitor connection pin for the bias voltage generator. 13 RINN 14 ROUTP Right channel output in BTL mode and SE mode. As “Typical Application Circuit” shown, this pin’s output signal is inverted against RINN input signal. 16 ROUTN Right channel output in BTL mode, high impedance in SE mode. Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 Ground connection of circuitry. Connect all GND pins to the thermal pad and system ground plane. Output Mode control pin, high for SE output mode and low for BTL mode. Shutdown mode control pin. Pulling high the voltage on this pin shuts off the IC. In shutdown mode, the IC only draws 0.5µA (typical) of supply current. Left channel output in BTL mode, high impedance in SE mode. Supply voltage input pin. Connect all of the VDD pins to supply voltage. Left channel output in BTL mode and SE mode. As “Typical Application Circuit” shown, this pin’s output signal is inverted against LINN input signal. Left channel input terminal. Right channel input terminal. 12 www.anpec.com.tw APA2036 Typical Application Circuit VDD Cs 0.1µF CiL 1µF RiL 20KΩ RfL VDD 20KΩ 10µF GND CCL LINN L-CH Input LOUTP 100µF LBYPASS CB 2.2µF 4Ω LOUTN CinR RiR 1µF 20KΩ R-CH Input Bias Voltage Generator 1KΩ SE/BTL Signal CCR RINN Control Pin Ring ROUTP Sleeve Tip Headphone Jack RfR 100µF 1KΩ 20KΩ RBYPASS VDD 100KΩ SE/BTL Signal Shutdown Signal Bias Voltage Generator 4Ω ROUTN 100KΩ SE/BTL SHUTDOWN Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 SE/BTL Mode Selection Shutdown circuit 13 www.anpec.com.tw APA2036 Function Description Single-Ended (SE) Operation Bridge-Tied Load (BTL) Operation To consider the single-supply SE configuration shown in Rf Typical Application Circuit, a coupling capacitor is required to block the DC offset voltage from reaching the load. Ri OUTP These capacitors can be quite large (approximately 33µF to 1000µF) so they tend to be expensive, occupy valuable OP1 PCB area, and have the additional drawback of limiting low-frequency performance of the system (refer to the RL OUTN Output Coupling Capacitor). OP2 SE/BTL Mode Selection Function Bias Voltage Generator Eazy switch between BTL and SE modes is one of its most important costs saving features for the APA2036. Figure 1: APA2036 internal configuration (each channel) This feature eliminates the requirement for an additional headphone amplifier in applications where internal ste- The power amplifier’s (OP1) gain is set by external resistance Ri and Rf, while the second amplifier (OP2) is internally fixed in a unity-gain and inverting configuration. Fig- reo speakers are driven in BTL mode but external headphone or speakers must be accommodated. ure 1 shows that the output of OP1 is connected to the input of OP2, which results in the output signals of both Inside of the APA2036, two separate amplifiers drive OUTP and OUTN (see Figure 1). The SE/BTL input controls the amplifiers with identical in magnitude, but out of phase 180°. Consequently, the differential gain for each chan- operation of the follower amplifier that drives LOUTP and ROUTN. nel is 2X (Gain of SE mode). By driving the load differentially through outputs OUTP and OUTN, an amplifier configuration is commonly referred to established bridged mode. BTL mode operation is different from the classical single-ended SE am- • When SE/BTL keeps low, the OP2 turns on and the • APA2036 is in the BTL mode. When SE/BTL keeps high, the OP2 is in a high output impedance state, which configures the APA2036 as SE driver from OUTP. IDD is reduced by approximately plifier configuration where one side of its load is connected to ground. one-half in SE mode. A BTL amplifier design has a few distinct advantages over Control of the SE/BTL input can be a logic-level TTL source the SE configuration, as it provides differential drive to the load, thus doubles the output swing for a specified sup- or a resistor divider network or the stereo headphone jack with switch pin as shown in Typical Application Circuit. ply voltage. Four times the output power is possible as compared with a SE amplifier in the same conditions. A BTL 1KΩ VDD configuration, such as the one used in the APA2036, also creates a second advantage over SE amplifiers. Since 100KΩ the differential outputs, ROUTP, ROUTN, LOUTP, and LOUTN, are biased at half-supply, DC voltage doesn’t Ring SE/BTL have to exist across the load. This eliminates the need for an output coupling capacitor which is required in a Tip Sleeve Headphone Jack single supply, SE configuration. Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 Control Pin Figure 2: SE/BTL input selection by phonejack plug 14 www.anpec.com.tw APA2036 Function Description (Cont.) SE/BTL Mode Selection Function (Cont.) Over-Current Protection In Figure 2, input SE/BTL operates as below: The APA2036 monitors the output current. When the cur- When the phonejack plug is inserted, the 1KΩ resistor is disconnected and the SE/BTL input is pulled high to en- rent exceeds the current-limit threshold, the APA2036 turns off the output to prevent the IC damages from over-cur- able the SE mode. Meanwhile, the OUTN amplifier is shut down which turns the speaker to be mute. The OUTP rent or short-circuits condition. When the over-current occurs in power amplifier, the output buffer’s current will amplifier then drives through the output capacitor into the headphone jack. When there is no headphone plugged be foldbacked to a low setting level, and it will release when over-current situation is no long existence. On the into the system, the contact pin of the headphone jack is connected from the signal pin, and the voltage divider is contrary, if the over-current period is long enough and the IC’s junction temperature reaches the thermal protection set up by resistors 100KΩ and 1KΩ. Resistor 1KΩ then is pulled low the SE/BTL pin, enabling the BTL function. threshold, the IC will enter thermal protection mode. Shutdown Function In order to reduce power consumption while not in use, the APA2036 with shutdown function externally turns off the amplifier bias circuitry. This shutdown feature turns the amplifier off when logic high is placed on the SHUTDOWN pin for the APA2036. The trigger point between a logic high and logic low level is typical 0.4VDD. It would be better to switch between ground and the supply voltage VDD to provide maximum device performance. By switching the SHUTDOWN pin to high level, the amplifier enters a low consumption current state; IDD for the APA2036 is in shutdown mode. In normal operation, the APA2036’s SHUTDOWN pin should be pulled to low level to keep the IC out of the shutdown mode. The SHUTDOWN pin should be tied to a definite voltage to avoid unwanted state changes. Thermal Protection The over-temperature circuit limits the junction temperature of the APA2036. When the junction temperature exceeds T J = +150 oC, a thermal sensor turns off the amplifier, allowing the devices to cool. The thermal sensor allows the amplifier to start up after the junction temperature cools down about 125oC. The thermal protection designed with a 25oC hysteresis lowers the average TJ during continuous thermal overload conditions, which is increasing lifetime of the IC. Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 15 www.anpec.com.tw APA2036 Application Information Effective Bypass Capacitor (CB) As other power amplifiers, proper supply bypassing is critical for low noise performance and high power supply Input Resistance (Ri) The gain of the APA2036 is set by the external resistors (Ri and Rf). R BTL Gain = −2 × f Ri SE Gain = − Rf Ri rejection. The capacitors located on the bypass and power supply pins should be as close to the device as possible. (1) The effect of a larger half-supply bypass capacitor will improve PSRR due to increased half-supply stability. Typi(2) cal application employs a 5V regulator with 1.0µF and a 0.1µF bypass as supply filtering. This does not elimi- BTL mode operation brings the factor of 2 in the gain equation due to the inverting amplifier mirroring the volt- nate the need for bypassing the supply nodes of the APA2036. The selection of bypass capacitors, especially age swing across the load. The input resistance will affect the low frequency performance of audio signal. CB, thus depends upon desired PSRR requirements, click-and-pop performance. To avoid start-up pop noise occurred, the bypass voltage Input Capacitor (Ci) should rise slower than the input bias voltage and the relationship shown in equation (5) should be maintained. V (5) CB B + 0.4 > 3RiCi 20µ The bypass capacitor is fed from a 160KΩ resistor inside In the typical application, an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the minimum input impedance Ri from a high-pass filter with the corner frequency are determined in the following the amplifier. Bypass capacitor, CB, values of 1µF to 2.2µF ceramic or tantalum low-ESR capacitors are recom- equation: FC(highpass ) = 1 2πR iCi (3) mended for the best THD+N and noise performance. The bypass capacitance also effects the start up time. It is determined in the following equation: V Tstart-up = CB B + 0.4 (6) 20µ 1 Note : VB = VDD 2 For example, if CB=2.2µF, VDD=5V, then the start-up time The value of Ci is important to consider as it directly affects the low frequency performance of the circuit. Consider the example where Ri is 20KΩ and the specification calls for a flat bass response down to 40Hz. Equation is reconfigured as followed: Ci = 1 2πR iFC (4) is 0.68s. Output Coupling Capcaitor (CC) Consider to input resistance variation, the Ci is 0.2µF, so one would likely choose a value in the range of 0.22µF to In the typical single-supply SE configuration, an output coupling capacitor (CC) is required to block the DC bias at the output of the amplifier thus preventing DC currents in 1.0µF. A further consideration for this capacitor is the leakage path from the input source through the input network the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high- (Ri +Rf, Ci) to the load. This leakage current creates a DC offset voltage at the leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of pass filter governed by following equation: 1 FC(highpass ) = (7) 2πRLCC For example, a 330µF capacitor with an 8Ω speaker would attenuate low frequencies below 60.6Hz. The main the capacitor should face the amplifier input in most applications as the DC level is held at VDD/2, which is likely disadvantage, from a performance standpoint, is typically small load impedance, which drives the low-frequency higher than the source DC level. Please note that it is important to confirm the capacitor polarity in the application. corner higher degrading the bass response. Large values of CC are required to pass low frequencies into the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low- load. Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 16 www.anpec.com.tw APA2036 Application Information (Cont.) In the most cases, choosing a small value of Ci in the range of 0.22µF to 1µF and CB being equal to 2.2µF should Power Supply Decoupling (CS) The APA2036 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to cause a virtually click-less and pop-less turn-on. A high gain amplifier intensifies the problem as the small ensure the output total harmonic distortion (THD+N) is as low as possible. Power supply decoupling also pre- delta in voltage is multiplied by the gain. Therefore it is advantageous to use low-gain configurations. vents the oscillations causing by long lead length between the amplifier and the speaker. BTL Amplifier Efficiency The optimum decoupling is achieved by using two different capacitors that target on different types of noise on the An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power sup- power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent- ply to the power is delivered to the load. The following equations are the basis for calculating amplifier efficiency. P (8) Efficiency = O PSUP where: 2 2 V V (9) PO = O.RMS = P 2RL RL series-resistance (ESR) ceramic capacitor, typically 0.1µF is placed as close as possible to the device VDD lead works best. For filtering lower frequency noise signals, a large aluminum electrolytic capacitor of 10µF or greater placed near the audio power amplifier is recommended. VO.RMS = Optimizing Depop Circuitry Circuitry has been included in the APA2036 to minimize the amount of popping noise at power-up while not in 2 2VP πRL Efficiency of a BTL configuration: 2 VP PO 2RL πVP = = 2V 4VDD PSUP P VDD × πRL PSUP = VDD × IDD.AVG = VDD shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to eliminate click-andpop, all capacitors must be fully discharged before turnon. Rapid on/off switching of the device or the shutdown func- (10) (11) (12) Table 1 is for calculating efficiency for four different out- tion will cause the click-and-pop circuitry. The value of Ci will also affect turn-on pops (refer to Effective Bypass put power levels. Note that the efficiency of the amplifier is quite low for Capacitance). The bypass voltage rises up but should be slower than input bias voltage. Although the bypass pin lower power levels and rises sharply as power to the load is increased resulting in nearly flat internal power dissi- current source cannot be modified, the size of CB can be changed to alter the device turn-on time and the amount pation over the normal operating range. In addition, the internal dissipation at full output power is less than in the of click-and-pops. By increasing the value of CB, turn-on pop can be reduced. However, the tradeoff for using a half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a larger bypass capacitor is to increase the turn-on time for this device. There is a linear relationship between the stereo 1W audio system with 8Ω loads and a 5V supply, the maximum draw on the power supply is almost 3W. size of CB and the turn-on time. In a SE configuration, the output coupling capacitor (CC) In the equation, VDD is in the denominator. One last key point to remember about linear amplifiers (either SE or is the particular concern. This capacitor discharges through the internal 10KΩ resistors. Depending on the BTL) is how to manipulate the terms in the efficiency equation to utmost advantage when possible. Note that in equa- size of CC, the time constant can be relatively large. To reduce transients in SE mode, an external 1KΩ resistor tion (12), VDD is in the denominator. This indicates that as VDD goes down, and efficiency goes up. In other words, can be placed in parallel with the internal 10KΩ resistor. The tradeoff for using this resistor is an increase in qui- choosing the correct supply voltage and speaker impedance for the application by using the efficiency analysis. escent current. Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 VP 17 www.anpec.com.tw APA2036 Application Information (Cont.) Thermal Consideration BTL Amplifier Efficiency (Cont.) Linear power amplifiers dissipates a significant amount PO (W) Efficiency (%) IDD (A) VPP (V) PO (W) 0.25 30.37 0.16 2.00 0.57 0.50 43.37 0.23 2.83 0.65 1.00 61.65 0.32 4.00 0.62 1.25 69.03 0.36 4.47 0.56 of heat in the package in normal operating condition. The first consideration to calculate maximum ambient temperatures is the numbers from the Power Dissipation vs. Output Power graphs are per channel values, so the dissipation of the IC heat needs to be doubled for two-channel operation. Given θJA, the maximum allowable junc- * *High peak voltages cause increasing of the THD+N. Table 1. Efficiency vs. Output Power in 5-V/8Ω Differential tion temperature (TJMax), the total internal dissipation (PD), and the maximum ambient temperature can be calcu- Amplifier Systems Power Dissipation lated with the following equation. The maximum recommended junction temperature for the APA2036 is 150°C. Whether the power amplifier is operated in BTL or SE modes, power dissipation is a major concern. Equation The internal dissipation figures are taken from the Power Dissipation vs. Output Power graphs. (13) states the maximum power dissipation point for a SE mode operating at a given supply voltage and driving TAMax = TJMax -θJA x PD a specified load. SE mode : PD, MAX = VDD (16) 150 – 45 (0.8x2) = 78°C 2 (13) 2 π 2R L The APA2036 is designed with a thermal shutdown protection that turns the device off when the junction tem- In BTL mode operation, the output voltage swing is doubled in SE mode. Thus the maximum power dissipa- perature surpasses 150°C to prevent damaging the IC. tion point for a BTL mode operated at the same given conditions is 4 times in SE mode. Layout Consideration π 2R L (14) 1mm 0.5mm 2.5mm Even with this substantial increase in power dissipation, the APA2036 does not require extra heatsinking. The power dissipation from equation (14), assuming a 5V power supply and an 8Ω load, must not be greater than 0.65mm the power dissipation that results from the equation (15): PD, MAX = Thermal Via diameter 0.3mm x 4 2 TJ, MAX − TA θ JA 4.9mm BTL mode : PD, MAX = 2 VDD 2.5mm Ground plane for Thermal PAD (15) Since the maximum junction temperature (TJ.MAX) of the APA2036 is 150OC and the ambient temperature (TA) is Figure 3: TQFN4x4-16 Land Pattern Recommendation defined by the power system design, the maximum power dissipation, which the IC package is able to handle, can be obtained from equation (15). Once the power dissipation is greater than the maximum limit (PD, Max), the supply voltage (VDD) must be decreased, the load impedance (R L) must be increased or the ambient temperature should be reduced. Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 18 www.anpec.com.tw APA2036 Application Information (Cont.) Layout Consideration (Cont.) 1. All components should be placed close to the APA2036. For example, the input capacitor (Ci) should be close to APA2036’s input pins to avoid causing noise coupling to APA2036’s high impedance inputs; the decoupling capacitor (CS ) should be placed by the APA2036’s power pin to decouple the power rail noise. 2. The output traces should be short, wide (>50mil) and symmetric. 3. The input trace should be short and symmetric. 4. The power trace width should be greater than 50mil. 5. The TQFN4X4-16 Thermal PAD should be soldered on PCB, and the ground plane needs soldered mask (to avoid short circuit) except the Thermal PAD area. Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 19 www.anpec.com.tw APA2036 Package Information TQFN4x4-20 D E A b D2 E2 Pin 1 Corner A1 L A3 e S Y M B O L TQFN4x4-16 MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 A3 b 0.20 REF 0.25 D D2 2.50 0.098 2.80 2.50 0.110 0.157 BSC 0.110 0.098 2.80 0.65 BSC 0.30 0.014 0.157 BSC 4.00 BSC e L 0.010 0.35 4.00 BSC E E2 0.008 REF 0.026 BSC 0.012 0.50 0.020 Note : Follow JEDEC MO-220 WGGC-3. Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 20 www.anpec.com.tw APA2036 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H T1 C d D W E1 F 12.4+2.00 13.0+0.50 330.0±2.00 50 MIN. 0.10 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5± -0.00 -0.20 TQFN 4x4-16 P0 P1 P2 D0 D1 T A0 B0 K0 1.5+0.10 0.6+0.00 4.0±0.10 8.0±0.10 2.0±0.10 4.30±0.20 4.30±0.20 1.30± 0.20 1.5 MIN. -0.00 -0.40 (mm) Devices Per Unit Package Type TQFN4x4-16 Unit Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 Quantity 3000 21 www.anpec.com.tw APA2036 Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone TL to TP Ramp-up Temperature TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25°C to Peak Time Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 sec 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Time 25°C to Peak Temperature Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Note: All temperatures refer to topside of the package. Measured on the body surface. Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 22 www.anpec.com.tw APA2036 Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures Volume mm3 ≥350 225 +0/-5°C 225 +0/-5°C 3 Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 240 +0/-5°C 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures 3 3 3 Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0°C* 260 +0°C* 260 +0°C* 1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C* * Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Package Thickness Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.1 - Feb., 2008 23 www.anpec.com.tw