APL5620 2A, Ultra Low Dropout (0.24V Typical) Linear Regulator General Description Features • • • • • • Ultra Low Dropout - 0.24V (typical) at 2A Output Current The APL5620 is a 2A ultra low dropout linear regulator. The IC needs two supply voltages, one is a control volt- 0.8V Reference Voltage age (V CNTL) for the control circuitry, the other is a main supply Voltage(VIN) for power conversion, to reduce power High Output Accuracy - ±1.5% Over Line, Load, and Temperature Range dissipation and provide extremely low dropout voltage. The APL5620 integrates many functions. A Power-On-Re- Fast Transient Response set (POR) circuit monitors both supply voltages on VCNTL and VIN pins to prevent erroneous operations. The func- Adjustable Output Voltage tions of thermal shutdown and current-limit protect the device against thermal and current over-loads. A POK Power-On-Reset Monitoring on Both VCNTL and VIN Pins • • • • • • • • indicates that the output voltage status with a delay time set internally. It can control other converter for power Internal Soft-Start Current-Limit and Short Current-Limit Protections sequence. The APL5620 can be enabled by other power systems. Pulling and holding the EN voltage below 0.4V Thermal Shutdown with Hysteresis Open-Drain VOUT Voltage Indicator (POK) shuts off the output. The APL5620 is available in a TDFN3x3-10 package Low Shutdown Quiescent Current ( < 30µA ) which features small size as TDFN3x3-10 and an Exposed Pad to reduce the junction-to-case resistance to Shutdown/Enable Control Function Simple TDFN3x3-10 Package with Exposed Pad extend power range of applications. Lead Free and Green Devices Available (RoHS Compliant) Simplified Application Circuit Applications • • • VCNTL Motherboards, VGA Cards Notebook PCs VIN Add-in Cards VCNTL Pin Configuration POK VIN POK VOUT VOUT VOUT VOUT VOUT FB POK 1 2 3 4 5 GND APL5620 10 VCNTL 9 VIN 8 VIN 7 VIN 6 EN EN Enable EN FB GND Optional TDFN3x3-10 (Top View) = Exposed Pad (connected to ground plane for better heat dissipation) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2009 1 www.anpec.com.tw APL5620 Ordering and Marking Information Package Code QB : TDFN3x3-10 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APL5620 Assembly Material Handling Code Temperature Range Package Code APL 5620 XXXXX APL5620 QB : XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol VCNTL VIN VOUT (Note 1) Parameter VCNTL Supply Voltage (VCNTL to GND) VIN Supply Voltage (VIN to GND) VOUT to GND Voltage POK to GND Voltage Rating Unit -0.3 ~ 6 V -0.3 ~ 6 V -0.3 ~ VIN+0.3 V -0.3 ~ 7 EN, FB to GND Voltage -0.3 ~ VCNTL+0.3 V PD Power Dissipation Internally Limited W TJ Maximum Junction Temperature TSTG Storage Temperature Range TSDR Maximum Lead Soldering Temperature, 10 Seconds 150 ο -65 ~ 150 ο 260 ο C C C Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA θJC Parameter Junction-to-Ambient Resistance in Free Air Typical Value Unit (Note 2) TDFN3x3-10 Junction-to-Case Resistance in Free Air (Note 3) TDFN3x3-10 50 o 6 o C/W C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Note 3: The “Thermal Pad Temperature” is measured on the PCB copper area connected to the thermal pad of package. 1 2 3 4 5 10 9 8 7 6 Measured Point PCB Copper Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2009 2 www.anpec.com.tw APL5620 Recommended Operating Conditions Symbol VCNTL VIN Parameter VCNTL Supply Voltage VIN Supply Voltage VOUT VOUT Output Voltage (when VCNTL-VOUT>1.7V) IOUT VOUT Output Current R2 FB to GND COUT VOUT Output Capacitance Range Unit 3.0 ~ 5.5 V 1.2 ~ 5.5 V 0.8 ~ VIN – VDROP V 0~2 A 1k ~ 24k Ω IOUT = 2A at 25% nominal VOUT 8 ~ 770 IOUT = 1A at 25% nominal VOUT 8 ~ 1400 IOUT = 0.5A at 25% nominal VOUT 8 ~ 1700 µF ESR of VOUT Output Capacitor 0 ~ 200 TA Ambient Temperature -40 ~ 85 ο TJ Junction Temperature -40 ~ 125 ο ESRCOUT mΩ C C Electrical Characteristics Refer to the typical application circuits. These specifications apply over VCNTL=5V, vIN=1.8v, VOUT=1.2V, and TA= -40 ~ 85oC, unless otherwise specified. Typical values are at TJ=25oC. Symbol Parameter APL5620 Test Conditions Min. Typ. Max. Unit SUPPLY CURRENT IVCNTL ISD - 1.0 1.5 mA VCNTL Supply Current at Shutdown EN = GND VCNTL Supply Current EN = VCNTL, IOUT=0A - 20 30 µA VIN Supply Current at Shutdown - - 1 µA 2.5 2.7 2.9 V - 0.4 - V 0.8 0.9 1.0 - 0.5 - 0.792 0.8 0.808 V -1.5 - +1.5 % - 0.06 0.25 % -0.15 - +0.15 %/V EN = GND, VIN=5.5V POWER-ON-RESET (POR) Rising VCNTL POR Threshold VCNTL POR Hysteresis Rising VIN POR Threshold VIN POR Hysteresis V OUTPUT VOLTAGE VREF Reference Voltage FB=VOUT, IOUT=10mA, TJ=25°C Output Voltage Accuracy IOUT= 0~2A, TJ= -40~125 oC Load Regulation IOUT=0A ~2A Line Regulation IOUT=10mA, VCNTL= 3.0 ~ 5.5V VOUT Pull-Low Resistance VCNTL=3.3V, VEN=0V, VOUT<0.8V FB Input Current VFB=0.8V - 85 - Ω -100 - 100 nA TJ=25oC - 0.26 0.32 TJ=-40~125oC - - 0.44 TJ=25 C - 0.25 0.30 TJ=-40~125oC - - 0.41 TJ=25oC - 0.24 0.29 TJ=-40~125oC - - 0.39 DROPOUT VOLTAGES VOUT=2.5V VDROP VIN-to-VOUT Dropout Voltage VCNTL=4.5V, VOUT=1.8V IOUT=2A VOUT=1.2V Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2009 3 o V www.anpec.com.tw APL5620 Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VCNTL=5V, vIN=1.8v, VOUT=1.2V, and TA= -40 ~ 85oC, unless o otherwise specified. Typical values are at TJ=25 C. Symbol Parameter Test Conditions APL5620 Unit Min. Typ. Max. 3.0 3.6 4.3 2.5 - - - 0.8 - A PROTECTIONS ILIM Current-Limit Level TJ=25οC ο TJ= -40 ~ 125 C ISHORT Short Current-Limit Level VFB<0.2V Short Current-Limit Blanking Time From beginning of soft-start TSD A 0.6 1.6 - ms - 170 - o - 50 - o VEN rising 0.5 0.8 1.1 V - 80 - mV EN=GND - 5 - µA 0.3 0.6 1 ms 90 92 94 % - 8 - % POK sinks 5mA - 0.25 0.4 V POK Denounce Interval VFB<falling POK voltage threshold - 10 - µs POK Delay Time From VFB =VTHPOK to rising edge of the VPOK 1 2 4 ms Thermal Shutdown Temperature TJ rising Thermal Shutdown Hysteresis C C ENABLE AND SOFT-START EN Logic High Threshold Voltage EN Hysteresis EN Pull-High Current TSS Soft-Start Interval POWER-OK AND DELAY VTHPOK Rising POK Threshold Voltage VFB rising POK Threshold Hysteresis POK Pull-Low Voltage Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2009 4 www.anpec.com.tw APL5620 Typical Operating Characteristics Current-Limit vs. Junction Temperature 4.3 900 VOUT = 1.2V 3.9 Short Current-Limit, ISHORT (mA) Current-Limit, ILIM (A) 4.1 VCNTL = 5V 3.7 3.5 3.3 VCNTL = 3.3V 3.1 2.9 2.7 2.5 -50 -25 Short Current-Limit vs. Junction Temperature 0 25 50 75 100 850 800 700 650 VCNTL = 3.3V 600 550 500 125 VCNTL = 5V 750 -50 Junction Temperature (oC) Dropout Voltage vs. Output Current 25 50 75 100 125 Dropout Voltage vs. Output Current 400 VCNTL = 5V VOUT = 1.2V 350 Dropout Voltage, VDROP (mV) Dropout Voltage, VDROP (mV) 0 Junction Temperature (oC) 400 TJ = 125° C 300 TJ = 75° C 250 TJ = 25° C 200 150 TJ = 0° C 100 TJ = - 40° C 50 VCNTL = 3.3V VOUT = 1.2V 350 TJ = 125° C 300 TJ = 75° C 250 TJ = 25° C 200 150 TJ = 0° C 100 TJ = - 40° C 50 0 0 0 0.5 1 1.5 0 2 0.5 1 1.5 2 Output Current, IOUT (A) Output Current, IOUT (A) Dropout Voltage vs. Output Current Dropout Voltage vs. Output Current 450 VCNTL = 5V VOUT = 1.8V 350 Dropout Voltage, VDROP (mV) 400 Dropout Voltage, VDROP (mV) -25 TJ = 125° C 300 TJ = 75° C 250 TJ = 25° C 200 150 TJ = 0° C 100 TJ = - 40° C 50 VCNTL = 3.3V 400 TJ = 125° C VOUT = 1.5V 350 TJ = 75° C 300 TJ = 25° C 250 200 150 TJ = 0° C 100 TJ = - 40° C 50 0 0 0 0.5 1 1.5 0 2 1 1.5 2 Output Current, IOUT (A) Output Current, IOUT (A) Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2009 0.5 5 www.anpec.com.tw APL5620 Typical Operating Characteristics (Cont.) Reference Voltage vs. Junction Temperature Dropout Voltage vs. Output Current 450 0.808 VCNTL = 5V VOUT = 2.5V Reference Voltage, VREF (V) Dropout Voltage, VDROP (mV) 400 TJ = 125° C 350 300 TJ = 75° C 250 TJ = 25° C 200 150 TJ = 0° C 100 TJ = - 40° C 50 0.5 1 0.804 0.802 0.800 0.798 0.796 0.794 0 0 0.806 1.5 0.792 -50 2 Output Current, IOUT (A) 0 -30 VCNTL=4.6~5.4V VIN=1.5V VOUT=1.2V IOUT=2A CIN=COUT=10µF Power Supply Rejection Ratio (dB) Power Supply Rejection Ratio (dB) 0 -20 -40 -50 -60 -70 10000 100000 1000000 Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2009 25 50 75 100 125 -10 -20 VIN Power Supply Rejection Ratio (PSRR) VCNTL=5V VIN=1.55V VINPK-PK=50mV VOUT=1.2V IOUT=2A COUT=10µF -30 -40 -50 100 -80 1000 0 Junction Temperature (oC) VCNTL Power Supply Rejection Ratio (PSRR) -10 -25 1000 10000 100000 100000 Frequency (Hz) 6 www.anpec.com.tw APL5620 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=1.5V, VCNTL=5V, VOUT=1.2V, TA= 25oC unless otherwise specified. Power Off Power On 1 VCNTL VCNTL 1 VIN 2 VIN 2 VOUT VOUT 3 3 4 VPOK VPOK 4 COUT=10µF, C IN=10µF, R L=0.6Ω CH1: V CNTL , 5V/Div, DC CH2: V IN, 1V/Div, DC CH3: V OUT, 1V/Div, DC CH4: V POK, 5V/Div, DC TIME: 5ms/Div COUT=10µF, C IN=10µF, R L=0.6Ω CH1: V CNTL , 5V/Div, DC CH2: V IN, 1V/Div, DC CH3: V OUT, 1V/Div, DC CH4: V POK, 5V/Div, DC TIME: 10ms/Div Over Current Protection Load Transient Response VOUT 1 VOUT 1 IOUT IOUT 4 4 COUT=10µF, CIN=10µF, IOUT=1A to 3.4A IOUT=10mA to 2A to 10mA (rise / fall time = 1µs) COUT=10µF, CIN=10µF CH1: VOUT, 50mV/Div, AC CH4: IOUT, 1A/Div, DC TIME: 20µs/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2009 CH1: VOUT, 1V/Div, DC CH4: IOUT, 1A/Div, DC TIME: 0.2ms/Div 7 www.anpec.com.tw APL5620 Operating Waveforms (Cont.) Refer to the typical application circuit. The test condition is VIN=1.5V, VCNTL=5V, VOUT=1.2V, TA= 25oC unless otherwise specified. Enable Shutdown VEN VEN 1 1 VOUT VOUT 2 2 VPOK VPOK 3 3 IOUT IOUT 4 4 COUT=10µF, CIN=10µF, RL=0.6Ω CH1: VEN, 5V/Div, DC CH2: VOUT, 1V/Div, DC CH3: VPOK, 5V/Div, DC CH4: IOUT, 2A/Div, DC TIME: 5µs/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2009 COUT=10µF, CIN=10µF, RL=0.6Ω CH1: VEN, 5V/Div, DC CH2: VOUT, 1V/Div, DC CH3: VPOK, 5V/Div, DC CH4: IOUT, 2A/Div, DC TIME: 0.5ms/Div 8 www.anpec.com.tw APL5620 Pin Description PIN NO. FUNCTION NAME 1,2,3 VOUT Output pin of the regulator. Connecting this pin to load and output capacitors (10µF at least) is required for stability and improving transient response. The output voltage is programmed by the resistor-divider connected to FB pin. The VOUT can provide 2A (max.) load current to loads. During shutdown, the output voltage is quickly discharged by an internal pull-low MOSFET. 4 FB Voltage Feedback Pin. Connecting this pin to an external resistor divider receives the feedback voltage of the regulator. 5 POK Power-OK signal output pin. This pin is an open-drain output used to indicate the status of output voltage by sensing FB voltage. This pin is pulled low when output voltage is not within the Power-OK voltage window. 6 EN Active-high enable control pin. Applying and holding the voltage on this pin below the enable voltage threshold shuts down the output. When re-enabled, the IC undergoes a new soft-start process. When left this pin open, an internal pull-up current (5µA typical) pulls the EN voltage and enables the regulator. 7,8,9 VIN Main supply input pin for voltage conversions. A decoupling capacitor (≥10µF recommended) is usually connected near this pin to filter the voltage noise and improve transient response. The voltage on this pin is monitored for Power-On-Reset purpose 10 VCNTL Bias voltage input pin for internal control circuitry. Connect this pin to a voltage source (+5V recommended). A decoupling capacitor (1µF typical) is usually connected near this pin to filter the voltage noise. The voltage at this pin is monitored for Power-On-Reset purpose. Exposed Pad GND Ground pin of the circuitry. All voltage levels are measured with respect to this pin. Block Diagram VCNTL Thermal Shutdown VCNTL POR Power-OnReset (POR) 5µA Enable EN 0.8V Control Logic and Soft-Start POR VIN VOUT Error Amplifier Delay Current-Limit and Short Current-Limit 90% VREF ISEN PWOK VREF 0.8V Enable Soft-Start POK GND FB Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2009 9 www.anpec.com.tw APL5620 Typical Application Circuit VCNTL (+5V is preferred) CCNTL 1µF 10 R3 5.1kΩ VCNTL 5 POK VIN POK VOUT VIN +1.8V CIN 10µF 7,8,9 1,2,3 VOUT +1.2V / 2A EN 6 APL5620 EN Enable FB 4 GND Exposed R2 24kΩ Pad R1 12kΩ COUT 10µF (X5R/X7R Recommended) C1 (Optional) (X5R/X7R Recommended) 10µF: GRM31MR60J106KE19 Murata Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2009 10 www.anpec.com.tw APL5620 Function Description Power-On-Reset Thermal Shutdown A Power-On-Reset (POR) circuit monitors both of supply A thermal shutdown circuit limits the junction temperature of APL5620. When the junction temperature exceeds voltages on VCNTL and VIN pins to prevent wrong logic controls. The POR function initiates a soft-start process +170oC, a thermal sensor turns off the output NMOS, allowing the device to cool down. The regulator regulates after both of the supply voltages exceed their rising POR voltage thresholds during powering on. The POR func- the output again through initiation of a new soft-start process after the junction temperature cools by 50oC, result- tion also pulls low the POK voltage regardless of the output status when one of the supply voltages falls below its falling POR voltage threshold. ing in a pulsed output during continuous thermal overload conditions. The thermal shutdown is designed with Internal Soft-Start a 50oC hysteresis to lower the average junction temperature during continuous thermal overload conditions, ex- An internal soft-start function controls rise rate of the output voltage to limit the current surge during start-up. The tending lifetime of the device. For normal operation, the device power dissipation should typical soft-start interval is about 0.6ms. be externally limited so that junction temperatures will not exceed +125οC. Output Voltage Regulation An error amplifier working with a temperature-compen- Enable Control sated 0.8V reference and an output NMOS regulates output to the preset voltage. The error amplifier is designed The APL5620 has a dedicated enable pin (EN). A logic low signal applied to this pin shuts down the output. Following a shutdown, a logic high signal re-enables the with high bandwidth and DC gain provides very fast transient response and less load regulation. It compares the reference with the feedback voltage and amplifies the dif- output through initiation of a new soft-start cycle. When left open, this pin is pulled up by an internal current source ference to drive the output NMOS which provides load current from VIN to VOUT. (5µA typical) to enable normal operation. It’s not necessary to use an external transistor to save cost. Current-Limit Protection Power-OK and Delay The APL5620 monitors the current flowing through the output NMOS and limits the maximum current to prevent The APL5620 indicates the status of the output voltage by monitoring the feedback voltage (VFB) on FB pin. As the load and APL5620 from damaging during current overload conditions. VFB rises and reaches the rising Power-OK voltage threshold (VTHPOK), an internal delay function starts to work. At the Short Current-Limit Protection The short current-limit function reduces the current-limit end of the delay time, the IC turns off the internal NMOS of the POK to indicate that the output is ok. As the VFB falls level down to 0.8A (typical) when the voltage on FB pin falls below 0.2V (typical) during current overload or short- and reaches the falling Power-OK voltage threshold, the IC turns on the NMOS of the POK ( after a debounce time circuit conditions. The short current-limit function is disabled for success- of 10µs typical ). ful start-up during soft-start. Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2009 11 www.anpec.com.tw APL5620 Application Information Power Sequencing Setting The Output Voltage The power sequencing of VIN and VCNTL is not neces- The output voltage is programmed by the resistor divider sary to be concerned. However, do not apply a voltage to VOUT for a long time when the main voltage applied at connected to FB pin. The preset output voltage is calculated by the following equation : R1 VOUT = 0.8 ⋅ 1 + R2 VIN does not present. The reason is the internal parasitic diode from VOUT to VIN conducts and dissipates power without protections due to the forward-voltage. ........... (V) where R1 is the risistor connected from VOUT to FB with Kelvin sensing connection and R2 is the risistor con- Output Capacitor nected from FB to GND. A bypass capacitor(C1) may be connected with R1 in parallel to improve load transient The APL5620 requires a proper output capacitor to maintain stability and improve transient response. The output capacitor selection is dependent upon ESR (equivalent response and stability. series resistance) and capacitance of the output capacitor over the operating temperature. Ultra-low-ESR capacitors (such as ceramic chip capacitors) and low-ESR bulk capacitors (such as solid tantalum, POSCap, and Aluminum electrolytic capacitors) can all be used as output capacitors. During load transients, the output capacitors which is depending on the stepping amplitude and slew rate of load current, are used to reduce the slew rate of the current seen by the APL5620 and help the device to minimize the variations of output voltage for good transient response. For the applications with large stepping load current, the low-ESR bulk capacitors are normally recommended. Decoupling ceramic capacitors must be placed at the load and ground pins as close as possible and the impedance of the layout must be minimized. Input Capacitor The APL5620 requires proper input capacitors to supply current surge during stepping load transients to prevent the input voltage rail from dropping. Because the parasitic inductor from the voltage sources or other bulk capacitors to the VIN pin limit the slew rate of the surge currents, more parasitic inductance needs more input capacitance. Ultra-low-ESR capacitors (such as ceramic chip capacitors) and low-ESR bulk capacitors (such as solid tantalum, POSCap, and Aluminum electrolytic capacitors can all be used as an input capacitor of VIN. For most applications, the recommended input capacitance of VIN is 10µF at least. However, if the drop of the input voltage is not cared, the input capacitance can be less than 10µF. More capacitance reduces the variations of the supply voltage on VIN pin. Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2009 12 www.anpec.com.tw APL5620 Layout Consideration (See Figure 1) 1. Please solder the Exposed Pad on the system ground Thermal Consideration pad on the top-layer of PCBs. The ground pad must have wide size to conduct heat into the ambient air The TDFN3x3-10 is a cost-effective package featuring a small size and a bottom exposed pad to minimize the through the system ground plane and PCB as a heat sink. thermal resistance of the package, being applicable to high current applications. The exposed pad must be sol- 2. Please place the input capacitors for VIN and VCNTL pins near the pins as close as possible for decoupling dered to the top-layer ground plane. It is recommended to connect the top-layer ground pad to the internal ground high-frequency ripples. 3. Ceramic decoupling capacitors for load must be placed plan by using vias. The copper of the ground plane on the top-layer conducts heat into the PCB and ambient air. near the load as close as possible for ecoupling highfrequency ripples. Please enlarge the area of the top-layer pad and the ground plane to reduce the case-to-ambient resistance 4. To place APL5620 and output capacitors near the load reduces parasitic resistance and inductance for excel- (θCA). lent load transient response. 5. The negative pins of the input and output capacitors and the GND pad must be connected to the ground plane of the load. 6. Large current paths, shown by bold lines on the figure 1, must have wide tracks. 7. Place the R1, R2, and C1 (option) near the APL5620 as close as to avoid noise coupling. 8. Connect the ground of the R2 to the GND pad by using a dedicated track. 9. Connect the one pin of the R1 to the load for Kelvin sensing. 10. Connect one pin of the C1 (option) to the VOUT pin for reliable feedback compensation. VCNTL CCNTL CIN VCNTL VIN VIN APL5620 VOUT VOUT C1 (Optional) COUT FB GND R1 Load R2 Figure 1 Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2009 13 www.anpec.com.tw APL5620 Package Information TDFN3x3-10 A b E D Pin 1 A1 D2 A3 L E2 Pin 1 Corner e S Y M B O L A A1 TDFN3x3-10 MILLIMETERS MIN. MAX. 0.70 0.00 A3 INCHES MIN. MAX. 0.80 0.028 0.031 0.05 0.000 0.002 0.012 0.20 REF 0.008 REF b 0.18 0.30 0.007 D 2.90 3.10 0.114 0.122 D2 2.20 2.70 0.087 0.106 E 2.90 3.10 0.114 0.122 E2 1.40 1.75 0.055 0.069 0.50 0.012 e 0.50 BSC L 0.30 K 0.20 0.020 BSC 0.020 0.008 Note : 1. Followed from JEDEC MO-229 VEED-5. Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2009 14 www.anpec.com.tw APL5620 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 OD1 B A B T SECTION A-A SECTION B-B H A d T1 Application TDFN3x3-10 A H T1 C d D W E1 F 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 3.30±0.20 3.30±0.20 1.30±0.20 4.0±0.10 8.0±0.10 (mm) Devices Per Unit Package Type Unit Quantity TDFN3x3-10 Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2009 15 www.anpec.com.tw APL5620 Taping Direction Information TDFN3x3-10 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2009 16 www.anpec.com.tw APL5620 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2009 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 17 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APL5620 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.2 - Jun., 2009 18 www.anpec.com.tw