DS96F172MQML,DS96F174MQML DS96F172MQML/DS96F174MQML EIA-485/EIA-422 Quad Differential Drivers Literature Number: SNOSAS8 April 28, 2011 EIA-485/EIA-422 Quad Differential Drivers General Description Features The DS96F172 and the DS96F174 are high speed quad differential line drivers designed to meet EIA-485 Standards. The DS96F172 and the DS96F174 offer improved performance due to the use of L-FAST bipolar technology. The use of LFAST technology allows the DS96F172 and DS96F174 to operate at higher speeds while minimizing power consumption. The DS96F172 and the DS96F174 have TRI-STATE® outputs and are optimized for balanced multipoint data bus transmission at rates up to 15 Mbps. The drivers have wide positive and negative common mode range for multipoint applications in noisy environments. Positive and negative current-limiting is provided which protects the drivers from line fault conditions over a +12V to −7.0V common mode range. A thermal shutdown feature is also provided. The DS96F172 features an active high and active low Enable, common to all four drivers. The DS96F174 features separate active high Enables for each driver pair. ■ ■ ■ ■ ■ ■ ■ ■ ■ Meets EIA-485 and EIA-422 standards Monotonic differential output switching TRI-STATE outputs Designed for multipoint bus transmission Common mode output voltage range: −7.0V to +12V Operates from single +5.0V supply Reduced power consumption Thermal shutdown protection DS96F172 and DS96F174 are lead and function compatible with the SN75172/174 or the AM26LS31/ MC3487 Ordering Information SMD Part Number NS Package Number DS96F172ME/883 NS Part Number 5962-9076501M2A E20A 20LD Leadless Chip Carrier Package Description DS96F172MJ/883 5962-9076501MEA J16A 16LD Ceramic Dip DS96F174ME/883 5962-9076502M2A E20A 20LD Leadless Chip Carrier DS96F174MJ/883 5962-9076502MEA J16A 16LD Ceramic Dip DS96F174MJ-QMLV 5962-9076502VEA J16A 16LD Ceramic Dip TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2011 National Semiconductor Corporation 201640 www.national.com DS96F172MQML/DS96F174MQML EIA-485/EIA-422 Quad Differential Drivers DS96F172MQML/ DS96F174MQML DS96F172MQML/DS96F174MQML Connection Diagrams 16-Lead Ceramic Dual-In-Line Package (NS Package Number J16A) DS96F172 DS96F174 20164001 20164002 Top View Top View 20-Lead Ceramic Leadless Chip Carrier (NS Package Number E20A) 20164018 20164019 Top View NC = No connection Top View www.national.com 2 DS96F172 DS96F174 20164014 20164015 DS96F174 Function Tables DS96F172 (Each Driver) Input Enable Outputs A E E Y Z H H X H L L H X L H H X L H L L X L L H X L H Z Z Input Enable A E Y Outputs H H H L L H L H X L Z Z Z H = High Level L = Low Level X = Don't Care Z = High Impedance (Off) 3 www.national.com DS96F172MQML/DS96F174MQML Logic Diagrams DS96F172MQML/DS96F174MQML Absolute Maximum Ratings (Note 1) −65°C ≤ TA ≤ +175°C 300°C Storage Temperature Range (TStg) Lead Temperature (Soldering, 60 sec.) Maximum Package Power Dissipation at 25°C (Note 2) Ceramic LCC (E) Ceramic DIP (J) Ceramic Flatpak (W) Supply Voltage Enable Input Voltage 2,000 mW 1,800 mW 1,000 mW 7.0V 5.5V Recommended Operating Conditions Min 4.50 −7.0 Supply Voltage (VCC) Common Mode Output Voltage (VOC) Output Current High (IOH) Output Current Low (IOL) Operating Temperature (TA) −55 Max 5.50 +12.0 −60 60 +125 Units V V mA mA °C Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A Subgroup Description Temp (°C) 1 Static tests at +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 10 Switching tests at +125 11 Switching tests at -55 12 Settling time at +25 13 Settling time at +125 14 Settling time at -55 www.national.com 4 AC/DC Parameters (Note 5) The following conditions apply, unless otherwise specified. DC: VCC = 5.5V AC: VCC = 5.0V Symbol Parameter Conditions VIL Logical 0 Input Voltage VIH Logical 1 Input Voltage VIC Input Clamp Voltage I = -18mA VOD1 Differential Output Voltage IO = 0mA VOD2 Differential Output Voltage VCC = 4.5V, RL = 54Ω Figure 1 VOD2 Differential Output Voltage VCC = 4.5V, RL = 100Ω Figure 1 ΔVOD1 Change In Magnitude of VOD2 VCC = 4.5V, RL = 54Ω ΔVOD2 Change In Magnitude of VOD2 VCC = 4.5V, RL = 100Ω VOC Common Mode Output Voltage VOC Notes Min Unit 0.8 V 1 0.7 V 2, 3 2.0 V 1, 2, 3 -1.5 V 1, 2, 3 6.0 (Note 3) Subgroups Max V 1, 2, 3 1.5 V 1, 2 1.2 V 3 2.0 V 1, 2, 3 (Note 6) -200 200 mV 1, 2 (Note 3, Note 6) -400 400 mV 3 (Note 6) -200 200 mV 1, 2 (Note 3, Note 6) -400 400 mV 3 RL = 54Ω Figure 1 3.0 V 1, 2, 3 Common Mode Output Voltage RL = 100Ω Figure 1 3.0 V 1, 2, 3 ΔVOC Change in Magnitude of VOC VCC = 4.5V, RL = 54Ω Figure 1 (Note 6) -200 200 mV 1, 2, 3 ΔVOC Change in Magnitude of VOC VCC = 4.5V, RL = 100Ω Figure 1 (Note 7) -200 200 mV 1, 2, 3 IO Output Current With Power Off VCC = 0V, VO = -7V to 12V -50 50 µA 1, 2, 3 IOZ High Impedance State Output Current VO = -7V to 12V -50 50 µA 1, 2, 3 IIH Logical 1 Input Current VI = 2.4V 20 µA 1, 2, 3 IIL Logical 0 Input Current VI = 0.4V µA 1, 2, 3 ICC Supply Current Outputs Enabled 50 mA 1, 2, 3 ICCX Supply Current Outputs Disabled 30 mA 1, 2, 3 IOS1 Short Circuit Output Current VO = -7V (Note 4) -250 mA 1, 2, 3 IOS2 Short Circuit Output Current VO = 0V (Note 4) -150 mA 1, 2, 3 IOS3 Short Circuit Output Current VO = VCC (Note 4) 150 mA 1, 2, 3 IOS4 Short Circuit Output Current VO = 12V (Note 4) 250 mA 1, 2, 3 tPLH Propagation Delay Lo to Hi level RL = 27Ω, CL = 15pF Figure 4 25 ns 10, 11 16 ns 9 tPHL Propagation Delay Hi to Low Level RL = 27Ω, CL = 15pF Figure 4 25 ns 10, 11 16 ns 9 SKEW Output to Output Delay Time RL = 60Ω 10 ns 10, 11 4 ns 9 tLZ Output Disable Time From Low Level RL = 110Ω, CL = 50pF Figure 6 40 ns 10, 11 25 ns 9 -50 5 www.national.com DS96F172MQML/DS96F174MQML DS96F172/DS96F174 Electrical Characteristics DS96F172MQML/DS96F174MQML Symbol Parameter Conditions Notes Min Max Unit Subgroups 10, 11 tHZ Output Disable Time From High Level RL = 110Ω, CL = 50pF Figure 5 80 ns 30 ns 9 tZL Output Enable Time to Low Level RL = 110Ω, CL = 50pF Figure 6 100 ns 10, 11 40 ns 9 tZH Output Enable Time to High Level RL = 110Ω, CL = 50pF Figure 4 40 ns 10, 11 32 ns 9 ns 10, 11 tDD Differential Output Delay Time RL = 60Ω, CL = 15pF Figure 3 30 22 ns 9 tTD Differential Output Transition Time RL = 60Ω, CL = 15pF Figure 3 40 ns 10, 11 22 ns 9 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: Above TA = 25°C, derate “E” package 13.3, “J” package 12.5, “W” package 7.1 mW/°C Note 3: −55°C limit exceeds EIA standard RS−485 specification Note 4: 0.2µF cap is connected between the output and Gnd to reduce oscillation. Note 5: All currents into the device pins are positive; all currents out of the device pins are negative. All voltages are reference to ground unless otherwise specified. Note 6: Δ|VOD| is the change in magnitude of VOD, that occurs when the input is changed between high and low levels. Note 7: Δ|VOC| is the change in magnitude of the VOC that occurs when the input is changed between high and low levels. www.national.com 6 20164013 20164003 FIGURE 2. Differential Output Voltage with Varying Common Mode Voltage FIGURE 1. Differential and Common Mode Output Voltage 20164005 20164004 FIGURE 3. Differential Output Delay and Transition Times 20164006 20164007 FIGURE 4. Propagation Delay Times 7 www.national.com DS96F172MQML/DS96F174MQML Parameter Measurement Information DS96F172MQML/DS96F174MQML 20164009 20164008 FIGURE 5. tZH and tHZ 20164011 20164010 FIGURE 6. tZL, tLZ, tLZL Note 8: The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, duty cycle = 50%, tr ≤ 5.0 ns, tf ≤ 5.0 ns, ZO = 50Ω. Note 9: CL includes probe and jig capacitance. Note 10: DS96F172 with active high and active low Enables is shown. DS96F174 has active high Enable only. Note 11: To test the active low Enable E of DS96F172 ground E and apply an inverted waveform to E . DS96F174 has active high Enable only. Note 12: For more information see Application Bulletin, Contact Product Marketing. www.national.com 8 DS96F172MQML/DS96F174MQML Typical Application 20164012 The line length should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept as short as possible. 9 www.national.com DS96F172MQML/DS96F174MQML Revision History Released Revision 8–Apr-11 A www.national.com Section Changes New Release, Corporate format 10 2 MDS data sheets converted into one Corp. data sheet format. MNDS96F172M-X Rev 1A0 & MNDS96F174M-X Rev 1B0 will be archived. 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