TI GRM32ER61E226KE15

TPS65163
www.ti.com
SLVSA28 – OCTOBER 2009
LCD Bias Supply With Integrated Level Shifters
Check for Samples :TPS65163
FEATURES
1
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8.6-V to 14.7-V Input Voltage Range
2.8-A Boost Converter Switch Current Limit
Boost Converter Output Voltages up to 18.5 V
Boost and Buck Converter Short-Circuit
Protection
1.5-A Buck Converter (3.3 V) Switch Current
Limit
Fixed 750-kHz Switching Frequency for Buck
and Boost Converters
Buck Converter and Boost Converter
Soft-Start
Two Charge-Pump Controllers to Regulate VGH
and VGL
Control Signal for External High-Side MOSFET
Isolation Switch
9-Channel Level Shifter Organized in Two
Groups of 7 and 2 Channels (Separate VGH)
Gate Shaping (Level Shifter Channels 1 to 6)
Display Panel Discharge Function
Supports VGH Voltages up to 38 V
Supports VGL Voltages Down to –13 V
Reset Signal With Programmable Reset-Pulse
Duration
Thermal Shutdown
48-Pin 7-mm × 7-mm QFN Package
In typical display panel applications, the boost
converter generates the display panel source voltage,
VS; the buck converter generates the system logic
supply, VLOGIC; and the two charge pump controllers
regulate the external charge pumps generating the
display transistors’ on and off supplies, VGH and VGL.
The level shifters transform the logic-level control
signals generated by the display timing controller into
the high-level signals needed by the LCD panel. The
nine level-shifter channels are organized in two
groups, each with its own positive supply voltage
(VGH). Each channel uses a low-impedance output
stage to achieve fast rise and fall times, even when
driving the capacitive loads present in LCD
applications. Channels 1 to 6 also support gate
voltage shaping.
The TPS65163 also provides a reset circuit that
monitors the buck converter output (VLOGIC) and
generates a reset signal for the timing controller
during power up and power down.
A control signal can also be generated to control an
external MOSFET isolation switch located between
the output of the boost converter and the display
panel.
APPLICATIONS
•
LCD TVs and Monitors Using GIP Technology
DESCRIPTION
The TPS65163 integrates a boost converter, buck
converter, reset generator, two charge pump
controllers and a nine-channel level shifter in a single
device.
Isolation Switch
Control
GD
Boost
Converter
VS
Buck
Converter
VLOGIC
Positive Charge
Pump Controller
VGH
Negative Charge
Pump Controller
VGL
Reset
Generator
RST
IN1 to IN9
Level Shifters
OUT1 to OUT9
FLK1 to FLK3
Panel Discharge
DISCH
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TPS65163
SLVSA28 – OCTOBER 2009
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
TA
ORDERING
PACKAGE
PACKAGE MARKING
–40°C to 85°C
TPS65163RGZR
48-Pin 7x7 QFN
TPS65163
The device is supplied taped and reeled, with 3000 (TBC) devices per reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
Supply voltage (2)
Input voltage (2)
Output voltage (2)
Output current
ESD rating
UNIT
VIN
–0.3 to 20
VGH1, VGH2
–0.3 to 45
VGL
0.3 to –15
FBN, FBP, FBB, FB, DLY, CRST, SS, COMP, VL, FLK1–FLK3,
IN1–IN9, VSENSE
–0.3 to 7
RST
–0.3 to 7
SWB, CTRLP, GD, SW, CTRLN
–0.3 to 20
RE
–0.3 to 45
OUT1–OUT9, DISCHARGE
–15 to 45
V
V
V
GD
1
RE
100
Human-body model
2000
V
Machine model
200
V
Charged-device model
mA
700
V
See Dissipation Table
W
Operating ambient
temperature range
–40 to 85
°C
Operating junction
temperature range
–40 to 150
°C
Storage temperature range
–65 to 150
°C
Continuous power dissipation
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
With respect to the GND and AGND pins.
DISSIPATION RATINGS
2
PACKAGE
RθJA
TA ≤ 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
48-pin QFN
36 °C/W
2.78 W
1.53 W
1.11 W
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SLVSA28 – OCTOBER 2009
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
8.6
12
14.7
V
VIN + 1
15
18.5
V
10
20
44
µF
Boost converter inductance
6.8
10
15
µH
Boost converter output capacitance
40
60
100
µF
L
Buck converter inductance
6.8
10
15
µH
COUT
Buck converter output capacitance
20
44
100
µF
TA
Operating ambient temperature
–40
25
85
°C
TJ
Operating junction temperature
–40
85
125
°C
VIN
Supply voltage range
VS
Boost converter output voltage range
CIN
Input capacitance
L
COUT
ELECTRICAL CHARACTERISTICS
VIN = 12 V; VS = 16 V; VLOGIC = 3.3 V; VGH1 = VGH2 = 30 V; VGL = –7 V; TA = –40°C to 85°C; typical values are at 25°C (unless
otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1
15
mA
7.8
8.2
8.5
V
POWER SUPPLY
IIN
Supply current
UVLO
UVLO threshold
VHYS
UVLO hysteresis
V
INTERNAL OSCILLATOR
fSW
Switching frequency
600
750
900
kHz
VOLTAGE REFERENCE
VREF
Voltage reference
1.24
V
BOOST CONVERTER
VS
Output voltage
VFB
Feedback regulation voltage
IFB
Feedback input bias current
ILIM
Switch current limit
ILEAK
Switch leakage current
VSW = 15 V
rDS(ON)
Switch ON resistance
ISW = ILIM
tSW
Switching time
Turnon and turnoff
Line regulation
9.6 V < VIN < 14.4 V, IS = 750 mA
Load regulation
VS = 17 V, IS = 100 mA to 1.5 A
VOVP
Overvoltage threshold
ISS
Soft-start capacitor charge current
VFB(SC)
Short circuit threshold
Measured after isolation switch
VIN+1
1.228
VFB = 1.24 V
2.8
VFB rising
18.5
V
1.24
1.252
V
±0.01
±1
µA
3.5
4.2
A
10
µA
0.15
0.25
10
Ω
ns
0.02
%/V
0.1
%/A
1.03 × VFB
V
11
µA
200
mV
GATE DRIVE SIGNAL
VGD
Output low voltage
IGD = 500 µA (sinking)
ILK
Leakage current
VGD = 20 V
0.05
0.5
V
1
µA
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 12 V; VS = 16 V; VLOGIC = 3.3 V; VGH1 = VGH2 = 30 V; VGL = –7 V; TA = –40°C to 85°C; typical values are at 25°C (unless
otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
3.2
3.3
MAX
UNIT
BUCK CONVERTER
VLOGIC
Output voltage
IFBB
Feedback input bias current
ILIM
Switch current limit
ILKG
Switch leakage current
rDS(on)
Switch ON resistance
tSW
Switching time
Turnon and turnoff
Line regulation
VIN = 9.6 V to 14.4 V, ILOGIC = 0.5 A
Load regulation
ILOGIC = 150 mA to 1.5 A
Short-circuit threshold
VFBB rising
VFB(SC)
VPG
Power-good threshold
tSS
Soft start time
VFBB = 3.3 V, sourcing (i.e. flowing out of IC).
1.5
2.1
VSWB = 0 V
3.4
V
125
µA
2.8
A
10
µA
Ω
0.21
10
ns
0.01
%/V
0.2
%/A
1.065
VLOGIC rising
3.2
VLOGIC falling
2.9
V
V
0.66
ms
POSITIVE CHARGE PUMP CONTROLLER
VFBP
Feedback regulation voltage
IFBP
Feedback input bias current
VFBP = 1.24 V
1.203
ICTRLP
Base drive current for external
transistor
Normal operation
ICTRLP(SC)
Base drive current for external
transistor
Short-circuit operation
Line regulation
VIN = 9.6 V to 14.4 V, VGH = 27 V, IGH = 50
mA, including external components
Load regulation
VGH = 27 V, IGH = 0 to 50 mA, including
external components
1.24
1.277
V
±10
±100
nA
5
40
mA
55
75
µA
±0.1
%/V
±1
%/A
NEGATIVE CHARGE PUMP CONTROLLER
VFBN
Feedback regulation voltage
IFBN
Feedback input bias current
VFBP = 1.24 V
ICTRLN
Base drive current for external
transistor
Normal operation
2.5
Short-circuit operation
200
ICTRLN(SC Base drive current for external
transistor
)
–36
Line regulation
VIN = 9.6 V to 14.4 V, VGL = –7 V, IGL = 50
mA, including external components
Load regulation
VGL = –7 V, IGH = 0 to 50 mA, including
external components
0
36
mV
±10
±100
nA
mA
300
480
µA
±0.1
%/V
±1
%/A
RESET GENERATOR
VOL
Output voltage low
IOL = 1 mA (sinking)
IOH
Output current high
VRST = 3.3 V
ICRST
Reset delay capacitor charge current
VCRST
Reset delay threshold voltage
0.5
V
±1
µA
10
µA
1.24
V
DELAY
IDLY
Delay capacitor charge current
VDLY
Delay threshold voltage
10
µA
1.24
V
THERMAL SHUTDOWN
TSD
Thermal shutdown threshold
150
°C
THYS
Thermal shutdown hysteresis
10
°C
4
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 12 V; VS = 16 V; VLOGIC = 3.3 V; VGH1 = VGH2 = 30 V; VGL = –7 V; TA = –40°C to 85°C; typical values are at 25°C (unless
otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.35
3
mA
0.012
1
mA
4
mA
POWER SUPPLY
IGH1
VGH1 supply current
IN1 to IN7 = VSENSE = 0 V
IGH2
VGH2 supply current
IN8 and IN9 = 0V
IGL
VGL supply current
IN1 to IN9 = VSENSE = 0 V
UVLO
Undervoltage lockout threshold
(VGH1)
VGH1 rising
VHYS
Undervoltage lockout hysteresis
(VGH1)
VGH1 falling
0.144
10.5
13.5
450
V
mV
LEVEL SHIFTERS
OUT1 to OUT7, continuous
IOUT
Output current
OUT1 to OUT7, peak
OUT8 to OUT9, DISCGARGE, continuous
OUT8 to OUT9, DISCHARGE, peak
±15
±300
±150
IN1 to IN9 = 0 V
±1
µA
IN1 to IN9 = 3.3 V
±1
µA
2
V
IIN
Input current
VIH
High level input threshold
IN1 to IN9
VIL
Low level input threshold
IN1 to IN9
0.5
OUT1 to OUT7, IOUT = –10 mA (sinking)
0.1
VDROPL
Output voltage drop low
VDROPH
Output voltage drop high
tR
Rise time
tF
Fall time
tPH
tPL
Propagation delay
mA
±15
OUT8 to OUT9, DISCHARGE, IOUT = –10 mA
(sinking)
V
0.3
0.2
1
V
OUT1 to OUT7, IOUT = 10 mA (sourcing)
0.15
0.4
V
OUT8 to OUT9, DISCHARGE, IOUT = 10 mA
(sourcing)
0.35
1
V
OUT1 to OUT7, COUT = 4.7 nF
300
520
OUT8 to OUT9, COUT = 4.7 nF
800
1200
OUT1 to OUT7, COUT = 4.7 nF
200
370
OUT8 to OUT9, COUT = 4.7 nF
500
850
Rising edge, COUT = 150 pF
60
Falling edge, COUT = 150 pF
60
ns
ns
ns
GATE VOLTAGE SHAPING
tPH
Propagation delay, gate voltage
shaping enabled
FLK falling
tSU
Set-up time
Time IN signals must be stable before falling
edge of FLK
rDS(on)
Resistance between OUT and RE
pins
Ilkg
Leakage current from RE pin
100
ns
70
ns
60
100
Ω
±1
±10
µA
DISCHARGE
VSENSE
Discharge voltage sense threshold
VSENSE falling
1.5
1.725
V
ISENSE
Discharge voltage sense current
VSENSE = 2V
1.275
±0.1
±1
µA
VHYS
Discharge voltage sense hysteresis
VSENSE rising
50
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5
TPS65163
SLVSA28 – OCTOBER 2009
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DEVICE INFORMATION
VL
VIN
VIN
PGND
PGND
SW
SW
GD
CTRLP
FBP
FB
COMP
48
47
46
45
44
43
42
41
40
39
38
37
PIN ASSIGNMENT
SWB
1
36
SS
CTRLN
2
35
CRST
FBN
3
34
DLY
FBB
4
33
AGND
RST
5
32
DISCH
Exposed
Thermal Die
31
VSENSE
30
VGH1
24
OUT4
OUT3
23
25
OUT5
12
22
IN3
OUT6
OUT2
21
26
OUT7
11
20
IN2
OUT8
OUT1
19
27
OUT9
10
18
IN1
IN9
RE
17
28
IN8
9
16
FLK3
IN7
VGH2
14
29
15
8
IN6
FLK2
13
7
IN4
FLK1
IN5
VGL
6
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
AGND
33
P
Analog ground
BOOT
48
I
Buck converter bootstrap capacitor connection
COMP
37
I
Boost converter compensation network connection.
CRST
35
I
Reset generator timing capacitor connection.
CTRLN
2
O
Base drive signal for an external transistor positive linear regulator
CTRLP
40
O
Base drive signal for an external transistor negative linear regulator
DISCH
32
I
Panel discharging connection
DLY
34
I
Positive charge pump and boost converter delay capacitor connection
FB
38
I
Boost regulator feedback. Connect this pin to the center of a resistor divider connected between the
boost converter output and AGND.
FBB
4
I
Buck converter feedback connection
FBN
3
I
Feedback pin for an external transistor positive linear regulator
FBP
39
I
Feedback pin for an external transistor negative linear regulator
FLK1
7
I
Flicker clock for level-shifter channels 1 and 4
FLK2
8
1
Flicker clock for level-shifter channels 2 and 5
FLK3
9
I
Flicker clock for level-shifter channels 3 and 6
GD
41
O
Gate drive signal for the external MOSFET isolation switch
IN1–IN7
10, 11, 12, 13,
14, 15, 16
I
Inputs for level-shifter channels 1 through 7 (connected to VGH1)
IN8–IN9
17, 18
I
Inputs for level-shifter channels 8 and 9 (connected to VGH2)
6
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PIN FUNCTIONS (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
OUT7–OUT1
21, 22, 23, 24,
25, 26, 27
O
Outputs for level-shifter channels 1 through 7 (connected to VGH1)
OUT9–OUT8
19, 20
O
Outputs for level-shifter channels 8 and 9 (connected to VGH2)
PGND
44, 45
P
Power ground
28
O
Gate shaping slope resistor connection
RST
5
O
Reset generator open-drain output
SS
36
I
Soft-start timing-capacitor connection.
SW
42, 43
O
Boost converter switching node
SWB
1
O
Buck converter switch node
VGH1
30
P
Positive supply voltage for level-shifter channels 1 through 7
VGH2
29
P
Positive supply voltage for level-shifter channels 8 and 9
VGL
6
P
Negative supply voltage for level-shifter channels 1 through 9
VIN
46, 47
P
Supply-voltage connection
31
I
Discharge sense voltage
P
Connect to the system GND
RE
VSENSE
Exposed
thermal die
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TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE NO.
BOOST CONVERTER
Efficiency
Figure 1
Load Transient Response
VIN = 12 V, VS = 15.5 V, IS = 250 mA to 750 mA
Figure 2
Line Transient Response
VIN = 11.5 V to 12.5 V, VS = 15.5 V, IS = 750 mA
Figure 3
Output Voltage Ripple
VIN = 12 V, VS = 15.5 V, IS = 500 mA
Figure 4
CCM Operation
Figure 5
DCM Operation
Figure 5
Switch Node (SW) Waveform
BUCK CONVERTER
Efficiency
Figure 7
Load Transient Response
VIN = 12 V, VLOGIC = 3.3 V, ILOGIC = 250 mA to 500 mA
Line Transient Response
VIN = 11.5 V to 12.5 V, VLOGIC = 3.3 V, ILOGIC = 500 mA
Figure 9
Output Voltage Ripple
VIN = 12 V, VLOGIC 3.3 V, ILOGIC = 500 mA
Figure 10
CCM Operation
Figure 11
DCM Operation
Figure 12
Skip Mode
Figure 13
Load Transient Response
VIN = 12 V, VGH = 26 V, IGH = 10 mA to 50 mA
Figure 14
Line Transient Response
VIN = 11.5 V to 12.5 V, VGH = 26 V, IGH = 50 mA
Figure 15
Output Voltage Ripple
VIN = 12 V, VGH = 26 V, IGH = 50 mA
Figure 16
Load Transient Response
VIN = 12 V, VGL = –7 V, IGL = 10 mA to 50 mA
Figure 17
Line Transient Response
VIN = 11.5 V to 12.5 V, VGL = –7 V, IGL = 50 mA
Figure 18
Output Voltage Ripple
VIN = 12 V, VGL = –7 V, IGL = 50 mA
Figure 19
Power-Up Sequencing
CDLY = 100 nF
Figure 20
Reset Sequencing
CDLY = 100 nF, CRST = 22 nF
Figure 21
Channels 1–7, CL = 4.7 nF, rising edge
Figure 22
Channels 1–7, CL = 4.7 nF, falling edge
Figure 23
Channels 8–9, CL = 4.7 nF, rising edge
Figure 24
Channels 8–9, CL = 4.7 nF, falling edge
Figure 25
Channels 1–7, RL = 47 Ω, CL = 10 nF, rising edge
Figure 26
Channels 1–7, RL = 47 Ω, CL = 10 nF, falling edge
Figure 27
IN to OUT, channels 1–7, CL = 150 pF, rising edge
Figure 28
IN to OUT, channels 1–7, CL = 150 pF, falling edge
Figure 29
IN to OUT, channels 8–9, CL = 150 pF, rising edge
Figure 30
IN to OUT, channels 8–9, CL = 150 pF, falling edge
Figure 31
FLK-RE, channels 1–6, CL = 150 pF, RE=1k
Figure 32
Channels 1–7, CL = 10 nF
Figure 33
Channels 8–9, CL = 10 nF
Figure 34
Power on
Figure 35
Power off
Figure 36
Switch Node (SW) Waveform
Figure 8
POSITIVE CHARGE PUMP
NEGATIVE CHARGE PUMP
START-UP SEQUENCING
LEVEL SHIFTERS
Output Rise and Fall Time
Propagation Delay
Output Current
Panel Discharge
8
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BOOST CONVERTER EFFICIENCY
BOOST CONVERTER LOAD TRANSIENT RESPONSE
IS = 250 mA TO 750 mA
100
90
VS = 15.5 V,
VGH = 26 V,
IGH = 50 mA
80
Efficiency - %
70
60
VS
50
40
30
20
IS
10
0
0
0.25
0.5
0.75
1
IO - Output Current - mA
1.25
1.5
Figure 1.
Figure 2.
BOOST CONVERTER LINE TRANSIENT RESPONSE
VIN = 11.5 V TO 12.5 V
BOOST CONVERTER OUTPUT VOLTAGE RIPPLE
IS = 500 mA
VS = 15.5 V,
IS = 750 mA,
VGH = 26 V,
IGH = 50 mA
VIN
VS
VS
VS = 15.5 V,
VGH = 26 V,
IGH = 50 mA
Figure 3.
Figure 4.
BOOST CONVERTER SWITCH NODE WAVEFORM
CONTINUOUS CONDUCTION MODE
VSW
BOOST CONVERTER SWITCH NODE WAVEFORM
DISCONTINUOUS CONDUCTION MODE
VS = 15.5 V,
IS = 50 mA
VSW
IINDUCTOR
VIN = 12 V,
IS = 250 mA
IINDUCTOR
Figure 5.
Figure 6.
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BUCK CONVERTER EFFICIENCY
BUCK CONVERTER LOAD TRANSIENT RESPONSE
ILOGIC = 250mA TO 500mA
100
90
80
Efficiency - %
70
VLOGIC
60
50
40
ILOGIC
30
20
VLOGIC = 12 V,
VGL = -7 V,
IGL = 50 mA
10
0
0
0.25
0.5
0.75
1
IO - Output Current - A
1.25
1.5
Figure 7.
Figure 8.
BUCK CONVERTER LINE TRANSIENT RESPONSE
VIN = 11.5 V TO 12.5 V
BUCK CONVERTER OUTPUT VOLTAGE RIPPLE
ILOGIC = 500 mA
VLOGIC = 3.3 V
VGL = -7 V
IGL = 50 mA
VIN
VLOGIC = 3.3 V
ILOGIC = 500 mA
VGL = -7 V
IGL = 50 mA
VLOGIC
VLOGIC
Figure 9.
Figure 10.
BUCK CONVERTER SWITCH NODE WAVEFORM
CONTINUOUS CONDUCTION MODE
BUCK CONVERTER SWITCH NODE WAVEFORM
DISCONTINUOUS CONDUCTION MODE
VLOGIC = 3.3 V
ILOGIC = 50 mA
VLOGIC = 3.3 V
ILOGIC = 250 mA
VSWB
VSWB
IINDUCTOR
IINDUCTOR
Figure 11.
10
Figure 12.
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BUCK CONVERTER SWITCH WAVEFORM
SKIP MODE
VLOGIC = 3.3 V
ILOGIC = 0 mA
POSITIVE CHARGE PUMP LOAD TRANSIENT RESPONSE
IGH = 10 mA to 50 mA
VS = 15.5 V
IS = 250 mA
VGH = 26 V
VSWB
VGH
IGH
IINDUCTOR
Figure 13.
Figure 14.
POSITIVE CHARGE PUMP LINE TRANSIENT RESPONSE
VIN = 11.5 V TO 12.5 V
POSITIVE CHARGE PUMP OUTPUT VOLTAGE RIPPLE
IGH = 50 mA
VS = 15.5 V
IS = 750 mA
VGH = 26 V
IGH = 50 mA
VIN
VS = 15.5 V
IS = 750 mA
VGH = 26 V
VGH
VS
Figure 15.
Figure 16.
NEGATIVE CHARGE PUMP LOAD TRANSIENT RESPONSE
IGL = 10 mA to 50 mA
NEGATIVE CHARGE PUMP LINE TRANSIENT RESPONSE
VIN = 11.5 V to 12.5 V
VLOGIC = 3.3 V
ILOGIC = 250 mA
VGL = -7 V
VIN
VGL
VLOGIC = 3.3 V
ILOGIC = 500 mA
VGL = -7 V
IGL = 50 mA
VGL
IGL
Figure 17.
Figure 18.
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NEGATIVE CHARGE PUMP OUTPUT VOLTAGE RIPPLE
IGL = 50 mA
VLOGIC = 3.3 V
ILOGIC = 250 mA
VGL = -7 V
POWER-UP SEQUENCING
VLOGIC
VGL
VGL
VS
VGH
Figure 19.
Figure 20.
RESET SEQUENCING
LEVEL SHIFTER OUTPUT RISE TIME
CHANNELS 1-7
VIN
VLOGIC
IN
VGL
VGH = 26 V
VGL = -7 V
COUT = 4.7 nF
tRISE = 288 ns
RESET
OUT
Figure 21.
Figure 22.
LEVEL SHIFTER OUTPUT RISE TIME
CHANNELS 8-9
LEVEL SHIFTER OUTPUT FALL TIME
CHANNELS 1-7
VGH = 26 V
VGL = -7 V
COUT = 4.7 nF
tFALL=216 ns
IN
IN
OUT
VGH = 26 V
VGL = -7 V
COUT = 4.7 nF
tRISE = 726 ns
OUT
Figure 23.
12
Figure 24.
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LEVEL SHIFTER OUTPUT FALL TIME
CHANNELS 8-9
LEVEL SHIFTER OUTPUT RISE TIME
CHANNELS 1-7
VGH = 26 V
VGL = -7 V
COUT = 4.7 nF
tFALL = 500 ns
IN
IN
OUT
VGH = 26 V
VGL = -7 V
CLOAD = 10 nF
RLOAD = 47 Ω
OUT
Figure 25.
Figure 26.
LEVEL SHIFTER OUTPUT FALL TIME
CHANNELS 1-7
LEVEL SHIFTER PROPAGATION DELAY
IN-OUT, LOW-HIGH, CHANNELS 1-7
VGH = 26 V
VGL = -7 V
CLOAD = 10 nF
RLOAD = 47 Ω
IN
OUT
IN
VGH = 26 V
VGL = -7 V
CLOAD = 150 pF
tPLH = 28.1 ns
OUT
Figure 27.
Figure 28.
LEVEL SHIFTER PROPAGATION DELAY
IN-OUT, HIGH-LOW, CHANNELS 1-7
LEVEL SHIFTER PROPAGATION DELAY
IN-OUT, LOW-HIGH, CHANNELS 8-9
IN
VGH = 26 V
VGL = -7 V
CLOAD = 150 pF
tPHL = 37.1 ns
IN
OUT
VGH = 26 V
VGL = -7 V
CLOAD = 150 pF
tPLH = 33.5 ns
OUT
Figure 29.
Figure 30.
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LEVEL SHIFTER PROPAGATION DELAY
IN-OUT, HIGH-LOW, CHANNELS 8-9
IN
VGH = 26 V
VGL = -7 V
CLOAD = 150 pF
tPHL = 38.3 ns
LEVEL SHIFTER PROPAGATION DELAY
FLK-RE, HIGH-LOW, CHANNELS 1-6
VGH = 26 V
VGL = -7 V
CLOAD = 150 pF
tPHL = 59.9 ns
RE
IN
OUT
Figure 31.
Figure 32.
LEVEL SHIFTER OUTPUT CURRENT
CHANNELS 1-7
LEVEL SHIFTER OUTPUT CURRENT
CHANNELS 8-9
VGH = 26 V
VGL = -7 V
CLOAD = 10 nF
IPK+=730 mA
IPK-=820 mA
IOUT
VGH = 26 V
VGL = -7 V
CLOAD = 10 nF
IPK+ = 248 mA
IPK- = 320 mA
IOUT
Figure 33.
Figure 34.
LEVEL SHIFTER DISCHARGE
DURING POWER-DOWN
LEVEL SHIFTER DISCHARGE
DURING POWER-UP
VIN
VIN
VDISCHARGE
VDISCHARGE
Figure 35.
14
Figure 36.
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DETAILED DESCRIPTION
GD
SW
SS
SW
VIN
LDO
VL
VL
PGND
Boost
Converter
VREF
Bandgap
PGND
OVP & SCP
Comparator
-
VIN
+
Switching
Enable
+
GD
Enable
-
CTRLP
+
FBP
+
VREF
DLY
EN
-
VREF
FB
VREF
COMP
Enable
750 kHz
Clock
Timer
VIN
VIN
CRST
EN
Timer
RST
Buck
Converter
Q
Latch
S
Enable
FBN
+
SWB
Bootstrap
Capacitor
PG
+
R
VREF
FBB
-
-
UVLO
VL
Z
CTRLN
AGND
VIN
-
VREF
UVLO
+
VGH1
FLK1
FLK2
RE
FLK3
OUT1
IN1
Gate
Shaping
IN2
OUT2
IN3
OUT3
IN4
OUT4
Level
Shifters
IN5
OUT5
IN6
OUT6
IN7
OUT7
-
VSENSE
VREF
DISCHARGE
+
VGL
VGH2
IN8
OUT8
Level
Shifter
IN9
OUT9
Figure 37. TPS65163 Internal Block Diagram
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BOOST CONVERTER
The non-synchronous boost converter uses a current-mode topology and operates at a fixed frequency of
750 kHz. The internal block diagram of the boost converter is shown in Figure 38, and a typical application circuit
in Figure 39. External compensation allows designers to optimize performance for individual applications, and is
easily implemented by connecting a suitable capacitor/resistor network between the COMP pin and AGND (see
the Boost Converter Design Procedure section for more details). The boost converter also controls a GD pin that
can be used to drive an external isolation MOSFET.
The boost converter can operate in either continuous conduction mode (CCM) or discontinuous conduction mode
(DCM), depending on the load current. At medium and high load currents, the inductor current is always greater
than zero and the converter operates in CCM; at low load currents, the inductor current is zero during part of
each switching cycle, and the converter operates in DCM. The switch node waveforms for CCM and DCM
operation are shown in Figure 5 and Figure 6. Note that the ringing seen during DCM operation occurs because
of parasitic capacitance in the PCB layout and is quite normal for DCM operation. There is very little energy
contained in the ringing waveform and it does not significantly affect EMI performance.
Equation 1 can be used to calculate the load current below which the boost converter operates in DCM.
(VS
- VI N )
´
VIN
VO UT
(1)
SW
2 ´ L ´ ¦ SW
SW
IDCM =
Current Sampling
&
Slope Compensation
VL
10µA
Current Limit
&
Soft-Start
SS
Current
Comparator
COMP
+
-
FBP
1.24V
+
Error
Amplifier
PGND
+
1.24V+3%
-
200mV
+
PGND
Overvoltage
Comparator
-
Short-Circuit
From Positive
Charge Pump
+
CTRLP
≈(VIN - 2V)
From Reset
Block
DLY
Control
Logic
Short-Circuit
Comparator
Boost Enable
Comparator
Delay
Delay
Variable
1.36ms
GD
750kHz
Oscillator
Figure 38. Boost Converter Internal Block Diagram
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VS
VIN
CIN
COUTB
COUTA
R1
SW
CFF
GD
FB
R2
COMP
SS
CSS
CCOMP
RCOMP
Figure 39. Boost Converter Typical Application Circuit
PROTECTION (BOOST CONVERTER)
The boost converter is protected against potentially damaging conditions such as overvoltage and short circuits.
An error condition is detected if the voltage on the converter's FB pin remains below 200 mV for longer than
1.36 ms, in which case the converter stops switching and is latched in the OFF condition. To resume normal
operation, the TPS65163 must be turned off and then turned on again.
Note: Because the positive charge pump is driven from its switch node, an error condition on the boost converter
output also causes the loss of VGH until the circuit recovers.
The boost converter also stops switching while the positive charge pump is in a short-circuit condition. This
condition is not latched, however, and the boost converter automatically resumes normal operation once the
short-circuit condition has been removed from the positive charge pump.
BOOST CONVERTER DESIGN PROCEDURE
Calculate Converter Duty Cycle (Boost Converter)
The simplest way to calculate the boost converter duty cycle is to use the efficiency curve in Figure 1 to
determine the converter efficiency under the anticipated load conditions and insert this value into Equation 2 (1).
Alternatively, a worst-case value (e.g., 90%) can be used for efficiency.
V ´ η
D = 1 - IN
VS
(2)
(1)
Valid only when boost converter operates in CCM.
where VS is the output voltage of the boost converter.
Calculate Maximum Output Current (Boost Converter)
The maximum output current IS that the boost converter can supply can be calculated using Equation 3. The
minimum specified output current occurs at the maximum duty cycle (which occurs at minimum VIN) and
minimum frequency (600 kHz).
æ
VIN ´ D ö
IS = ç ILIM ÷ ´ (1 - D )
2 ´ ¦SW ´ L ø
è
(3)
where ILIM is the minimum specified switch current limit (2.8 A) and ƒSW is the converter switching frequency.
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Calculate Peak Switch Current (Boost Converter)
Equation 4 can be used to calculate the peak switch current occurring in a given application. The worst-case
(maximum) peak current occurs at the minimum input voltage and maximum duty cycle.
IS
VIN ´ D
ISW(PK) =
+
1 - D 2 ´ ¦ SW ´ L
(4)
Inductor Selection (Boost Converter)
The boost converter is designed for use with inductors in the range 6.8 µH to 15 µH. A 10-µH inductor is typical.
Inductors should be capable of supporting at least 125% of the peak current calculated by Equation 4 without
saturating. This ensures sufficient margin to tolerate heavy load transients. Alternatively, a more conservative
approach can be used in which an inductor is selected whose saturation current is greater than the maximum
switch current limit (4.2 A).
Another important parameter is dc resistance, which can significantly affect the overall converter efficiency.
Physically larger inductors tend to have lower dc resistance (DCR) because they can use thicker wire. The type
and core material of the inductor can also affect efficiency, sometimes by as much as 10%. Table 1 shows some
suitable inductors.
Table 1. Boost Converter Inductor Selection
PART NUMBER
INDUCTOR VALUE
COMPONENT SUPPLIER
SIZE (L×W×H, mm)
ISAT / DCR
CDRH8D43
10 µH
Sumida
8.3 × 8.3 × 4.5
4 A / 29 mΩ
CDRH8D38
10 µH
Sumida
8.3 × 8.3 × 4
3 A / 38 mΩ
MSS 1048-103
10 µH
Coilcraft
10.5 × 10.5 × 5.1
4.8 A / 26 mΩ
744066100
10 µH
Wuerth
10 × 10 × 3.8
4 A / 28 mΩ
Rectifier Diode Selection (Boost Converter)
For highest efficiency, the rectifier diode should be a Schottky type. Its reverse voltage rating should be higher
than the maximum output voltage VS. The average rectified forward current through the diode is the same as the
output current.
ID(AVG) = IS
(5)
A Shottky diode with a 2-A average rectified current rating is adequate for most applications. Smaller diodes can
be used in applications with lower output current; however, the diode must be able to handle the power
dissipated in it, which can be calculated using Equation 6. Table 2 lists some diodes suitable for use in typical
applications.
PD = ID(AVG) ´ VF
(6)
Table 2. Boost Converter Rectifier Diode Selection
PART NUMBER
VR / IAVG
VF
RθJA
SIZE
COMPONENT SUPPLIER
MBRS320
20 V / 3 A
0.44 V at 3 A
46°C/W
SMC
International Rectifier
SL22
20 V / 2 A
0.44 V at 2 A
75°C/W
SMB
Vishay Semiconductor
SS22
20 V / 2 A
0.5 V at 2 A
75°C/W
SMB
Fairchild Semiconductor
Output Capacitance Selection (Boost Converter)
For best performance, a total output capacitance (COUTA + COUTB in Figure 39) in the range 50 µF to 100 µF is
recommended. At least 20 µF of the total output capacitance should be connected directly to the cathode of the
boost converter rectifier diode, i.e., in front of the isolation switch.
Operating the boost converter with little or no capacitance in front of the isolation switch may cause overvoltage
conditions that reduce reliability of the TPS65163.
Table 3 suggests some output capacitors suitable for use with the boost converter.
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Table 3. Boost Converter Output Capacitor Selection
PART NUMBER
VALUE / VOLTAGE RATING
COMPONENT SUPPLIER
GRM32ER61E226KE15
22 µF / 25 V
Murata
GRM31CR61E106KA12
10 µF / 25 V
Murata
UMK325BJ106MM
10 µF / 50 V
Taiyo Yuden
Setting the Output Voltage (Boost Converter)
The boost converter output voltage is programmed by a resistor divider according to Equation 7.
æ
R ö
VS = VREF ´ ç 1+ 1 ÷
è R2 ø
(7)
where VREF is the internal 1.24-V reference of the IC.
A current of the order of 100 µA through the resistor network ensures good accuracy and improves noise
immunity. A good approach is to assume a value of about 12 kΩ for the lower resistor (R2) and then select the
upper resistor (R1) to set the desired output voltage.
Compensation (Boost Converter)
Boost converter external compensation can be fine-tuned for each individual application. Recommended starting
values are 33 kΩ and 1 nF, which introduce a pole at the origin for high dc gain and a zero for good transient
response. The frequency of the zero set by the compensation components can be calculated using Equation 8.
1
¦z =
2 ´ p ´ RCOMP ´ C COMP
(8)
Selecting the Soft-Start Capacitor (Boost Converter)
The boost converter features a programmable soft-start function that ramps up the output voltage to limit the
inrush current drawn from the supply voltage. The soft-start duration is set by the capacitor connected between
the SS pin and AGND according to Equation 9.
C
´ VREF
tSS = SS
ISS
(9)
where CSS is the capacitor connected between the SS pin and GND, VREF is the internal 1.24-V reference of the
IC, and ISS is the internally generated 10-µA soft-start current.
Selecting the Isolation Switch Gate Drive Components
The isolation switch is controlled by an active-low signal generated by the GD pin. Because this signal is
open-drain, an external pullup resistor is required to turn the MOSFET switch off. If the maximum MOSFET
gate-source voltage rating is less than the maximum VIN, two resistors in series can be used to reduce the
maximum VGS applied to the device. The exact value of the gate drive resistors is not critical: 100 kΩ for both is a
good value to start with.
A capacitor can also be connected in parallel with the top resistor, as illustrated in Figure 39. The effect of this
capacitor is to slow down the speed with which the transistor turns on, thereby limiting inrush current. (Note that
the capacitor also slows down the speed with which the transistor turns off, and therefore the speed with which it
can respond to error conditions.)
Even when trying to limit inrush current, the capacitor must not be too large or the output voltage will rise so
slowly the condition will be interpreted as an error (see the Power Supply Sequencing in Detail section). Typical
values are 10 nF to 100 nF, depending on the transistor used for the isolation switch and the value of the
gate-drive resistors.
Note that even in applications that do not use an isolation switch, an external pullup resistor (typically 100 kΩ)
between GD and VIN is required.
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BUCK CONVERTER
The buck converter is a non-synchronous type that runs at a fixed frequency of 750 kHz. The converter features
integrated soft-start (0.66 ms), bootstrap, and compensation circuits to minimize external component count. The
buck converter internal block diagram is shown in Figure 40, and a typical application circuit in Figure 41.
The output voltage of the buck converter is internally programmed to 3.3 V and is enabled as soon as VIN
exceeds the UVLO threshold. For best performance, the buck converter FB pin should be connected directly to
the positive terminal of the output capacitor(s).
The buck converter can operate in either continuous conduction mode (CCM) or discontinuous conduction mode
(DCM), depending on the load current. At medium and high load currents, the inductor current is always greater
than zero and the converter operates in CCM; at low load currents, the inductor current is zero during part of
each switching cycle, and the converter operates in DCM. The switch node waveforms for CCM and DCM
operation are shown in Figure 11 and Figure 12. Note that the ringing seen during DCM operation occurs
because of parasitic capacitance in the PCB layout and is quite normal for DCM operation. However, there is
little energy contained in the ringing waveform, and it does not significantly affect EMI performance. Equation 10
can be used to calculate the load current below which the buck converter operates in DCM.
(VIN - VLOGIC ) VLOGIC
IDCM =
´
2 ´ L ´ ¦ SW
VIN
(10)
The buck converter uses a skip mode to regulate VLOGIC at low load currents. This mode allows the converter to
maintain its output at the required voltage while still meeting the requirement of a minimum on-time. The buck
converter enters skip mode when its feedback voltage exceeds the skip-mode threshold (25% above the normal
VFBB regulation voltage). During skip mode, the buck converter switches for a few cycles, then stops switching for
a few cycles, and then starts switching again, and so on, for as long as VFBB remains above the skip-mode
threshold. Output voltage ripple can be higher during skip mode (see Figure 13).
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VIN
SWB
VIN
SWB
Current Sampling
&
Slope Compensation
Bootstrap
Capacitor
VL
+
Control
Logic
Current
Comparator
+
Error
Amplifier
1.24V
OVP Pull-Up
Resistor
-
FBB
Current Limit
&
Soft-Start
Overvoltage
Comparator
+
-
Power Good
Comparator
To Reset Block
1.24V+15%
+
-
1.24V-3%
Clock/2
+
0.8V
-
Control
Logic
Clock/4
+
0.4V
-
750kHz
Oscillator
Clock Selection for Short-Circuit and Soft-Start
Figure 40. Buck Converter Internal Block Diagram
FBB
VIN
VIN
SWB
VLOGIC
Figure 41. Buck Converter Application Circuit
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PROTECTION (BUCK CONVERTER)
To protect against short-circuit conditions, the buck converter automatically limits its output current when the
voltage applied to its FBB pin is less than 1.065 V. To reduce power dissipation in the IC, the buck converter
switches at 25% of its nominal switching frequency as long as VFBB < 1.065 V. When VFBB is between 1.065 V
and 2.13 V, the buck converter switches at 50% of its nominal switching frequency.
Note: Because the negative charge pump is driven from its switch node, a short-circuit condition on the buck
converter output also causes the loss of VGL until the short circuit is removed.
An internal pullup prevents the buck converter from generating excessive output voltages if its FBB pin is left
floating.
Buck Converter Design Procedure
Because the negative charge pump is driven from the buck converter switch node, the effective output current for
design purposes is greater than ILOGIC alone. For best performance, the effective current calculated using
Equation 11 should be used during the design.
ILOGIC(EFFECTIVE) = ILOGIC +
VGL ´ IGL
VLOGIC
(11)
Calculate Converter Duty Cycle (Buck Converter)
The simplest way to calculate the converter duty cycle is to use the efficiency curve in Figure 7 to determine the
converter efficiency under the anticipated load conditions and insert this value into Equation 12 (1). Alternatively,
a worst-case value (e.g., 80%) can be used for efficiency.
V
D = LOGIC
VIN ´ η
(12)
(1)
Valid only when buck converter operates in CCM.
Calculate Maximum Output Current (Buck Converter)
The maximum output current that the buck converter can supply can be calculated using Equation 13. The
minimum specified output current occurs at the minimum duty cycle (which occurs at maximum VIN) and
maximum frequency (900 kHz).
VIN ´ (1 - D)
´ D
ILOGIC(EFFECTIVE) = ISW(LIM) 2 ´ ¦SW ´ L
(13)
Where ISW(LIM) is the minimum specified switch current limit (1.5 A) and ƒSW is the converter switching frequency.
Calculate Peak Switch Current (Buck Converter)
Equation 14 can be used to calculate the peak switch current occurring in a given application. The worst-case
(maximum) peak current occurs at maximum VIN.
VIN ´ (1 - D)
´ D
ISW(PK) = ILOGIC(EFFECTIVE) +
2 ´ ¦SW ´ L
(14)
Inductor Selection (Buck Converter)
The buck converter is designed for use with inductors in the range 6.8 µH to 15 µH, and is optimized for 10 µH.
The inductor must be capable of supporting the peak current calculated by Equation 14 without saturating.
Alternatively, a more conservative approach can be used in which an inductor is selected whose saturation
current is greater than the maximum switch current limit (2.25 A).
Another important parameter is dc resistance, which can significantly affect the overall converter efficiency.
Physically larger inductors tend to have lower dc resistance (DCR) due to the use of thicker wire. The type and
core material of the inductor can also affect efficiency, sometimes by as much as 10%. Table 4 shows some
suitable inductors.
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Table 4. Buck Converter Inductor Selection
PART NUMBER
INDUCTOR VALUE
COMPONENT SUPPLIER
SIZE (L×W×H, mm)
ISAT / DCR
CDRH8D43
10 µH
Sumida
8.3 × 8.3 × 4.5
4 A / 29 mΩ
CDRH8D38
10 µH
Sumida
8.3 × 8.3 × 4
3 A / 38 mΩ
MSS 1048-103
10 µH
Coilcraft
10.5 × 10.5 × 5.1
4.8 A / 26 mΩ
744066100
10 µH
Wuerth
10 × 10 × 3.8
4 A / 28 mΩ
Rectifier Diode Selection (Buck Converter)
To achieve good efficiency, the rectifier diode should be a Schottky type. Its reverse voltage rating should be
higher than the maximum VIN. The average rectified forward current through the diode can be calculated using
Equation 15.
IRECT(AVG) = ILOGIC(EFFECTIVE) ´ (1 - D)
(15)
A Schottky diode with a 2-A average rectified current rating is adequate for most applications. Smaller diodes can
be used in applications with lower output current; however, the diode must be able to handle the power
dissipated in it, which can be calculated using Equation 16.
PRECT = IRECT(AVG) ´ VF
(16)
Table 5. Buck Converter Rectifier Diode Selection
PART NUMBER
VR / IAVG
VF
RθJA
SIZE
COMPONENT SUPPLIER
MBRS320
20 V / 3 A
0.44 V at 3 A
46°C/W
SMC
International Rectifier
SL22
20 V / 2 A
0.44 V at 2 A
75°C/W
SMB
Vishay Semiconductor
SS22
20 V / 2 A
0.5 V at 2 A
75°C/W
SMB
Fairchild Semiconductor
Output Capacitance Selection (Buck Converter)
To minimize output voltage ripple, the output capacitors should be good-quality ceramic types with low ESR. The
buck converter is stable over a range of output capacitance values, but an output capacitance of 44 µF is a good
starting point for typical applications.
POSITIVE CHARGE PUMP CONTROLLER
The positive charge pump is driven directly from the boost converter switch node and regulated by controlling the
current through an external PNP transistor. An internal block diagram of the positive charge pump is shown in
Figure 42 and a typical application circuit in Figure 43.
During normal operation, the TPS65163 is able to provide up to 5 mA of base current and is designed to work
best with transistors whose dc gain (hFE) is between 100 and 300. The charge pump is protected against short
circuits on its output, which are detected when the voltage on the charge pump feedback pin (VFBP) is below
100 mV. During short-circuit mode, the base current available from the CTRLP pin is limited to 55 µA. Note that if
a short circuit is detected during normal operation, boost converter switching is also halted until VFBP > 100 mV.
NOTE
The emitter of the external PNP transistor should always be connected to VS, the
output of the boost converter at the output side of the isolation switch. The TPS65163
uses the CTRLP pin to sense the voltage across the isolation switch and control boost
converter start-up. Connecting the emitter of the external PNP transistor to any other
voltage (e.g., VIN) prevents proper start-up of the boost converter and positive charge
pump.
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VIN
R
R
FBB
1.65V
Short-Circuit
Mode
+
FBN
300μA
Short-Circuit
Comparator
+
-
Control
Logic
Normal
Mode
2.5mA
Error
Amplifier
CTRLN
Figure 42. Positive Charge Pump Internal Block Diagram
VS
VSW
RPULL-UP
VREF
-
CTRLP
RFLY
CFLY
+
VGH
ICTRLP
COUT
CCOLLECTOR
CFF
R1
FBP
R2
Figure 43. Positive Charge Pump Application Circuit
POSITIVE CHARGE PUMP DESIGN PROCEDURE
Setting the Output Voltage (Positive Charge Pump)
The positive charge pump output voltage is programmed by a resistor divider according to Equation 17.
æ
R ö
VGH = VREF ´ ç 1 + 1 ÷
R
è
2 ø
(17)
where VREF is the internal 1.24-V reference of the TPS65163.
Rearranging Equation 17, the values of R1 and R2 are calculated:
æ VOUT
ö
R1 = R 2 ´ ç
- 1÷
V
è REF
ø
(18)
A current of the order of 1 mA through the resistor network ensures good accuracy and increases the circuit's
immunity to noise. It also ensures a minimum load on the charge pump, which reduces output voltage ripple
under no-load conditions. A good approach is to assume a value of about 1.2 kΩ for the lower resistor (R2) and
then select the upper resistor (R1) to set the desired output voltage.
24
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Note that the maximum voltage in an application is determined by the boost converter output voltage and the
voltage drop across the diodes and PNP transistor. For a typical application in which the positive charge pump is
configured as a voltage doubler, the maximum output voltage is given by Equation 19.
VG H(MA X) = (2 ´ VS ) - (2 × VF ) - VCE
(19)
where VS is the output voltage of the boost converter, VF is the forward voltage of each diode, and VCE is the
collector-emitter voltage of the PNP transistor (recommended to be at least 1 V to avoid transistor saturation).
Selecting the Feed-Forward Capacitor (Positive Charge Pump)
To improve transient performance, a feed-forward capacitor connected across the upper feedback resistor (R1) is
recommended. The feed-forward capacitor modifies the frequency response of the feedback network by adding
the zero, which improves high frequency gain. For typical applications, a zero at 5 kHz is a good place to start, in
which case CFF can be calculated using Equation 20.
1
CFF =
2 ´ p ´ 5 kHz ´ R1
(20)
Selecting the PNP Transistor (Positive Charge Pump)
The PNP transistor used to regulate VGH should have a dc gain (hFE) of at least 100 when its collector current is
equal to the charge pump output current. The transistor should also be able to withstand voltages up to 2 × VS
across its collector-emitter junction (VCE).
The power dissipated in the transistor is given by Equation 21. The transistor must be able to dissipate this
power without its junction becoming too hot. Note that the ability to dissipate power depends on adequate PCB
thermal design.
PQ = éë(2 ´ VS ) -
(2 ´
VF ) - VGH ùû ´ IGH
(21)
where IGH is the mean (not RMS) output current drawn from the charge pump.
A pullup resistor is also required between the base and emitter of the transistor. The value of this resistor is not
critical, but it should be large enough not to divert significant current away from the base of the transistor. A
value of 100 kΩ is suitable for most applications.
Selecting the Diodes (Positive Charge Pump)
Small-signal diodes can be used for most low-current applications (<50 mA), and higher-rated diodes for
higher-power applications. The average current through the diode is equal to the output current, so that the
power dissipated in the diode is given by Equation 22.
PD = IGH ´ VF
(22)
The peak current through the diode occurs during start-up, and for a few cycles may be as high as a few
amperes. However, this condition typically lasts for <1 ms and can be tolerated by many diodes whose repetitive
current rating is much lower. The reverse voltage rating of the diodes should be equal to 2 × VS.
Table 6. Positive Charge-Pump Diode Selection
PART NUMBER
IAVG
IPK
VR
VF
BAV99W
150 mA
1 A for 1 ms
75 V
1 V at 50 mA
COMPONENT SUPPLIER
NXP
BAT54S
200 mA
600 mA for 1 s
30 V
0.8 V at 100 mA
Fairchild Semiconductor
MBR0540
500 mA
5.5 A for 8 ms
40 V
0.51 at 500 mA
Fairchild Semiconductor
Selecting the Capacitors (Positive Charge Pump)
For lowest output voltage ripple, low-ESR ceramic capacitors are recommended. The actual value is not critical,
and 1 µF to 10 µF is suitable for most applications. Larger capacitors provide better performance in applications
where large load transient currents are present.
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A flying capacitor in the range 100 nF to 1 µF is suitable for most applications. Larger values experience a
smaller voltage drop by the end of each switching cycle and allow higher output voltages and/or currents to be
achieved. Smaller values tend to be physically smaller and a bit cheaper. For best performance, it is
recommended to include a resistor of a few ohms (2 Ω is a good value to start with) in series with the flying
capacitor to limit peak currents occurring at the instant of switching.
A collector capacitor in the range 100 nF to 1 µF is suitable for most applications. Larger values are more
suitable for high-current applications but can affect stability if they are too big.
A combination of COUT = 10 µF, CFLY = 1 µF, and CCOLLECTOR = 100 nF is a good starting point for most
applications (the final values can be optimized on a case-by-case basis if necessary).
NEGATIVE CHARGE PUMP
The negative charge pump controller uses an external NPN transistor to regulate an external charge pump
circuit. The IC is optimized for use with transistors having a dc gain (hFE) in the range 100 to 300; however, it is
possible to use transistors outside this range, depending on the application requirements. Regulation of the
charge pump is achieved by using the external transistor as a controlled current source whose output depends
on the voltage applied to the FBN pin: the higher the transistor current, the greater the charge transferred to the
output during each switching cycle and therefore the higher (i.e., the more negative) the output voltage. The
internal block diagram of the negative charge pump is shown in Figure 44, and a typical application circuit in
Figure 45.
VIN
R
FBB
R
1.65V
Short-Circuit
Mode
+
FBN
300μA
Short-Circuit
Comparator
+
-
Control
Logic
Normal
Mode
2.5mA
Error
Amplifier
CTRLN
Figure 44. Negative Charge Pump Internal Block Diagram
26
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VSWB
RFLY
CFLY
-
VGL
CTRLN
+
RPULL-DOWN
ICTRLN
COUT
CCOLLECTOR
R1
FBN
R2
RFILTER
VLOGIC
CFILTER
Figure 45. Negative Charge Pump Application Circuit
The TPS65163 contains a circuit to protect the negative charge pump against short circuits on its output. A
short-circuit condition is detected as long as the FBN pin remains above 1.65 V, during which time the charge
pump output current is limited.
To ensure proper start-up under normal conditions, circuit designers should make sure the full load current is not
drawn by the load until the feedback voltage VFBN is below the short-circuit threshold voltage. The value of VGL
beyond which the negative charge pump no longer works in short-circuit mode is given by Equation 23.
R1 ö
æ
VGL(SC) = - 1.65 V ´ ç1 ÷
è R2 ø
(23)
NEGATIVE CHARGE PUMP DESIGN PROCEDURE
Setting the Output Voltage (Negative Charge Pump)
The negative charge pump output voltage is programmed by a resistor divider according to Equation 24.
R
VGL = - VLO GIC ´ 1
R2
(24)
Rearranging Equation 25, the values of R1 and R2 are calculated.
R1 = R2 ´
VGL
VLOGIC
(25)
A current of the order of 1 mA through the resistor network ensures accuracy and increases the circuit's immunity
to noise. It also ensures a minimum load on the charge pump, which reduces output voltage ripple under no-load
conditions. A good approach is to assume a value of about 3.3 kΩ for the lower resistor (R2) and then select the
upper resistor (R1) to set the desired output voltage.
Note that the maximum voltage in an application is determined by the boost converter output voltage and the
voltage drop across the diodes and NPN transistor. For a typical application in which the negative charge pump
is configured as a voltage inverter, the maximum (i.e., most negative) output voltage is given by Equation 26.
VGL(MAX) = - VIN + (2 ´ VF ) + VCE
(26)
where VF is the forward voltage of each diode and VCE is the collector-emitter voltage of the NPN transistor
(recommended to be at least 1 V to avoid transistor saturation).
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Selecting the NPN Transistor (Negative Charge Pump)
The NPN transistor used to regulate VGL should have a dc gain (hFE) of at least 100 when its collector current is
equal to the charge pump output current. The transistor should also be able to withstand voltages up to VIN
across its collector-emitter junction (VCE).
The power dissipated in the transistor is given by Equation 27. The transistor must be able to dissipate this
power without its junction becoming too hot. Note that the ability to dissipate power depends heavily on adequate
PCB thermal design.
PQ = éë V IN -
(2
´ VF ) - VGL ùû ´ IGL
(27)
where IGL is the mean (not RMS) output current drawn from the charge pump.
Selecting the Diodes (Negative Charge Pump)
Small-signal diodes can be used for most low-current applications (<50 mA) and higher-rated diodes for
higher-power applications. The average current through the diode is equal to the output current, so that the
power dissipated in the diode is given by Equation 28.
PD = IGL × VF
The peak current through the diode occurs during start-up and for a few cycles may be as high as a few
amperes. However, this condition typically lasts for <1 ms and can be tolerated by many diodes whose repetitive
current rating is much lower. The diodes' reverse voltage rating should be equal to at least 2 × VIN.
Table 7. Negative Charge Pump Diode Selection
PART NUMBER
IAVG
IPK
VR
VF
COMPONENT SUPPLIER
BAV99W
150 mA
1 A for 1 ms
75 V
1 V at 50 mA
NXP
BAT54S
200 mA
600 mA for 1 s
30 V
0.8 V at 100 mA
Fairchild Semiconductor
MBR0540
500 mA
5.5 A for 8 ms
40 V
0.51 A at 500 mA
Fairchild Semiconductor
Selecting the Capacitors (Negative Charge Pump)
For lowest output voltage ripple, low-ESR ceramic capacitors are recommended. The actual value is not critical,
and 1 µF to 10 µF is suitable for most applications. Larger capacitors provide better performance in applications
where large load transient currents are present.
A flying capacitor in the range 100 nF to 1 µF is suitable for most applications. Larger values experience a
smaller voltage drop by the end of each switching cycle and allow higher output voltages and/or currents to be
achieved. Smaller values tend to be physically smaller and a bit cheaper.
A collector capacitor in the range 100 nF to 1 µF is suitable for most applications. Larger values are more
suitable for high-current applications but can affect stability if they are too big.
A combination of COUT = 10 µF, CFLY = 1 µF, and CCOLLECTOR = 100 nF is a good starting point for most
applications (the final values can be optimized on a case-by-case basis if necessary).
POWER-SUPPLY SEQUENCING
Figure 46 shows the power-supply sequencing block diagram. The four supply rails generated by the TPS65163
turn on the following sequence: first VLOGIC, then VGL, then VGH and VS, as shown in Figure 46.
The buck converter turns on when the supply voltage exceeds the undervoltage threshold.
When the internal power-good signal of the buck converter has been asserted, the reset timer starts; after the
reset time is over, RST goes high and the negative charge pump is enabled. This sequence ensures that the
negative charge pump, which is driven by the switch node of the buck converter, does not attempt to draw
current until the T-CON is out of reset and drawing current from VLOGIC.
At the same time as the negative charge pump is enabled, an internal delay timer is started. This timer generates
a delay, after which the boost converter and positive charge pump are enabled. The delay time tDLY is
determined by the capacitor CDLY connected between the DLY pin and AGND according to Equation 29.
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tDLY =
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CDLY ´ VREF
IDLY
(29)
No special sequencing is implemented during power-down, and all power supplies are disabled if VIN falls below
VUVLO.
To Buck
Converter
OUT
UVLO
EN
Buck
PG
IN
Reset
Generator
To Negative
Charge Pump
RESET
RESET
IN
To Boost
Converter
Delay OUT
Latched
To Positive
Charge Pump
CRST
RST
DLY
Figure 46. Power Supply Sequencing Block Diagram
VIN
VLOGIC
VIN > VUVLO
VLOGIC > VPG
PG
RST
tRST
VGL
tDLY
VGH
VS
Figure 47. Power Supply Sequencing
POWER-SUPPLY SEQUENCING IN DETAIL
The detailed start-up behavior of the boost converter and positive charge pump is illustrated in Figure 48.
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RST
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tDLY
≈1ms
GD
VS
≈VIN
VS
VIN
VSW
1.24V
VFBP
100mV
VGH
TIME
Figure 48. Boost Converter and Positive Charge Pump Detailed Start-Up Behavior
The isolation switch is enabled when the GD pin goes low, tDLY seconds after RST goes high. When the isolation
switch turns on, VS rises at a rate determined by the RC network controlling the switch's gate and the amount of
capacitance on the output. The TPS65163 senses the rising VS via the CTRLP pin, and 1 ms after GD goes low
checks that VS ≈ VIN. If it is, then the boost converter is enabled. This scheme prevents the boost converter from
switching before the isolation switch is fully enabled, which could otherwise cause overvoltage conditions to
damage the switch node. If VS does not reach ≈VIN within 1 ms of the GD pin going low, the TPS65163 detects
an error condition and the boost converter is not enabled.
The positive charge pump short-circuit mode is enabled when the GD pin goes low. Although the boost converter
is not switching at this point, there is a dc path from VS to VGH, and the output ramps up as current flows into the
collector capacitor and output capacitors. When VFBP reaches 100 mV, the IC determines that no short circuit
exists, and the output current from the CTRLP pin is disabled temporarily. (If there is no significant load
connected to VGH, the output voltage remains almost constant, held up by the output capacitance; if there is a
load, the output voltage decays.) When the boost converter starts switching, normal operation of the positive
charge pump is enabled, and VGH ramps up to its programmed value. (Note that the positive charge pump
implements a soft-start characteristic that ramps the current available from the CTRLP pin over time. This causes
the collector voltage of the regulating PNP to go temporarily negative.)
RESET GENERATOR
The reset generator generates an active low signal that can used to reset the timing controller used in LCD
applications. The RST output is an open-drain type and requires an external pullup resistor. This signal is
typically pulled up to the 3.3-V supply generated by the buck converter, which also supplies the timing controller
I/O functions.
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Reset pulse timing starts when the internal power-good signal of the buck converter is asserted, and its duration
is set by the size of the capacitor connected between the CRST pin and AGND, as described by Equation 30.
´ VREF
C
tRST = RST
IRST
(30)
The duration of the reset pulse also affects power-supply sequencing, as the boost converter and positive charge
pump are not enabled until the reset pulse is finished. In applications that do not require a reset signal, the RST
pin can be left floating or tied to AGND. This does not prevent the boost converter or positive charge pump from
starting.
If the CRST pin is left open-circuit, the duration of the reset pulse is close to zero (determined only by the
parasitic capacitance present), and the boost converter and positive charge pump start up instantaneously.
Alternatively, the CRST pin can be used to enable the boost converter and charge pumps by connecting a 3.3-V
logic-level ENABLE signal via a 10-kΩ resistor, as shown in Figure 49. Using this scheme, the buck converter
starts as soon as VIN exceeds the UVLO threshold, but the negative charge pump is not enabled until ENABLE
goes high. The boost converter and positive charge pump are enabled tDLY seconds after ENABLE goes high,
where tDLY is defined by the capacitor connected to the DLY pin. The resulting power-supply sequencing is
shown in Figure 50.
TPS65163
10 kW
CRST
ENABLE
Figure 49. Using an ENABLE Signal to Control Boost Converter and Charge Pumps
VIN
VLOGIC
VIN > VUVLO
VLOGIC > VPG
ENABLE
RST
VGL
VGH
tDLY
VS
Figure 50. Power-Supply Sequencing Using an ENABLE Signal
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Undervoltage Lockout
An undervoltage lockout function inhibits the device if the supply voltage VIN is below the minimum needed for
proper operation.
Thermal Shutdown
A thermal shutdown function automatically disables all LCD bias functions if the device junction temperature
exceeds ≈150°C. The device automatically starts operating again once it has cooled down to ≈140°C.
Level Shifters and Gate Shaping
The nine level-shifter channels in the TPS65163 are divided into two groups. Channels 1 through 7 are powered
from VGH1 and VGL, channels 8 and 9 are powered from VGH2 and VGL. Channels 1 to 6 support gate shaping and
channels 7 through 9 do not. Figure 51 contains a simplified block diagram of one channel with gate voltage
shaping.
VGH1
INX
From Timing
Controller
FLKX
Q1
Channel
Control
OUTX
To LCD panel
Q2
Q3
VGL
RE
RE
Figure 51. Level Shifter Channel with Gate Voltage Shaping
On the rising edge of IN, Q1 turns on, Q2 and Q3 turn off, and OUT is driven to VGH1. On the falling edge of FLK,
Q1 turns off, Q3 is turned on, and the panel now discharges through Q3 and RE (see Figure 52). On the falling
edge of IN, Q2 turns on and Q3 turns off, and OUT is driven to VGL. This sequence is repeated in turn for each
channel.
VLOGIC
INX
GND
VLOGIC
FLKX
GND
VGH1
OUTX
VGL
Gate shaping starts on
falling edge of FLKX
Gate shaping stops on
falling edge of INX
Figure 52. Gate Voltage Shaping Timing Diagram
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The alternative configuration shown in Figure 53 can be used to define a minimum gate voltage reached during
gate voltage shaping.
VGH1
INX
From Timing
Controller
FLKX
Q1
Channel
Control
OUTX
To LCD panel
Q2
VGH1
Q3
RE1
VGL
RE
RE2
Figure 53. Alternative Gate Voltage Shaping Circuit Configuration
In this circuit, resistors RE1 and RE2 define both the rate of change of gate voltage decay and the minimum gate
voltage VMIN. Using the Thevenin equivalent, the operating parameters of Figure 53 are calculated.
RE2
VMIN = VGH1 x
RE1 + RE2
(31)
RE =
RE1 x RE2
RE1 + RE2
(32)
Flicker Clocks
The gate voltage shaping control logic in the TPS65163 allows the device to be used with one, two or three
flicker clock signals, according to the application requirements.
In six-phase applications where one signal controls gate voltage shaping for six CLK channels, the flicker clock
should be connected to FLK1 and the unused pins FLK2 and FLK3 connected to GND.
In six-phase applications where three signals control gate voltage shaping for six CLK channels, the flicker clock
for channels 1 and 4 should be connected to FLK1, the flicker clock for channels 2 and 5 connected to FLK2,
and the flicker clock for channels 3 and 6 connected to FLK3.
In four-phase applications where two signals control gate voltage shaping for four CLK channels, the flicker clock
for phases 1 and 3 should be connected to FLK1, the flicker clock for phases 2 and 4 connected to FLK2, and
the unused FLK3 pin connected to GND. The unused pins IN3 and IN6 should be connected to VLOGIC.
Alternatively, IN3 can be connected to IN2 and IN6 connected to IN5; this arrangement can simplify PCB layout.
Gate voltage shaping is started by the falling edge of the FLK signal(s), which must occur during a valid part of
the clock waveform. For six-phase systems, this means the last 60° of the clock waveform; for four-phase
systems, this means the last 90° of the clock waveform (see Figure 54 and Figure 55). Falling edges of the FLK
signal(s) occurring outside the valid part of the clock waveform are ignored. The rising edge of the FLK signal(s)
has no effect, regardless of when it occurs.
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IN1
IN2
IN3
IN4
IN5
IN6
Figure 54. FLK Falling Edge Validity, Six-Phase Applications
IN1
IN2
IN3
IN4
IN5
IN6
Figure 55. FLK Falling Edge Validity, Four-Phase Applications
Level Shifters Without Gate Voltage Shaping
Channels 7 through 9 do not support gate voltage shaping and are controlled only by the logic level applied to
their INx pin. Figure 56 contains a block diagram of a channel that does not support gate voltage shaping.
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VGH1
Q1
From Timing
Controller
INX
OUTX
Channel
Control
To LCD panel
Q2
VGL
Figure 56. Block Diagram of Level Shifter Without Gate Voltage Shaping
Panel Discharge
The TPS65163 contains a function for discharging the display panel during power down. The discharge function
comprises a comparator and a level shifter (see Figure 57). During normal operation, the voltage applied to the
VSENSE pin is greater than VREF, the output of the level shifter is low, and the DISCHARGE signal is at VGL.
During power down, when the voltage applied to the VSENSE pin falls below VREF, the level shifter output goes
high and the DISCHARGE signal tracks VGH1 as it discharges (see Figure 35 and Figure 36).
VX
VGH1
R1
VSENSE
1.5V
DISCHARGE
+
R2
VGL
Figure 57. Panel Discharge Function Block Diagram
Suitable values for resistors R1 and R2 in Figure 57 are calculated using Equation 33.
æ V
ö
R1 = R2 x ç X - 1÷
1.5V
è
ø
(33)
where VX is the voltage used to activate/deactivate the discharge function.
For most applications, a value between 1 kΩ and 10 kΩ for R2 can be used (R1 depends on the value of R2 and
the value of VX).
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APPLICATION INFORMATION
SW
SL22
10µH
Si2307
33k
VS (15.6V @ 1.5A)
30µF
100k
100k
SW
1nF
30µF
SW
44µF
10nF
(12V) VIN
COMP
VIN
VIN
15k
GD
FB
1.3k
DLY
22nF
SS
22nF
CRST
RST
RST
100nF
2R
100nF
10µF
VGL
MMBT22222A
VGH1
VS
100k
100nF
2.4k
VLOGIC
VLOGIC (3.3V @ 1.5A)
FLK1
FLK2
FLK2
FLK3
FLK3
MMBT2907A
100k
CTRLN
FLK1
44µF
SL22
VGH2
FBN
100nF
10µH
SWB
VL
SWB
BAT54S
5.1k
FBB
100nF
SW
CTRLP
BAT54S
100nF
100nF
10µF
20k
FBP
1k
10k
VSENSE
10k
DISCH
DISCH
OUT1
OUT1
IN2
OUT2
OUT2
IN3
OUT3
OUT3
IN4
IN4
OUT4
OUT4
IN5
IN5
OUT5
OUT5
IN6
IN6
OUT6
OUT6
IN7
IN7
OUT7
OUT7
IN8
IN8
OUT8
OUT8
IN9
IN9
OUT9
OUT9
IN1
IN1
IN2
IN3
PGND
PGND
RE
1k
AGND
Figure 58. Typical LCD Bias Application Circuit
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PACKAGE OPTION ADDENDUM
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3-Dec-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
TPS65163RGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Request Free Samples
TPS65163RGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Purchase Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS65163RGZR
Package Package Pins
Type Drawing
VQFN
RGZ
48
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
7.3
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
7.3
1.5
12.0
16.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS65163RGZR
VQFN
RGZ
48
2500
367.0
367.0
38.0
Pack Materials-Page 2
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