AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
Document No: AX88772_07/6/21/05
Features
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Single chip USB to 10/100 Fast Ethernet and
HomePNA and HomePlug Network Controller
Integrates on-chip 10/100Mbps Fast Ethernet PHY
USB specification 1.0 and 1.1 and 2.0 compliant
Supports USB Full and High Speed modes with Bus
power capability
Supports 4 endpoints on USB interface
High performance packet transfer rate over USB
bus using proprietary burst transfer mechanism
(submitted for US patent application)
IEEE 802.3 10BASE-T and 100BASE-TX
compatible
Embedded 20KB SRAM for RX packet buffering
and 8KB SRAM for TX packet buffering
Supports both full-duplex and half-duplex
operation in Fast Ethernet
Provides optional MII interface for Ethernet PHY
and HomePNA/ HomePlug PHY interface
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Supports Suspend mode and Remote Wakeup via
Link-up, Magic packet, or external pin
Optional PHY power down during Suspend mode
Supports 256/512 bytes (93c56/93c66) of serial
EEPROM (for storing USB Descriptors)
Supports automatic loading of Ethernet ID, USB
Descriptors and Adapter Configuration from
EEPROM after power-on initialization
External PHY loop-back diagnostic capability
Integrates on-chip 3.3V to 2.5V voltage regulator
and requires only single power supply: 3.3V
Small form factor with 128-pin LQFP package
12MHz and 25Mhz clock input from either crystal
or oscillator source
Operating temperature range: 0°C to 70°C.
*IEEE is a registered trademark of the Institute of Electrical and
Electronic Engineers, Inc.
*All other trademarks and registered trademark are the property of their
respective holders.
Product Description
The AX88772 USB to 10/100 Fast Ethernet/HomePNA/HomePlug controller is a high performance and highly integrated
ASIC with embedded 28KB SRAM for packet buffering. It enables low cost and affordable Fast Ethernet network
connection to desktop, notebook PC, and embedded system using popular USB ports. It has an USB interface to
communicate with USB host controller and is compliant with USB specification V1.0, V1.1 and V2.0. It implements
10/100Mbps Ethernet LAN function based on IEEE802.3, and IEEE802.3u standards or HomePNA standard. It
integrates an on-chip 10/100Mbps Ethernet PHY to simplify system design and provides an optional media-independent
interface (MII) for implementing Fast Ethernet and HomePNA functions.
System Block Diagram
RJ11
RJ45
Magnetic
Magnetic
RJ45
10/100 PHY (FX)
Magnetic
Home LAN PHY
AX88772
EEPROM
USB I/F
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No
liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
4F, NO.8, Hsin Ann Rd., Science-Based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
FAX: 886-3-579-9558
TEL: 886-3-579-9500
Released Date: 6/21/2005
http://www.asix.com.tw/
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
Table of Contents
1.0
1.1
1.2
1.3
INTRODUCTION ................................................................................................................4
GENERAL DESCRIPTION ...........................................................................................................4
AX88772 BLOCK DIAGRAM ....................................................................................................4
AX88772 PINOUT DIAGRAM ...................................................................................................5
2.0
SIGNAL DESCRIPTION ....................................................................................................6
3.0
FUNCTION DESCRIPTION ............................................................................................10
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
4.0
4.1
5.0
5.1
5.2
5.3
6.0
USB CORE AND INTERFACE ..................................................................................................10
10/100 ETHERNET PHY.........................................................................................................10
MAC CORE ...........................................................................................................................10
STATION MANAGEMENT (STA).............................................................................................10
MEMORY ARBITER ................................................................................................................11
USB TO ETHERNET BRIDGE...................................................................................................11
SERIAL EEPROM LOADER ...................................................................................................11
GENERAL PURPOSE I/O..........................................................................................................11
SERIAL EEPROM MEMORY MAP...............................................................................12
DETAILED DESCRIPTION ........................................................................................................13
USB CONFIGURATION STRUCTURE .........................................................................16
USB CONFIGURATION ...........................................................................................................16
USB INTERFACE ....................................................................................................................16
USB ENDPOINTS ...................................................................................................................16
USB COMMANDS .............................................................................................................17
6.1 USB STANDARD COMMANDS ................................................................................................17
6.2 USB VENDOR COMMANDS ....................................................................................................18
6.2.1 DETAILED REGISTER DESCRIPTION ....................................................................................19
6.2.2 REMOTE WAKEUP DESCRIPTION ........................................................................................27
6.3 INTERRUPT ENDPOINT ...........................................................................................................27
7.0
EMBEDDED ETHERNET PHY REGISTER DESCRIPTION ....................................28
7.1 DETAILED REGISTER DESCRIPTION........................................................................................28
7.1.1 BASIC MODE CONTROL REGISTER (BMCR) ......................................................................28
7.1.2 BASIC MODE STATUS REGISTER (BMSR) ..........................................................................29
7.1.3 PHY IDENTIFIER REGISTER 1 .............................................................................................30
7.1.4 PHY IDENTIFIER REGISTER 2 .............................................................................................30
7.1.5 AUTO NEGOTIATION ADVERTISEMENT REGISTER (ANAR) ...............................................30
7.1.6 AUTO NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR) ................................31
7.1.7 AUTO NEGOTIATION EXPANSION REGISTER (ANER).........................................................31
8.0
ELECTRICAL SPECIFICATIONS .................................................................................33
8.1 DC CHARACTERISTICS...........................................................................................................33
8.1.1 ABSOLUTE MAXIMUM RATINGS .........................................................................................33
8.1.2 RECOMMENDED OPERATING CONDITION ...........................................................................33
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ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
8.1.3 LEAKAGE CURRENT AND CAPACITANCE ............................................................................33
8.1.4 DC CHARACTERISTICS OF 2.5V I/O PINS ...........................................................................34
8.1.5 DC CHARACTERISTICS OF 3.3V I/O PINS ...........................................................................34
8.2 POWER CONSUMPTION...........................................................................................................34
8.3 POWER-UP SEQUENCE............................................................................................................35
8.4 AC TIMING CHARACTERISTICS ..............................................................................................35
8.4.1 CLOCK TIMING ...................................................................................................................35
8.4.2 RESET TIMING ....................................................................................................................36
8.4.3 MII TIMING (100MBPS) .....................................................................................................36
8.4.4 STATION MANAGEMENT TIMING ........................................................................................37
8.4.5 SERIAL EEPROM TIMING..................................................................................................38
9.0
10.0
PACKAGE INFORMATION............................................................................................39
ORDERING INFORMATION ......................................................................................40
APPENDIX A: SYSTEM APPLICATIONS .................................................................................41
A.1 USB TO FAST ETHERNET CONVERTER .....................................................................................41
A.2 USB TO FAST ETHERNET AND/OR HOMELAN COMBO SOLUTION ............................................41
REVISION HISTORY ....................................................................................................................42
List of Figures
FIGURE 1: AX88772 BLOCK DIAGRAM ................................................................................................4
FIGURE 2: AX88772 PINOUT DIAGRAM................................................................................................5
FIGURE 3: INTERNAL DATAPATH DIAGRAM OF 10/100 ETHERNET PHY AND MII INTERFACE ...........10
FIGURE 4: INTERNAL CONTROL MUX FOR STATION MANAGEMENT INTERFACE .................................11
FIGURE 5: MULTICAST FILTER EXAMPLE ............................................................................................23
List of Tables
TABLE 1: PINOUT DESCRIPTION ............................................................................................................6
TABLE 2: SERIAL EEPROM MEMORY MAP .......................................................................................12
TABLE 3: USB STANDARD COMMAND REGISTER MAP.......................................................................17
TABLE 4: USB VENDOR COMMAND REGISTER MAP ..........................................................................18
TABLE 5: REMOTE WAKEUP TRUTH TABLE ........................................................................................27
TABLE 6: EMBEDDED ETHERNET PHY REGISTER MAP ........................................................................28
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ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
1.0 Introduction
1.1 General Description
The AX88772 USB to 10/100 Fast Ethernet/HomePNA/HomePlug controller is a high performance and highly integrated
ASIC with embedded 28KB SRAM for packet buffering. It enables low cost and affordable Fast Ethernet network
connection to desktop, notebook PC, and embedded system using popular USB ports. It has an USB interface to
communicate with USB host controller and is compliant with USB specification V1.0, V1.1 and V2.0. It implements
10/100Mbps Ethernet LAN function based on IEEE802.3, and IEEE802.3u standards or HomePNA standard. It
integrates an on-chip 10/100Mbps Ethernet PHY to simplify system design and provides an optional media-independent
interface (MII) for implementing Fast Ethernet and HomePNA functions.
The AX88772 needs 12MHz clock for USB operation and 25Mhz clock for Fast Ethernet operation. It is in 128-pin LQFP
low profile package with CMOS process and requires only single 3.3V power supply to operate.
1.2 AX88772 Block Diagram
Memory Arbiter
28KB
SRAM
EECS
EECK
EEDI
EEDO
GPIO2~0
SEEPROM
Loader I/F
General
Purpose I/O
USB to
Ethernet
Bridge
10/100
Ethernet
PHY
RXIP/RXIN
TXOP/TXON
MAC
Core
MII I/F
STA
MDC
MDIO
USB Core and Interface
DP/DM
DPRS/DMRS
Figure 1: AX88772 Block Diagram
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ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
1.3 AX88772 Pinout Diagram
The AX88772 is housed in the 128-pin LQFP package.
76
75
74
73
72
71
70
RSTPB
77
79
AVDDK
78
81
AGND
80
82
AGND
AVDDK
83
84
NC
85
NC
NC
NC
VDDK
GND
NC
86
NC
88 87
NC
89
NC
VDD2
90
GND
TXD3
TXD2
91
TXD1
TXD0
92
VDD2
GND
93
TX_ER
TX_EN
94
NC
NC
95
RX_LED
COL_LED
LINK_LED
FDX_LED
ET_SPEED_LED
96
69
68
66
65
67
97
64
98
63
99
62
100
61
DB4
TX_CLK
101
60
102
59
NC
RX_CLK
103
58
104
57
RX_DV
RX_ER
105
56
106
55
RXD0
RXD1
107
54
108
53
RXD2
RXD3
109
52
110
51
DB3
DB2
111
50
DB1
DB0
113
CRS
COL
115
MDINT
VDDK
117
44
118
43
GND
MDIO
119
42
120
41
MDC
PHYRST_N
121
40
122
39
VDD2
GND
123
38
124
37
LED
USB_SPEED_LED
125
36
126
35
GND
VDD3
127
34
128
33
VDD3
GND
VDDK
GND
ASIX
AX88772
112
114
49
48
47
46
116
45
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30 31
32
AVDDK
AGND
TXOP
TXON
AGND
XIN25M
XOUT25M
AVDDK
IBREF
AGND
AGND
AVDDK
RXIP
RXIN
AGND
AVDDK
NC
NC
CLKSEL
CLK60EXT
SCAN_ENABLE
SCAN_TEST
HS_TEST_MODE
VDD3
GND
AVDD3
AGND
AVDD3
DPRS
DMRS
RPU
AGND
DP
RREF
DM
AGND
AVDD3
XOUT12M
XIN12M
GND
VDDK
GNDAH
VDDAH
V25
INT_REGULATOR_EN
VDD3
GND
GND
VDDK
FORCEFS_N
NC
TESTSPEEDUP
RESET_N
EXTWAKEUP_N
VBUS
EEDO
VDD3
GND
EEDI
EECS
EECK
GPIO0
GPIO1
GPIO2
Figure 2: AX88772 Pinout Diagram
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ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
2.0 Signal Description
The following abbreviations apply to the following pin description table.
I2
I3
I5
O2
O3
O5
B
Input, 2.5V with 3.3V tolerant
Input, 3.3V
Input, 3.3V with 5V tolerant
Output, 2.5V with 3.3V tolerant
Output, 3.3V
Output, 3.3V with 5V tolerant
Bi-directional I/O
B2
B5
PU
PD
P
S
Bi-directional I/O, 2.5V with 3.3V tolerant
Bi-directional I/O, 3.3V with 5V tolerant
Internal Pull Up (75K)
Internal Pull Down (75K)
Power Pin
Schmitt Trigger
Table 1: Pinout Description
Pin Name
DP
DM
DPRS
DMRS
VBUS
XIN12M
XOUT12M
RREF
RPU
MDC
MDIO
MDINT
RX_CLK
RXD [3:0]
RX_DV
RX_ER
COL
Type
Pin No
Pin Description
USB Interface
B
32
USB 2.0 data positive pin.
B
31
USB 2.0 data negative pin.
B
36
USB 1.1 data positive pin. Please connect to DP through a 39ohm
(+/-1%) serial resistor.
B
35
USB 1.1 data negative pin. Please connect to DM through a 39ohm
(+/-1%) serial resistor.
I5/PD/S
10
VBUS pin input. Please connect to USB bus power.
I3
26
12Mhz crystal or oscillator clock input. This clock is needed for USB
PHY transceiver to operate.
O3
27
12Mhz crystal or oscillator clock output.
I
30
For USB PHY’s internal biasing. Please connect to AGND through a
12.1Kohm (+/-1%) resistor.
I
34
For USB PHY’s internal biasing. Please connect to AVDD3 (3.3V)
through a 1.5Kohm (+/-5%) resistor.
Station Management Interface
O2
121
Station Management Data Clock output. The timing reference for
MDIO. All data transfers on MDIO are synchronized to the rising edge
of this clock. The frequency of MDC is 1.5MHz.
B2/PU
120
Station Management Data Input/Output. Serial data input/output
transfers from/to the PHYs. The transfer protocol conforms to the
IEEE 802.3u MII spec.
I2/PU
117
Station Management Interrupt input.
MII Interface
I2
104
Receive Clock. RX_CLK is received from PHY to provide timing
reference for the transfer of RXD [7:0], RX_DV, and RX_ER signals
on receive direction of MII interface.
I2
110, 109, Receive Data. RXD [3:0] is driven synchronously with respect to
108, 107 RX_CLK by PHY.
I2
105
Receive Data Valid. RX_DV is driven synchronously with respect to
RX_CLK by PHY. It is asserted high when valid data is present on
RXD [3:0].
I2
106
Receive Error. RX_ER is driven synchronously with respect to
RX_CLK by PHY. It is asserted high for one or more RX_CLK
periods to indicate to the MAC that an error has detected.
I2
116
Collision Detected. COL is driven high by PHY when the collision is
detected.
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ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
CRS
I2
TX_CLK
I2
TXD [3:0]
O2
TX_EN
O2
TX_ER
O2
EECK
O5
EECS
O5
EEDI
O5
EEDO
I5/PD
XIN25M
I3
XOUT25M
RSTPB
O3
I
RXIP
I
RXIN
I
TXOP
O
TXON
O
IBREF
B
RX_LED
O3
COL_LED
O3
LINK_LED
O3
FDX_LED
O3
ET_SPEED_LED
O3
115
Carrier Sense. CRS is asserted high asynchronously by the PHY when
either transmit or receive medium is non-idle.
102
Transmit Clock. TX_CLK is received from PHY to provide timing
reference for the transfer of TXD [3:0], TX_EN and TX_ER signals
on transmit direction of MII interface.
82, 83, 84, Transmit Data. TXD [3:0] is transitioned synchronously with respect
85
to the rising edge of TX_CLK.
89
Transmit Enable. TX_EN is transitioned synchronously with respect
to the rising edge of TX_CLK. TX_EN is asserted high to indicate a
valid TXD [3:0].
88
Transmit Coding Error. TX_ER is transitioned synchronously with
respect to the rising edge of TX_CLK. When asserted high for one or
more TX_CLK, the PHY shall emit one or more code-groups that are
not part of the valid data or delimiter set somewhere in the frame
being transmitted.
Serial EEPROM Interface
4
EEPROM Clock. EECK is an output clock to EEPROM to provide
timing reference for the transfer of EECS, EEDI, and EEDO signals.
5
EEPROM Chip Select. EECS is asserted high synchronously with
respect to rising edge of EECK as chip select signal.
6
EEPROM Data In. EEDI is the serial output data to EEPROM’s data
input pin and is synchronous with respect to the rising edge of EECK.
9
EEPROM Data Out. EEDO is the serial input data from EEPROM’s
data output pin.
Ethernet Phy Interface
59
25Mhz crystal or oscillator clock input. This clock is needed for the
embedded 10/100 Ethernet PHY to operate.
58
25Mhz crystal or oscillator clock input.
65
Reset input of embedded Ethernet PHY: RSTPB is an active low input
used for resetting internal Ethernet PHY. When internal Ethernet
PHY is used, user can connect this pin to an external RC circuit,
which gets pulled-up to AVDDK (2.5V). The reset period from 50ms
to 150ms is recommended.
52
Receive data input positive pin for both 10BASE-T and
100BASE-TX.
51
Receive data input negative pin for both 10BASE-T and
100BASE-TX.
62
Transmit data output positive pin for both 10BASE-T and 100
BASE-TX
61
Transmit data output negative pin for both 10BASE-T and 100
BASE-TX
56
For Ethernet PHY’s internal biasing. Please connect to GND through
a 12.3Kohm resistor.
92
Receive activity LED indicator. This pin drives low and high in turn
(blinking) when Ethernet PHY is receiving and drives high when not
receiving.
93
Collision detected LED indicator. This pin drives low when the
Ethernet PHY detects collision and drives high when no collision.
94
Link status LED indicator. This pin drives low continuously when the
Ethernet link is up and drives low and high in turn (blinking) when
Ethernet PHY is in receiving or transmitting state.
95
Full-Duplex LED indicator. This pin drives low when the Ethernet
PHY is in full-duplex mode and drives high when in half duplex
mode.
96
Ethernet speed LED indicator. This pin drives low when the Ethernet
PHY is in 100BASE-TX mode and drives high when in 10BASE-T
mode.
Misc. Pins
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ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
RESET_N
I5/PU/S
EXTWAKEUP_N I5/PU/S
GPIO [2:0]
B5/PD
PHYRST_N
O2
FORCEFS_N
I3/PU
LED
O3
USB_SPEED_LE
D
O3
TESTSPEEDUP
HS_TEST_MODE
SCAN_TEST
SCAN_ENABLE
CLK60EXT
CLKSEL
DB [4:0]
I3/PD
I3/PD
I3/PD
I3/PD
I3/PD
I3/PD
I2
INT_REGULATO
R_EN
I
VDDAH
GNDAH
V25
P
P
P
VDDK
P
VDD2
VDD3
P
P
GND
P
AVDDK
P
AVDD3
P
12
Chip Reset Input. RESET_N pin is active low. When asserted, it puts
the entire chip into reset state immediately. After completing reset,
EEPROM data will be loaded automatically.
11
Remote-wakeup trigger from external pin. EXTWAKEUP_N should
be asserted low for more than 2 cycles of 12MHz clock to be
effective. For
1, 2, 3 General Purpose Input/ Output Pins. These pins are default as input
pins after power-on reset. Please use GPIO0 for controlling the power
down pin of external Ethernet Phy, if applicable.
122
PHYRST_N is a tri-state output used for resetting external Ethernet
PHY. This pin is default in tri-state after power-on reset. If external
Ethernet PHY’s reset level is active low, connect this to PHY’s reset
pin with a pulled-down resistor. If it’s active high, connect this to
PHY with a pulled-up resistor. This way can make sure the external
Ethernet PHY stays in reset state before software brings it out of reset.
15
Force USB Full Speed (active low). For normal operation, user should
keep this pin NC to enable USB High Speed handshaking process to
decide the speed of USB bus. Setting this pin low sets the device to
operate at Full speed mode only and disables Chirp K (HS
handshaking process).
125
LED indicator: When USB bus is in Full speed, this pin drives high
continuously. When USB bus is in High speed, this pin drives low
continuously. This pin drives high and low in turn (blinking) to
indicate TX data transfer going on whenever the host controller sends
bulk out data transfer.
126
USB bus speed LED indicator. When USB bus is in Full speed, this
pin drives high continuously. When USB bus is in High speed, this
pin drives low continuously.
13
Test pin. For normal operation, user should keep this pin NC.
42
Test pin. For normal operation, user should keep this pin NC.
43
Test pin. For normal operation, user should keep this pin NC.
44
Test pin. For normal operation, user should keep this pin NC.
45
Test pin. For normal operation, user should keep this pin NC.
46
Test pin. For normal operation, user should keep this pin NC.
101, 111, Debug pins. For normal operation, user should set these pins low.
112, 113,
114
On-chip Regulator Pins
20
On-chip 3.3V to 2.5V voltage regulator enable. Connect this pin to
VDDAH directly to enable on-chip regulator. Connect this pin to
GNDAH to disable on-chip regulator.
22
3.3V Power supply to on-chip 3.3V to 2.5V voltage regulator.
23
Ground pin of on-chip 3.3V to 2.5V voltage regulator.
21
2.5V voltage output of on-chip 3.3V to 2.5V voltage regulator.
Power and Ground Pins
16, 24, 74, Digital Core Power. 2.5V.
99, 118
80, 86, 123 Digital I/O Power. 2.5V.
8, 19, 41, Digital I/O Power. 3.3V.
97, 128
7, 17, 18, Digital Ground.
25, 40, 75,
81, 87, 98,
100, 119,
124, 127
49, 53, 57, Analog Core Power. 2.5V.
64, 66, 68
28, 37, 39 Analog I/O Power. 3.3V.
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ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
AGND
P
29, 33, 38, Analog Ground.
50, 54, 55,
60, 63, 67,
69
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ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
3.0 Function Description
3.1 USB Core and Interface
The USB core and interface contains an USB 2.0 transceiver, serial interface engine (SIE), USB bus protocol
handshaking block, USB standard command, vendor command registers, logic for supporting bulk transfer, and interrupt
transfer, etc. The USB interface is used to communicate with USB host controller and is compliant with USB
specification V1.0, V1.1 and V2.0.
3.2 10/100 Ethernet PHY
The 10/100 Fast Ethernet PHY is compliant with IEEE 802.3 and IEEE 802.3u standards. It contains an on-chip crystal
oscillator, PLL-based clock multiplier, digital phase-locked loop for data/timing recovery. It provides over-sampling
mixed-signal transmit drivers complying with 10/100BASE-TX transmit wave shaping / slew rate control requirements.
It has robust mixed-signal loop adaptive equalizer for receiving signal recovery. It contains baseline wander corrective
block to compensate data dependent offset due to AC coupling transformers. It supports auto-negotiation and has
multi-function LED outputs.
3.3 MAC Core
The MAC core supports 802.3 and 802.3u MAC sub-layer functions, such as basic MAC frame receive and transmit,
CRC checking and generation, filtering, forwarding, flow-control in full-duplex mode, and collision-detection and
handling in half-duplex mode, etc. It provides a media-independent interface (MII) for implementing Fast Ethernet and
HomePNA functions.
The MAC core interfaces to both external MII interface I/O pins and MII interface of the embedded 10/100 Ethernet
PHY. The selection between the two MII interfaces is done via USB vendor command, Software PHY Select register.
Figure 3 shows the datapath diagram of 10/100 Ethernet PHY and MII interface to MAC core.
RX
10/100
Ethernet PHY
MAC
Core
RXIP/RXIN
TXOP/TXON
MII Interface I/O:
RX_CLK, RXD [3:0], RX_DV,
RX_ER, COL, CRS
TX
TX_CLK, TXD [3:0], TX_EN, TX_ER
Figure 3: Internal Datapath Diagram of 10/100 Ethernet PHY and MII Interface
3.4 Station Management (STA)
The station management interface provides a simple, two-wire, serial interface to connect to a managed PHY device for
the purposes of controlling the PHY and gathering status from the PHY. The station management interface allows
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ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
communicating with multiple PHY devices at the same time by identifying the managed PHY with 5-bit, unique Phy ID.
The Phy ID of the embedded 10/100 Ethernet PHY is being pre-assigned to “1_0000”.
Figure 4 shows the internal control mux for the station management interface. When doing read, the “mdin” signal will be
driven from 10/100 Ethernet PHY only if Phy ID matches with “1_0000”, otherwise, it will always be driven from
external MDIO pin of the ASIC.
10/100 Ethernet
PHY
Phy ID = 1_0000
MDC
mdout
STA
MDIO
mdin
Figure 4: Internal Control Mux for Station Management Interface
3.5 Memory Arbiter
The memory arbiter block is responsible for storing received MAC frames into on-chip SRAM (packet buffer) and then
forwarding to USB bus upon request from USB host via bulk in transfer. It also monitors packet buffer usage in
full-duplex mode for triggering PAUSE frame transmission out on TX direction. The memory arbiter block is also
responsible for storing MAC frames received from USB host via bulk out transfer and waiting to be transmitted out
towards Ethernet network.
3.6 USB to Ethernet Bridge
The USB to Ethernet bridge block is responsible for converting Ethernet MAC frame into USB packets or vice-versa.
This block supports proprietary burst transfer mechanism (submitted for US patent application) to offload software
burden and to offer very high packet transfer throughput over USB bus.
3.7 Serial EEPROM Loader
The serial EEPROM loader is responsible for reading configuration data automatically from external serial EEPROM
after power-on reset.
3.8 General Purpose I/O
There are 3 general purpose I/O pins provided by this ASIC.
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AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
4.0 Serial EEPROM Memory Map
EEPROM
OFFSET
00H
HIGH BYTE
LOW BYTE
Reserved
Word Count For Preload
01H
Flag
02H
Length of High-Speed Device Descriptor (bytes)
EEPROM Offset of High-Speed Device Descriptor
03H
04H
Length of High-Speed Configuration Descriptor
(bytes)
Node ID 1
EEPROM Offset of High-Speed Configuration
Descriptor
Node ID 0
05H
Node ID 3
Node ID 2
06H
Node ID 5
Node ID 4
07H
Language ID High Byte
Language ID Low Byte
08H
Length of Manufacture String (bytes)
EEPROM Offset of Manufacture String
09H
Length of Product String (bytes)
EEPROM Offset of Product String
0AH
Length of Serial Number String (bytes)
EEPROM Offset of Serial Number String
0BH
Length of Configuration String (bytes)
EEPROM Offset of Configuration String
0CH
Length of Interface 0 String (bytes)
EEPROM Offset of Interface 0 String
0DH
Length of Interface 1/0 String (bytes)
EEPROM Offset of Interface 1/0 String
0EH
Length of Interface 1/1 String (bytes)
EEPROM Offset of Interface 1/1 String
0FH
Phy Register Offset for Interrupt Endpoint
Phy Register Offset for Interrupt Endpoint
10H
Max Packet Size High Byte
Max Packet Size Low Byte
11H
Secondary Phy_Type [7:5] and Phy_ID [4:0]
Primary Phy_Type [7:5] and Phy_ID [4:0]
12H
Pause Frame High Water Mark
Pause Frame Low Water Mark
13H
Length of Full-Speed Device Descriptor (bytes)
EEPROM Offset of Full-Speed Device Descriptor
14H
Length of Full-Speed Configuration Descriptor
(bytes)
Reserved
EEPROM Offset of Full-Speed Configuration
Descriptor
Reserved
15H-1FH
Table 2: Serial EEPROM Memory Map
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AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
4.1 Detailed Description
The following sections provide detailed description for some of the field in serial EEPROM memory map, for other fields
not covered here, please refer to AX88772L application note for more details.
4.1.1 Word Count for Preload (00h)
The number of words to be preloaded by the EEPROM loader = 15h.
4.1.2 Flag (01h)
Bit 15
Bit 14
Bit 7
TACE
Bit 6
RDCE
Bit 13
Bit 12
Reserved
Bit 5
Bit 4
SCPR
DCK
Bit 11
Bit 10
Bit 3
1
Bit 2
RWU
Bit 9
TDPE
Bit 1
Reserved
Bit 8
CEM
Bit 0
SP
SP: Self-Power (for USB GetStatus)
1: Self power.
0: Bus power.
RWU: Remote Wakeup support.
1: Indicate that this device supports Remote Wakeup.
0: Not support.
DCK: Disable Chirp K.
1: Disabled.
0: Enable.
SCPR: Software Control PHY Reset.
1: The PRL and PRTE bits of Software Reset Register control the PHYRST_N output level.
0: The USB reset on USB bus and PRTE bit of Software Reset Register control the PHYRST_N output level.
RDCE: RX Drop CRC Enable.
1: CRC byte is dropped on received MAC frame forwarding to host.
0: CRC byte is not dropped.
TACE: TX Append CRC Enable.
1: CRC byte is generated and appended by the ASIC for every transmitted MAC frame.
0: CRC byte is not appended.
CEM: Capture Effective Mode.
1: Capture effective mode enable.
0: Disabled.
TDPE: Test Debug Port Enable.
1: Enable test debug port for chip debug purpose.
0: Disable test debug port and the chip operate in normal function mode
Bit 1, 10~15: Reserved.
4.1.3 Node ID (04~06h)
The Node ID 0 to 5 bytes represent the MAC address of the device, for example, if MAC address = 01-23-45-67-89-ABh,
then Node ID 0 = 01, Node ID 1 = 23, Node ID 2 = 45, Node ID 3 = 67, Node ID 4 = 89, and Node ID 5 = AB.
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AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
4.1.4 Phy Register Offset for Interrupt Endpoint (0Fh)
Bit 15
Bit 7
Bit 14
Reserved
Bit 6
Reserved
Bit 13
Bit 12
Bit 5
Bit 4
Bit 11
Bit 10
Bit 9
Phy Register Offset 1
Bit 3
Bit 2
Bit 1
Phy Register Offset 2
Bit 8
Bit 0
Phy Register Offset 1: Fill in Phy’s Register Offset of Primary Phy here. Upon each Interrupt Endpoint issued, its
register value will be reported in byte# 5 and 6 of Interrupt Endpoint packet.
Phy Register Offset 2: Fill in Phy’s Register Offset of Primary Phy here. Upon each Interrupt Endpoint issued, its
register value will be reported in byte# 7 and 8 of Interrupt Endpoint packet.
4.1.5 Max Packet Size High/Low Byte (10h)
Fill in this field the maximum RX/TX MAC frame size supported by this ASIC. The number must be even number in
terms of byte and should be less than or equal to 2500 bytes.
4.1.6 Primary/Secondary Phy_Type and Phy_ID (11h)
The 3 bits Phy_Type field for both Primary and Secondary Phy is defined as follows,
3’b000: 10/100 Ethernet Phy or 1M HOME Phy.
3’b111: non-supported Phy. For example, the High Byte value of “E0h” means that secondary Phy is not supported.
Note that the Phy_ID of the embedded 10/100 Ethernet PHY is being assigned to 5’b1_0000.
4.1.7 Pause Frame High Water and Low Water Mark (12H)
When operating in full-duplex mode, correct setting of this field is very important and can affect the overall packet
receive throughput performance in a great deal. The High Water Mark is the threshold to trigger sending of Pause frame
and the Low Water Mark is the threshold to stop sending of Pause frame. Note that each free buffer count here represents
256 bytes of packet storage space in SRAM.
Total free buffer count = 80
Stop sending Pause frame when free buffer > Low Water Mark
Start sending Pause frame when free buffer < High Water Mark
0
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AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
4.1.8 Power-Up Steps
After power-on reset, the ASIC will automatically perform following steps to the Ethernet Phys via MDC/MDIO lines,
1. Write to Phy_ID of 00h with Phy register offset 00h to power down all Phys attached to station management
interface.
2. Write to Primary Phy_ID with Phy register offset 00h to power down Primary Phy.
3. Write to Secondary Phy_ID with Phy register offset 00h to power down Secondary Phy.
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AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
5.0 USB Configuration Structure
5.1 USB Configuration
The AX88772 supports 1 Configuration only.
5.2 USB Interface
The AX88772 supports 1 interface.
5.3 USB Endpoints
The AX88772 supports following 4 endpoints:
Endpoint 0: Control endpoint. It is used for configuring the device, e.g., standard commands and vendor commands,
etc.
Endpoint 1: Interrupt endpoint. It is used for reporting status.
Endpoint 2: Bulk In endpoint. It is used for receiving Ethernet Packet.
Endpoint 3: Bulk Out endpoint. It is used for transmitting Ethernet Packet.
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AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
6.0 USB Commands
There are three command groups for Endpoint 0 (Control Endpoint) in AX88772:
The USB standard commands
The USB vendor commands
The USB Communication Class commands
6.1 USB Standard Commands
The Language ID is 0x0904 for English
PPLL means buffer length
CC means configuration number
I I means Interface number
AA means Device Address
Setup Command
Data Bytes
8006_00 01 00 00 LLPP
PPLL bytes in Data stage
Access
Type
Read
Description
8006_0002 0000_LLPP
PPLL bytes in Data stage
Read
Get Configuration Descriptor
8006_0003_0000_LLPP
PPLL bytes in Data stage
Read
Get Supported Language ID
8006_0103_0904_LLPP
PPLL bytes in Data stage
Read
Get Manufacture String
8006_0203_0904_LLPP
PPLL bytes in Data stage
Read
Get Product String
8006_0303_0904_LLPP
PPLL bytes in Data stage
Read
Get Serial Number String
8006_0403_0904_LLPP
PPLL bytes in Data stage
Read
Get Configuration String
8006_0503_0904_LLPP
PPLL bytes in Data stage
Read
Get Interface 0 String
8006_0603_0904_LLPP
PPLL bytes in Data stage
Read
Get Interface 1/0 String
8006_0703_0904_LLPP
PPLL bytes in Data stage
Read
Get Interface 1/1 String
8008_0000_0000_0100
1 bytes in Data stage
Read
Get Configuration
0009_CC00_0000_0000
No data in Data stage
Write
Set Configuration
810A_0000 _I I00_0100
1 bytes in Data stage
Read
Get Interface
010B_AS00_0000_0000
No data in Data stage
Write
Set Interface
0005_AA00_0000_0000
No data in Data stage
Write
Set Address
Get Device Descriptor
Table 3: USB Standard Command Register Map
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ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
6.2 USB Vendor Commands
No
Setup Command
Data Bytes
1.
C002_AA0B_0C00_0800
8 bytes in Data stage
Access
Description
Type
Read Rx/Tx SRAM Read Register
2.
4003_AA0B_0C00_0800
8 bytes in Data stage
Write Rx/Tx SRAM Write Register
3.
4006_0000_0000_0000
No data in Data stage
4.
C007_ AA00_CC00_0200
2 bytes in Data stage
Write Software Serial Management Control
Register
Read PHY Read Register
5.
4008 _AA00_CC00_0200
2 bytes in Data stage
Write PHY Write Register
6.
C009_0000_0000_0100
1 bytes in Data stage
Read Serial Management Status Register
7.
400A_0000_0000_0000
No data in Data stage
8.
C00B_AA00_0000_0200
2 bytes in Data stage
Write Hardware Serial Management Control
Register
Read SROM Read Register
9.
400C_AA00_CCDD_0000 No data in Data stage
Write SROM Write Register
10. 400D_0000_0000_0000
No data in Data stage
Write SROM Write Enable Register
11. 400E_0000_0000_0000
No data in Data stage
Write SROM Write Disable Register
12. C00F_0000_0000_0200
2 bytes in Data stage
Read Rx Control Register
13. 4010_AABB_0000_0000
No data in Data stage
Write Rx Control Register
14. C011_0000_0000_0300
3 bytes in Data stage
Read IPG/IPG1/IPG2 Register
15. 4012_AABB_CC00_0000
No data in Data stage
Write IPG/IPG1/IPG2 Register
16. C013_0000_0000_0600
6 bytes in Data stage
Read Node ID Register
17. 4014_0000_0000_0600
6 bytes in Data stage
Write Node ID Register
18. C015_0000_0000_0800
20. 4017_AA00_0000_0000
8 bytes, MA0~MA7, in Read Multicast Filter Array Register
Data stage
8 bytes, MA0~MA7, in Write Multicast Filter Array Register
Data stage
No data in Data stage Write Test Register
21. C019_0000_0000_0200
2 bytes in Data stage
22. C01A_0000_0000_0200
2 bytes in Data stage
Read Ethernet/HomePNA Phy Address
Register
Read Medium Status Register
23. 401B_AABB_0000 _0000
No data in Data stage
Write Medium Mode Register
24. C01C_0000_0000_0100
1bytes in Data stage
Read Monitor Mode Status Register
25. 401D_AA00_0000_0000
No data in Data stage
Write Monitor Mode Register
26. C01E _0000_0000_0100
1 bytes in Data stage
Read GPIOs Status Register
27. 401F_AA00_0000_0000
No data in Data stage
Write GPIOs Register
28. 4020_AA00_0000_0000
No data in Data stage
Write Software Reset Register
29. C021_AA00_0000_0100
1 bytes in Data stage
Read Software PHY Select Status Register
30. 4022_AA00_0000_0000
No data in Data stage
Write Software PHY Select Register
19. 4016_0000_0000_0800
Table 4: USB Vendor Command Register Map
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AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
6.2.1 Detailed Register Description
6.2.1.1 Rx/Tx SRAM Read Register (02h, read only)
Bit7
Bit6
Bit5
Bit4
Bit3
AA [7:0]
Bit2
Reserved
0h
Bit1
Bit0
B [3:0]
C [3:0]
DD [7:0] in Data stage
EE [7:0] in Data stage
FF [7:0] in Data stage
GG [7:0] in Data stage
HH [7:0] in Data stage
II [7:0] in Data stage
JJ [7:0] in Data stage
KK [7:0] in Data stage
{B [3:0], AA [7:0]}: The read address of RX or TX SRAM.
C [0]: RAM selection.
0: indicates to read from RX SRAM.
1: indicates to read from TX SRAM.
C [3:1]: Reserved.
{DD [7:0], EE [7:0], FF [7:0], GG [7:0], HH [7:0], II [7:0], JJ [7:0], KK [7:0]}: The 64-bits of data presented in Data
stage are the data to be written to RX or TX SRAM.
6.2.1.2 Rx/Tx SRAM Write Register (03h, write only)
Bit7
Bit6
Bit5
Bit4
Bit3
AA [7:0]
Reserved
Reserved
Bit2
Bit1
Bit0
B [3:0]
C [3:0]
DD [7:0] in Data stage
EE [7:0] in Data stage
FF [7:0] in Data stage
GG [7:0] in Data stage
HH [7:0] in Data stage
II [7:0] in Data stage
JJ [7:0] in Data stage
KK [7:0] in Data stage
{B [3:0], AA [7:0]}: The write address of RX or TX SRAM.
C [0]: RAM selection.
0: indicates to write to RX SRAM.
1: indicates to write to TX SRAM.
C [3:1]: Reserved.
{DD [7:0], EE [7:0], FF [7:0], GG [7:0], HH [7:0], II [7:0], JJ [7:0], KK [7:0]}: The 64-bits of data presented in Data
stage are the data to be written to RX or TX SRAM.
6.2.1.3 Software Serial Management Control Register (06h, write only)
When software needs to access to Ethernet PHY’s internal registers, one has to first issue this command to request the
ownership of Serial Management Interface. The ownership status of the interface can be retrieved from Serial
Management Status Register.
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AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
6.2.1.4 PHY Read Register (07h, read only)
Bit7
Bit6
Bit5
Bit4
Bit3
AA [7:0]
00h
CC [7:0]
Bit2
Bit1
Bit0
Bit1
Bit0
Bit1
Bit0
Host_EN
AA [4:0]: The PHY ID value.
CC [4:0]: The register address of Ethernet PHY’s internal register.
AA [7:5]: Reserved
CC [7:5]: Reserved
6.2.1.5 PHY Write Register (08h, write only)
Bit7
Bit6
Bit5
Bit4
Bit3
AA [7:0]
00h
CC [7:0]
Bit2
AA [4:0]: The PHY ID value.
CC [4:0]: The register address of Ethernet PHY’s internal register.
AA [7:5]: Reserved
CC [7:5]: Reserved
6.2.1.6 Serial Management Status Register (09h, read only)
Bit7
Bit6
Bit5
Bit4
Reserved
Bit3
Bit2
Host_EN: Host access Enable. Software can read this register to determine the current ownership of Serial
Management Interface.
1: Software is allowed to access Ethernet PHY’s internal registers via PHY Read Register or PHY Write Registers.
0: ASIC’s hardware owns the Serial Management Interface and software’s access is ignored.
6.2.1.7 Hardware Serial Management Control Register (0Ah, write only)
When software is done accessing Serial Management Interface, one needs to issue this command to release the
ownership of the Interface back to ASIC’s hardware. After issuing this command, following PHY Read Register or
PHY Write Register from software will be ignored. NOTE: Software should issue this command every time after
finished accessing Serial Management Interface to release the ownership back to hardware to allow periodic Interrupt
Endpoint to be able to access the Ethernet PHY’s registers via the Serial Management Interface.
6.2.1.8 SROM Read Register (0Bh, read only)
Bit7
Bit6
Bit5
Bit4
Bit3
AA [7:0]
Bit2
Bit1
Bit0
AA [7:0]: The read address of Serial EEROM.
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AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
6.2.1.9 SROM Write Register (0Ch, write only)
Bit7
Bit6
Bit5
Bit4
Bit3
AA [7:0]
00h
CC [7:0]
DD [7:0]
Bit2
Bit1
Bit0
AA [7:0]: The write address of Serial EEROM.
{ DD [7:0], CC [7:0] }: The write data value of Serial EEROM
6.2.1.10 Write SROM Enable (0Dh, write only)
User issues this command to enable write permission to Serial EEPROM from SROM Write Register.
6.2.1.11 Write SROM Disable (0Eh, write only)
User issues this command to disable write permission to Serial EEPROM from SROM Write Register.
6.2.1.12 Rx Control Register (0Fh, read only and 10h, write only)
Bit7
SO
Bit6
Reserved
Bit5
AP
0h
Bit4
AM
Bit3
Bit2
AB
SEP
Reserved
Bit1
Bit0
AMALL
PRO
MFB [1:0]
AA [7:0] = { SO, Reserved, AP, AM, AB, Reserved, AMALL, PRO }
BB [7:0] = { 0h, Reserved [3:2], SB [1:0] }
PRO: PACKET_TYPE_PROMISCUOUS.
1: All frames received by the ASIC are forwarded up toward the host.
0: Disabled (default).
AMALL: PACKET_TYPE_ALL_MULTICAST.
1: All multicast frames received by the ASIC are forwarded up toward the host, not just the frames whose
scrambling result of DA matching with multicast address list provided in Multicast Filter Array Register.
0: Disabled. This only allows multicast frames whose scrambling result of DA field matching with multicast
address list provided in Multicast Filter Array Register to be forwarded up toward the host (default).
SEP: Save Error Packet.
1: Received packets with CRC error are saved and forwarded to the host anyway.
0: Received packets with CRC error are discarded automatically without forwarding to the host (default).
AB: PACKET_TYPE_BROADCAST.
1: All broadcast frames received by the ASIC are forwarded up toward the host (default).
0: Disabled.
AM: PACKET_TYPE_MULTICAST.
1: All multicast frames whose scrambling result of DA matching with multicast address list are forwarded up to the
host (default).
0: Disabled.
AP: Accept Physical Address from Multicast Filter Array.
1: Allow unicast packets to be forwarded up toward host if the lookup of scrambling result of DA is found within
multicast address list.
0: Disabled, that is, unicast packets filtering are done without regarding multicast address list (default).
SO: Start Operation.
1: Ethernet MAC start operating.
0: Ethernet MAC stop operating (default).
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AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
MFB [1:0]: Maximum Frame Burst transfer on USB bus.
00: 2048 Bytes
01: 4096 Bytes
10: 8192 Bytes
11: 16384 Bytes (default).
6.2.1.13 IPG/IPG1/IPG2 Control Register (11h, read only and 12h, write only)
Bit7
Bit6
Bit5
Bit4
Bit3
AA [7:0]
BB [7:0]
CC [7:0]
Bit2
Bit1
Bit0
AA [6:0] = IPG [6:0].
BB [6:0] = IPG1 [6:0].
CC [6:0] = IPG2 [6:0].
IPG [6:0]: Inter Packet Gap for back-to-back transfer on TX direction in MII mode (default = 15h).
IPG1 [6:0]: IPG part1 value (default = 0Ch).
IPG2 [6:0]: IPG part1 value + part2 value (default = 12h).
AA [7]: Reserved.
BB [7]: Reserved.
CC [7]: Reserved.
6.2.1.14 Node ID Register (13h, read only and 14h, write only)
Bit7
Bit6
Bit5
Bit4
Bit3
AA [7:0]
BB [7:0]
CC [7:0]
DD [7:0]
EE [7:0]
FF [7:0]
Bit2
Bit1
Bit0
AA [7:0] = NOID 0.
BB [7:0] = NOID 1.
CC [7:0] = NOID 2.
DD [7:0] = NOID 3.
EE [7:0] = NOID 4.
FF [7:0] = NOID 5.
{FF [7:0], EE [7:0], DD [7:0], CC [7:0], BB [7:0], AA [7:0]} = Ethernet MAC address [47:0] of the node.
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USB to 10/100 Fast Ethernet/HomePNA Controller
6.2.1.15 Multicast Filter Array (15h, read only and 16h, write only)
Bit7
Bit6
Bit5
Bit4
Bit3
MA 0 [7:0]
MA 1 [7:0]
MA 2 [7:0]
MA 3 [7:0]
MA 4 [7:0]
MA 5 [7:0]
MA 6 [7:0]
MA 7 [7:0]
Bit2
Bit1
Bit0
{MA7 [7:0], MA6 [7:0], MA5 [7:0], MA4 [7:0], MA3 [7:0], MA2 [7:0], MA1 [7:0], MA0 [7:0]} = the multicast
address bit map for multicast frame filtering block. See Figure 5: Multicast Filter Example, for example.
DA
81 81 81 81 81 81
CRC32
{crc31, 30, 29, 28, 27, 26}
Address[5:0] = 1Ah
MAR[63:0] =
400_0000h
Figure 5: Multicast Filter Example
6.2.1.16 Test Register (17h, write only)
Bit7
Bit6
Bit5
Bit4
MM [7:6]
Bit3
Bit2
Bit1
Bit0
LDRND
LDRND: Load Random number into MAC’s exponential back-off timer. User writes a “1” to enable the ASIC to load
a small random number into MAC’s back-off timer to shorten the back-off duration in each retry after
collision. This register is used for test purpose. Default value = 0.
MM [7:6]: Reserved.
6.2.1.17 Ethernet / HomePNA Phy Address Register (19h, read only)
Bit7
Bit6
Bit5
SecPhyType [2:0]
PriPhyType [2:0]
Bit4
Bit3
Bit2
Bit1
SecPhyID [4:0]
PriPhyID [4:0]
Bit0
SecPhyType, SecPhyID: The Secondary PHY address loaded from serial EEPROM’s offset address 11h.
PriPhyType, PriPhyID: The Primarily PHY address loaded from serial EEPROM’s offset address 11h.
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AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
6.2.1.18 Medium Status Register (1Ah, read only) and Medium Mode Register (1Bh, write only)
Bit7
PF
Bit6
0
Reserved
Bit5
TFC
Bit4
RFC
SM
Bit3
0
SBP
Bit2
1
Reserved
Bit1
FD
PS
Bit0
0
RE
AA [7:0] = {PF, JFE, TFC, RFC, EN125, AC, FD, GM}.
BB [7:0] = {Reserved, SM, SBP, JE, PS, RE}.
Bit 0: Please always write 0 to this bit.
PS: Port Speed in MII mode
1: 100 Mbps (default).
0: 10 Mbps.
FD: Full Duplex mode
1: Full Duplex mode (default).
0: Half Duplex mode.
Bit 2: Please always write 1 to this bit.
Bit 3: Please always write 0 to this bit.
RFC: RX Flow Control enable.
1: Enable receiving of pause frame on RX direction during full duplex mode (default).
0: Disabled.
TFC: TX Flow Control enable.
1: Enable transmitting pause frame on TX direction during full duplex mode (default).
0: Disabled.
Bit 6: Please always write 0 to this bit.
PF: Check only “length/type” field for Pause Frame.
1: Enable, i.e., Pause frames are identified only based on L/T filed.
0: Disabled, i.e., Pause frames are identified based on both DA and L/T fields (default).
RE: Receive Enable.
1: Enable RX path of the ASIC.
0: Disabled (default).
SBP: Stop Backpressure.
1: When TFC bit = 1, setting this bit enables backpressure on TX direction “continuously” during RX buffer full
condition in half duplex mode.
0: When TFC bit = 1, setting this bit enable backpressure on TX direction “intermittently” during RX buffer full
condition in half duplex mode (default).
SM: Super Mac support.
1: Enable Super Mac to shorten exponential back-off time during transmit retry.
0: Disabled (default).
6.2.1.19 Monitor Mode Status Register (1Ch, read only)
Bit7
Bit6
Reserved
Bit5
Bit4
US
Bit3
Reserved
Bit2
RWMP
Bit1
RWLU
Bit0
MOM
MOM: Monitor Mode.
1: Enable. All received packets will be checked on DA and CRC but not buffered into memory.
0: Disabled (default).
RWLU: Remote Wakeup trigger by Ethernet Link-up.
1: Enable
0: Disabled (default).
RWMP: Remote Wakeup trigger by Magic Packet.
1: Enable
0: Disabled (default).
US: USB Speed.
1: High speed mode.
0: FS speed mode.
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AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
6.2.1.20 Monitor Mode Register (1Dh, write only)
Bit7
Bit6
Bit5
Reserved
Bit4
Bit3
Bit2
RWMP
Bit1
RWLU
Bit0
MOM
MOM: Monitor Mode.
1: Enable. All received packets will be checked on DA and CRC but not buffered into memory.
0: Disabled (default).
RWLU: Remote Wakeup trigger by Ethernet Link-up.
1: Enable.
0: Disabled (default).
RWMP: Remote Wakeup trigger by Magic Packet.
1: Enable.
0: Disabled (default).
AA [7:3]: Reserved.
6.2.1.21 GPIO Status Register (1Eh, read only)
Bit7
Bit6
Bit5
GPI_2
Bit4
GPO_2_EN
Bit3
GPI_1
Bit2
GPO_1_EN
Bit1
GPI_0
Bit0
GPO_0_EN
GPO_0_EN: Current level of pin GPIO0’s output enable.
GPI_0: Input level on GPIO0 pin when GPIO0 is as an input pin.
GPO_1_EN: Current level of pin GPIO1’s output enable.
GPI_1: Input level on GPIO1 pin when GPIO1 is as an input pin.
GPO_2_EN: Current level of pin GPIO2’s output enable.
GPI_2: Input level on GPIO2 pin when GPIO2 is as an input pin.
6.2.1.22 GPIO Register (1Fh, write only)
Bit7
RSE
Bit6
Bit5
GPO_2
Bit4
GPO2EN
Bit3
GPO_1
Bit2
GPO1EN
Bit1
GPO_0
Bit0
GPO0EN
GPO0EN: Pin GPIO0 Output Enable.
1: Output is enabled (meaning GPIO0 is used as an output pin).
0: Output is tri-stated (meaning GPIO0 is used as an input pin) (default).
GPO_0: Pin GPIO0 Output Value.
GPO1EN: Pin GPIO1 Output Enable.
1: Output is enabled (meaning GPIO1 is used as an output pin).
0: Output is tri-stated (meaning GPIO1 is used as an input pin) (default).
GPO_1: Pin GPIO1 Output Value.
0: (default).
GPO2EN: Pin GPIO2 Output Enable.
1: Output is enabled (meaning GPIO2 is used as an output pin).
0: Output is tri-stated (meaning GPIO2 is used as an input pin) (default).
GPO_2: Pin GPIO2 Output Value.
0: (default).
RSE: Reload Serial EEPROM.
1: Enable.
0: Disabled (default)
6.2.1.23 Software Reset Register (20h, write only)
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ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
Bit7
Reserved
Bit6
IPPD
Bit5
IPRL
Bit4
BZ
Bit3
PRL
Bit2
PRTE
Bit1
RT
Bit0
RR
RR: Clear frame length error for Bulk In.
1: set high to clear state.
0: set low to exit clear state (default).
RT: Clear frame length error for Bulk Out.
1: set high to enter clear state.
0: set low to exit clear state (default).
PRTE: External Phy Reset pin Tri-state Enable.
1: Enable, i.e., the external PHYRST_N pin is tri-stated (default). This allows the PHYRST_N pin’s active level to
be controlled by external pulled-up (active high during power-on) or pulled-down resistor (active low during
power-on).
0: Disabled, i.e., the external PHYRST_N pin’s level is driven by either PRL bit or internal “USB RESET” based on
the setting in SCPR bit in Flag byte of EEPROM.
PRL: External Phy Reset pin Level. When SCPR bit = 1 and PRTE = 0, this bit controls the output level of external
PHYRST_N pin.
1: Set to high (default).
0: Set to low.
BZ: Force Bulk In to return a Zero-length packet.
1: Software can force Bulk In to return a zero-length USB packet.
0: Normal operation mode (default).
IPRL: Internal Phy Reset control. When SCPR bit = 1, this bit acts as reset signal of internal Ethernet Phy.
1: Internal Ethernet Phy is in operating state.
0: Internal Ethernet Phy in reset state (default).
IPPD: Internal Ethernet Phy Power Down control.
1: Internal Ethernet Phy is in power down mode (default).
0: Internal Ethernet Phy is in operating mode.
6.2.1.24 Software PHY Select Status Register (21h, read only) and Software PHY Select Register
22h, write only)
Bit7
Bit6
Bit5
Bit4
Reserved
Bit3
Bit2
Bit1
ASEL
Bit0
PSEL
PSEL: Phy Select, when ASEL = 0 (manually select the Phy to operate)
1: Select embedded 10/100 Ethernet Phy (default).
0: Select external Phy, which is attached to the MII interface
ASEL: Auto Select or Manual Select
1: Automatically select based on link status of embedded 10/100 Ethernet Phy (default).
0: Manually select between the embedded 10/100 Ethernet Phy and the external one.
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ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
6.2.2 Remote Wakeup Description
After AX88772 enters into suspend mode, either the USB host or AX88772 itself can awake it up and resume back to the
original operation mode before it entered suspend. Following truth table shows the chip setting, wakeup event, and device
response supported by this ASIC. Note that “X” stands for don’t-care.
Wakeup
by
Host
Device
Device
Device
Device
Device
Setting
Wakeup Event
RWU bit Set_Feature RWLU of
of Flag
standard
Monitor
byte in
command
Mode
EEPRO
Register
M
X
X
X
0
0
X
1
1
0
1
1
1
1
1
1
1
1
X
RWMP of
Monitor
Mode
register
Host send
resume
signal
X
X
1
0
0
X
J -> K
Device
awakes up?
Receiving EXTWAKE Linkup
Linkup
Magic
UP_N pin detected detected on
Packet
on
Secondary
Primary
Phy
Phy
X
Yes
X
X
X
Yes
Yes
Low-pulse
Yes
No
Yes
Yes
Yes
Yes
Table 5: Remote Wakeup Truth Table
6.3 Interrupt Endpoint
The Interrupt Endpoint contains 8 bytes of data and its frame format is defined as: A100_BB00_CCDD_EEFF.
Where BB byte in byte 3:
Bit7
Bit6
Bit5
Reserved
Bit4
Bit3
MDINT
Bit2
FLE
Bit1
SPLS
Bit0
PPLS
PPLS: Primarily PHY Link State.
1: Link is up.
0: Link is down.
SPLS: Secondary PHY Link State.
1: Link is up.
0: Link is down.
FLE: Bulk Out Ethernet Frame Length Error.
1: Proprietary Length field has parity error during Bulk Out transaction.
0: Proprietary Length field has no parity error during Bulk Out transaction.
MDINT: Input level of MDINT pin. The MDINT pin can be connected to MDINT# pin of Ethernet Phy.
1: When MDINT input pin = 1.
0: When MDINT input pin = 0.
CCDD byte in byte 5 and 6: Primary Phy’s register value, whose offset is given in High byte of EEPROM offset 0Fh.
EEFF byte in byte 7 and 8: Primary Phy’s register value, whose offset is given in Low byte of EEPROM offset 0Fh.
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AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
7.0 Embedded Ethernet Phy Register Description
Address
0h
1h
2h
3h
4h
5h
6h
7h
8h-Fh
Register Name
BMCR
BMSR
PHYIDR1
PHYIDR2
ANAR
ANLPAR
ANER
Reserved
IEEE reserved
Description
Basic mode control register, basic register.
Basic mode status register, basic register.
PHY identifier register 1, extended register.
PHY identifier register 2, extended register.
Auto negotiation advertisement register, extended register.
Auto negotiation link partner ability register, extended register.
Auto negotiation expansion register, extended register.
Reserved and currently not supported.
IEEE 802.3u reserved.
Table 6: Embedded Ethernet Phy Register Map
7.1 Detailed Register Description
The following abbreviations apply to following sections for detailed register description.
Reset value:
1: Bit set to logic one
0: Bit set to logic zero
X: No set value
Pin#: Value latched from pin # at reset time
Access type:
RO: Read only
RW: Read or write
Attribute:
SC: Self-clearing
PS: Value is permanently set
LL: Latch low
LH: Latch high
7.1.1 Basic Mode Control Register (BMCR)
Address 00h
Bit
Bit Name
15 Reset
Default
0, RW / SC
14
Loopback
0, RW
13
Speed selection
1, RW
12
Auto-negotiation
enable
1, RW
Description
Reset:
1 = Software reset
0 = Normal operation
Loopback:
1 = Loopback enabled
0 = Normal operation
Speed selection:
1 = 100 Mb/s
0 = 10 Mb/s
Auto-negotiation enable:
1 = Auto-negotiation enabled. Bits 8 and 13 of this register are
ignored when this bit is set.
0 = Auto-negotiation disabled. Bits 8 and 13 of this register
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AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
11
Power down
0, RW
10
Isolate
(PHYAD = 00000),
RW
9
Restart
auto-negotiation
0, RW / SC
8
Duplex mode
1, RW
7
Collision test
0, RW
6:0 Reserved
X, RO
determine the link speed and mode.
Power down:
1 = Power down
0 = Normal operation
Isolate:
1 = Isolate
0 = Normal operation
Restart auto-negotiation:
1 = Restart auto-negotiation
0 = Normal operation
Duplex mode:
1 = Full duplex operation
0 = Normal operation
Collision test:
1 = Collision test enabled
0 = Normal operation
Reserved:
Write as 0, read as “don’t care”.
7.1.2 Basic Mode Status Register (BMSR)
Address 01h
Bit
Bit Name
15 100BASE-T4
Default
0, RO / PS
14
100BASE-TX full
duplex
1, RO / PS
13
100BASE-TX half
duplex
1, RO / PS
12
10BASE-T full
duplex
11 10BASE-T half
duplex
10:7 Reserved
1, RO / PS
1, RO / PS
0, RO
6
MF preamble
suppression
0, RO / PS
5
Auto-negotiation
complete
0, RO
4
Remote fault (Not
supported)
0, RO / LH
3
1, RO / PS
2
Auto-negotiation
ability
Link status
0, RO / LL
1
Jabber detect
0, RO / LH
0
Extended capability
1, RO / PS
Description
100BASE-T4 capable:
0 = This PHY is not able to perform in 100BASE-T4 mode.
100BASE-TX full-duplex capable:
1 = This PHY is able to perform in 100BASE-TX full-duplex
mode.
100BASE-TX half-duplex capable:
1 = This PHY is able to perform in 100BASE-TX half-duplex
mode.
10BASE-T full-duplex capable:
1 = This PHY is able to perform in 10BASE-T full-duplex mode.
10BASE-T half-duplex capable:
1 = This PHY is able to perform in 10BASE-T half-duplex mode.
Reserved:
Write as 0, read as “don’t care”.
Management frame preamble suppression:
0 = This PHY will not accept management frames with preamble
suppressed.
Auto-negotiation completion:
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed
Remote fault:
1 = Remote fault condition detected (cleared on read or by a chip
reset)
0 = No remote fault condition detected
Auto configuration ability:
1 = This PHY is able to perform auto-negotiation.
Link status:
1 = Valid link established (100Mb/s or 10Mb/s operation)
0 = Link not established
Jabber detection:
1 = Jabber condition detected
0 = No Jabber condition detected
Extended capability:
29
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AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
1 = Extended register capable
0 = Basic register capable only
7.1.3 PHY Identifier Register 1
Address 02h
Bit
Bit Name
15:0 OUI_MSB
Default
003B hex, RO / PS
Description
OUI most significant bits:
Bits 3 to 18 of the OUI are mapped to bits 15 to 0 of this register
respectively. The most significant two bits of the OUI are ignored.
7.1.4 PHY Identifier Register 2
Address 03h
Bit
Bit Name
15:10 OUI_LSB
9:4
3:0
VNDR_MDL
MDL_REV
Default
00_0110, RO / PS
00_0001, RO / PS
0001, RO / PS
Description
OUI least significant bits:
Bits 19 to 24 of the OUI are mapped to bits 15 to 10 of this register
respectively.
Vendor model number.
Model revision number.
7.1.5 Auto Negotiation Advertisement Register (ANAR)
Address 04h
Bit
Bit Name
15 NP
Default
0, RO / PS
14
ACK
0, RO
13
RF
0, RW
12:11 Reserved
X, RW
10
Pause
0, RW
9
T4
0, RO/PS
8
TX_FD
1, RW
7
TX_HD
1, RW
6
10_FD
1, RW
5
10_HD
1, RW
4:0
Selector
0_0001, RW
Description
Next page indication:
0 = No next page available
The PHY does not support the next page function.
Acknowledgement:
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
Remote fault:
1 = Fault condition detected and advertised
0 = No fault detected
Reserved:
Write as 0, read as “don’t care”.
Pause:
1 = Pause operation enabled for full-duplex links
0 = Pause operation not enabled
100BASE-T4 support:
0 = 100BASE-T4 not supported
100BASE-TX full-duplex support:
1 = 100BASE-TX full-duplex supported by this device
0 = 100BASE-TX full-duplex not supported by this device
100BASE-TX half-duplex support:
1 = 100BASE-TX half-duplex supported by this device
0 = 100BASE-TX half-duplex not supported by this device
10BASE-T full-duplex support:
1 = 10BASE-T full-duplex supported by this PHY
0 = 10BASE-T full-duplex not supported by this PHY
10BASE-T half-duplex support:
1 = 10BASE-T half-duplex supported by this PHY
0 = 10BASE-T half-duplex not supported by this PHY
Protocol selection bits:
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ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
These bits contain the binary encoded protocol selector supported
by this PHY. [0 0001] indicates that this PHY supports IEEE
802.3u CSMA/CD.
7.1.6 Auto Negotiation Link Partner Ability Register (ANLPAR)
Address 05h
Bit
Bit Name
15 NP
Default
0, RO
14
ACK
0, RO
13
RF
0, RO
12:11 Reserved
X, RO
10
Pause
0, RO
9
T4
0, RO
8
TX_FD
0, RO
7
TX_HD
0, RO
6
10_FD
0, RO
5
10_HD
0, RO
4:0
Selector
0_0000, RO
Description
Next page indication:
1 = Link partner next page enabled
0 = Link partner not next page enabled
Acknowledgement:
1 = Link partner ability for reception of data word acknowledged
0 = Not acknowledged
Remote fault:
1 = Remote fault indicated by link partner
0 = No remote fault indicated by link partner
Reserved:
Write as 0, read as “don’t care”.
Pause:
1 = Pause operation supported by link partner
0 = Pause operation not supported by link partner
100BASE-T4 support:
1 = 100BASE-T4 supported by link partner
0 = 100BASE-T4 not supported by link partner
100BASE-TX full-duplex support:
1 = 100BASE-TX full-duplex supported by link partner
0 = 100BASE-TX full-duplex not supported by link partner
100BASE-TX half-duplex support:
1 = 100BASE-TX half-duplex supported by link partner
0 = 100BASE-TX half-duplex not supported by link partner
10BASE-T full-duplex support:
1 = 10BASE-T full-duplex supported by link partner
0 = 10BASE-T full-duplex not supported by link partner
10BASE-T half-duplex support:
1 = 10BASE-T half-duplex supported by link partner
0 = 10BASE-T half-duplex not supported by link partner
Protocol selection bits:
Link partner’s binary encoded protocol selector.
7.1.7 Auto Negotiation Expansion Register (ANER)
Address 06h
Bit
Bit Name
15:5 Reserved
Default
0, RO
4
PDF
0, RO / LH
3
LP_NP_AB
0, RO
2
NP_AB
0, RO / PS
1
Page_RX
0, RO / LH
Description
Reserved:
Write as 0, read as “don’t care”.
Parallel detection fault:
1 = Fault detected via the parallel detection function
0 = No fault detected
Link partner next page enable:
1 = Link partner next page enabled
0 = Link partner not next page enabled
PHY next page enable:
0 = PHY not next page enabled
New page reception:
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ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
0
LP_AN_AB
0, RO
1 = New page received
0 = New page not received
Link partner auto-negotiation enable:
1 = Auto-negotiation supported by link partner
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ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
8.0 Electrical Specifications
8.1 DC Characteristics
8.1.1 Absolute Maximum Ratings
Symbol
VDDK
Parameter
Digital core power supply
Rating
- 0.3 to VDDK + 0.3
Unit
V
VDD2
VDD3
AVDDK
AVDD3
VIN2
Power supply of 2.5V I/O
Power supply of 3.3V I/O
Analog core power supply
Power supply of analog I/O
Input voltage of 2.5V I/O
Input voltage of 2.5V I/O with 3.3V tolerant
Input voltage of 3.3V I/O
- 0.3 to VDD2 + 0.3
- 0.5 to VDD3 + 0.5
- 0.3 to AVDDK + 0.3
- 0.5 to AVDD3 + 0.5
- 0.3 to VDD2 + 0.3
- 0.3 to 3.9
- 0.3 to VDD3 + 0.3
V
V
V
V
V
V
V
Input voltage of 3.3V I/O with 5V tolerant
- 0.3 to 5.5
V
VIN3
TSTG
Storage temperature
- 40 to 150
℃
Note: Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be
restricted in the optional sections of this datasheet. Exposure to absolute maximum rating condition for extended periods
may affect device reliability.
8.1.2 Recommended Operating Condition
Symbol
VDDK
VDD2
VDD3
AVDDK
AVDD3
VIN2
VIN3
Tj
Tc
Parameter
Digital core power supply
Power supply of 2.5V I/O
Power supply of 3.3V I/O
Analog core power supply
Power supply of analog I/O
Input voltage of 2.5 V I/O
Min
2.25
2.25
3.0
2.25
3.0
0
Typ
2.5
2.5
3.3
2.5
3.3
2.5
Max
2.75
2.75
3.6
2.75
3.6
2.75
Unit
V
V
V
V
V
V
0
2.5
3.6
V
0
0
3.3
3.3
3.6
5.25
V
V
0
-
115
℃
0
-
70
℃
Input voltage of 2.5 V I/O with 3.3 V
tolerance
Input voltage of 3.3 V I/O
Input voltage of 3.3 V I/O with 5 V
tolerance
Commercial junction operating
temperature
Commercial operating temperature
8.1.3 Leakage Current and Capacitance
Symbol
IIN
IOZ
CIN
Parameter
Input current
Tri-state leakage current
Input capacitance
Condition
No pull-up or pull-down
Min
-10
-10
-
Typ
±1
±1
3.1
Max
10
10
-
Unit
μA
μA
pF
COUT
Output capacitance
-
3.1
-
pF
CBID
Bi-directional buffer capacitance
-
3.1
-
pF
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ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
Note: The capacitance listed above does not include pad capacitance and package capacitance. One can estimate pin
capacitance by adding a pad capacitance of about 0.5pF and the package capacitance.
8.1.4 DC Characteristics of 2.5V I/O Pins
Symbol
VDD2
Temp
Vil
Vih
VtVt+
Vol
Voh
Rpu
Rpd
Iin
Ioz
Parameter
Condition
Power supply of 2.5V I/O
Junction temperature
CMOS
Input low voltage
Input high voltage
Schmitt trigger negative going CMOS
threshold voltage
Schmitt trigger positive going
threshold voltage
Output low voltage
|Iol| = 2~16mA
Output high voltage
|Ioh| = 2~16mA
Input pull-up resistance
Input pull-down resistance
Input leakage current
Vin = VDD2 or 0
Tri-state output leakage current
Min Typ
2.25 2.5
0
25
1.7
0.7 1.0
Max
2.75
115
0.7
-
Unit
V
℃
V
V
V
-
1.5
1.7
V
1.85
40
40
-10
-10
75
75
±1
±1
0.4
190
190
10
10
V
V
KΩ
KΩ
μA
μA
Max
3.6
115
0.8
-
Unit
V
℃
V
V
V
8.1.5 DC Characteristics of 3.3V I/O Pins
Symbol
VDD3
Temp
Vil
Vih
VtVt+
Vol
Voh
Rpu
Rpd
Iin
Ioz
Parameter
Condition
Power supply of 3.3V I/O
3.3V I/O
Junction temperature
LVTTL
Input low voltage
Input high voltage
Schmitt trigger negative going LVTTL
threshold voltage
Schmitt trigger positive going
threshold voltage
Output low voltage
|Iol| = 2~16mA
Output high voltage
|Ioh| = 2~16mA
Input pull-up resistance
Input pull-down resistance
Input leakage current
Vin = VDD3 or 0
Tri-state output leakage current
Min Typ
3.0 3.3
0
25
2.0
0.8 1.1
-
1.6
2.0
V
2.4
40
40
-10
-10
75
75
±1
±1
0.4
190
190
10
10
V
V
KΩ
KΩ
μA
μA
8.2 Power Consumption
Symbol
IVDDK2
IVDD3
IAVDDK
IAVDD3
ΘJC
ΘJA
Description
Condition
Current consumption of VDDK/VDD2, Operating at Ethernet
100Mbps full duplex
2.5V
mode and USB High
Current consumption of VDD3, 3.3V
Current consumption of AVDDK, 2.5V speed mode
Current consumption of AVDD3, 3.3V
Thermal resistance of junction to case
Thermal resistance of junction to ambient Still air
34
Min
-
Typ
25.4
-
<1
69.3
51.1
16.5
46
Max Units
mA
-
mA
mA
mA
°C/W
°C/W
ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
8.3 Power-up Sequence
At power-up, AX88772 requires the VDD3/AVDD3 power supply to rise to nominal operating voltage within Trise3 and
the VDDK/AVDD2/AVDDK power supply to rise to nominal operating voltage within Trise2.
Trise3
3.3V
VDD3/AVDD3
0V
Tdelay32
Trise2
2.5V
VDDK/VDD2/AVDDK
0V
Symbol
Trise3
Trise2
Tdelay32
Parameter
3.3V power supply rise time
2.5V power supply rise time
3.3V rise to 2.5V rise time delay
Condition
From 0V to 3.3V
From 0V to 2.5V
Min
-5
Typ
-
Max
10
10
5
Unit
ms
ms
ms
Typ
83.33
41.6
41.6
-
Max
1.0
1.0
Unit
ns
ns
ns
ns
ns
8.4 AC Timing Characteristics
8.4.1 Clock Timing
8.4.1.1 XIN12M
TP_XIN12M
TH_XIN12M
TL_XIN12M
VIH
VIL
TR_XIN12M
Symbol
TP_XIN12M
TH_XIN12M
TL_XIN12M
TR_XIN12M
TF_XIN12M
TF_XIN12M
Parameter
XIN12M clock cycle time
XIN12M clock high time
XIN12M clock low time
XIN12M rise time
XIN12M fall time
Condition
VIL (max) to VIH (min)
VIH (min) to VIL (max)
35
Min
-
ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
8.4.1.2 XIN25M
TP_XIN25M
TL_XIN25M
TH_XIN25M
VIH
VIL
TR_XIN25M
Symbol
TP_XIN25M
TH_XIN25M
TL_XIN25M
TR_XIN25M
TF_XIN25M
TF_XIN25M
Parameter
XIN25M clock cycle time
XIN25M clock high time
XIN25M clock low time
XIN25M rise time
XIN25M fall time
Condition
VIL (max) to VIH (min)
VIH (min) to VIL (max)
Min
-
Typ
40.0
20.0
20.0
-
Max
1.0
1.0
Unit
ns
ns
ns
ns
ns
8.4.2 Reset Timing
XIN12M
RESET_N
Trst
Symbol
Description
Trst
Reset pulse width (6ms ~10ms) after XIN12M
is running
Min
72000
Typ
-
Max
-
Units
XIN12M clock cycle
8.4.3 MII Timing (100Mbps)
Ttclk
Ttch
Ttcl
TX_CLK
Tts
Tth
TXD [3:0]
TX_EN, TX_ER
Symbol
Ttclk
Ttch
Ttcl
Tts
Tth
Description
Min
28.0
5.0
TX_CLK clock cycle time *1
TX_CLK clock high time *2
TX_CLK clock low time *2
TXD [3:0], TX_EN, TX_ER setup time
TXD [3:0], TX_EN, TX_ER hold time
36
Typ
40.0
20.0
20.0
-
Max
-
Units
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
Trclk
Trch
Trcl
RX_CLK
Trs
Trh
RXD [3:0]
RX_DV, RX_ER
Symbol
Trclk
Trch
Trcl
Trs
Trh
Description
Min
3.0
0.5
RX_CLK clock cycle time *1
RX_CLK clock high time *2
RX_CLK clock low time *2
RXD [3:0], RX_DV, and RX_ER setup time
RXD [3:0], RX_DV, and RX_ER hold time
Typ
40.0
20.0
20.0
-
Max
-
Units
ns
ns
ns
ns
ns
Max
2
-
Units
ns
ns
ns
ns
ns
ns
*1: For 10Mbps, the typical value of Ttclk and Trclk shall scale to 400ns.
*2: For 10Mbps, the typical value of Ttch, Ttcl, Trch, and Trcl shall scale to 200ns.
8.4.4 Station Management Timing
Tclk
MDC
Tch
Tcl
Tod
MDIO (as output)
Ts Th
MDIO (as input)
Symbol
Tclk
Tch
Tcl
Tod
Ts
Th
Description
MDC clock cycle time
MDC clock high time
MDC clock low time
MDC clock falling edge to MDIO output delay
MDIO data input setup time
MDIO data input hold time
Min
0
10
0
37
Typ
666
333
333
-
ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
8.4.5 Serial EEPROM Timing
Tclk
EECK
Tch
Tcl
Tdv
EEDI (output)
Tod
VALID
VALID
Thcs
Tscs
Tlcs
EECS
Ts
EEDO (input)
Symbol
Tclk
Tch
Tcl
Tdv
Tod
Tscs
Thcs
Tlcs
Ts
Th
Th
DATA VALID
Description
EECK clock cycle time
EECK clock high time
EECK clock low time
EEDI output valid to EECK rising edge time
EECK rising edge to EEDI output delay time
EECS output valid to EECK rising edge time
EECK falling edge to EECS invalid time
Minimum EECS low time
EEDO input setup time
EEDO input hold time
Min
2666
2666
2666
0
23904
10
100
38
Typ
5333
2666
2666
-
Max
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
9.0 Package Information
A
A2
A1
L
L1
D
Hd
He
E
pin 1
e
b
θ
Symbol
Millimeter
Min
Typ
Max
A1
0.05
-
-
A2
1.35
1.40
1.45
A
-
-
1.60
b
0.13
0.18
0.23
D
13.90
14.00
14.10
E
13.90
14.00
14.10
e
-
0.4 BSC
-
Hd
15.85
16.00
16.15
He
15.85
16.00
16.15
L
0.45
0.60
0.75
L1
-
1.00 REF
-
θ
0°
3.5°
7°
39
ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
10.0 Ordering Information
AX88772
Product Name
L
Package LQFP
F
Lead Free
40
ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
Appendix A: System Applications
Some typical applications for AX88772 are illustrated bellow.
A.1 USB to Fast Ethernet Converter
RJ45
Current driver do not
support for this
MAGNETIC
RJ45
10/100 Ethernet PHY
MAGNETIC
AX88772
EEPROM
USB I/F
A.2 USB to Fast Ethernet and/or HomeLAN Combo solution
RJ11
Current driver do
not support for this
MAGNETIC
RJ45
Home LAN PHY
MAGNETIC
AX88772
EEPROM
USB I/F
41
ASIX ELECTRONICS CORPORATION
AX88772
USB to 10/100 Fast Ethernet/HomePNA Controller
Revision History
Revision
Date
Comment
V 0.1
V 0.2
1/5/04
4/16/04
V 0.3
8/9/04
V 0.4
V 0.5
V 0.6
V 0.7
12/23/04
1/6/05
3/23/05
6/21/05
Initial Release.
Added power consumption data and updated pin description for pin
USB_SPEED_LED.
Changed Bulk In transfer to Endpoint 2 and Bulk Out transfer to
Endpoint 3 in section 5.3.
Added thermal data in section 8.2.
Added operating temperature in feature and section 8.1.2.
Added power-up sequence in section 8.3.
Changed the support to 1 USB interface in section 5.2.
4F, No. 8, Hsin Ann Rd., Science-Based Industrial Park,
HsinChu, Taiwan, R.O.C.
TEL: 886-3-5799500
FAX: 886-3-5799558
Email: [email protected]
Web: http://www.asix.com.tw/
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