OPA172 OPA2172 OPA4172 www.ti.com SBOS618 – DECEMBER 2013 36-V, Single-Supply, 10-MHz, Rail-to-Rail Output Operational Amplifiers Check for Samples: OPA172, OPA2172, OPA4172 FEATURES DESCRIPTION • The OPA172, OPA2172 and OPA4172 (OPAx172) are a family of 36-V, single-supply, low-noise operational amplifiers with the ability to operate on supplies ranging from +4.5 V (±2.25 V) to +36 V (±18 V). This latest addition of high voltage CMOS operational amplifiers, in conjunction with the OPAx171 and OPAx170 provide a family of bandwidth, noise, and power options to meet the needs of a wide variety of applications. The OPAx172 are available in micropackages and offer low offset, drift, and quiescent current. These devices also offer wide bandwidth, fast slew rate, and high output current drive capability. The single, dual, and quad versions all have identical specifications for maximum design flexibility. 1 23 • • • • • • • • • • • • • Wide Supply Range: +4.5 V to +36 V, ±2.25 V to ±18 V Low Offset Voltage: ±0.2 mV Low Offset Drift: ±0.3 µV/°C Gain Bandwidth: 10 MHz Low Input Bias Current: ±8 pA Low Quiescent Current: 1.6 mA per Amplifier Low Noise: 6 nV/√Hz EMI and RFI Filtered Inputs Input Range Includes the Negative Supply Input Range Operates to Positive Supply Rail-to-Rail Output High Common-Mode Rejection: 120 dB Industry-Standard Packages: – 8-Pin SOIC – 8-Pin MSOP – 14-Pin SOIC – 14-Pin TSSOP microPackages: – Single in SC-70, SOT-23 Unlike most op amps, which are specified at only one supply voltage, the OPAx172 family is specified from +4.5 V to +36 V. Input signals beyond the supply rails do not cause phase reversal. The input can operate 100 mV below the negative rail and within 2 V of the top rail during normal operation. Note that these devices can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within 2 V of the top rail. The OPAx172 series of op amps are specified from –40°C to +125°C. APPLICATIONS • • • • • • • • • Tracking Amplifier in Power Modules Merchant Power Supplies Transducer Amplifiers Bridge Amplifiers Temperature Measurements Strain Gauge Amplifiers Precision Integrators Battery-Powered Instruments Test Equipment PRODUCT FAMILY DEVICE PACKAGE OPA172 (single) (1) SC-70, SOT23-5, SO-8 OPA2172 (dual) SO-8, MSOP-8 OPA4172 (quad) TSSOP-14, SO-14 AMPLIFIER SELECTION TABLE DEVICE QUIESCENT CURRENT (IQ) GAIN BANDWIDTH (GBW) VOLTAGE NOISE DENSITY (en) OPAx172 1600 µA 10 MHz 6 nV/√Hz OPAx171 475 µA 3.0 MHz 14 nV/√Hz OPAx170 110 µA 1.2 MHz 19 nV/√Hz (1) 1 2 3 OPA172 SO-8 package is production data. All other devices are product preview. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Bluetooth is a registered trademark of Bluetooth SIG, Inc. All other trademarks are the property of their respective owners. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated OPA172 OPA2172 OPA4172 SBOS618 – DECEMBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. Supply voltage Signal input terminals Common-mode Voltage (2) VALUE UNIT ±20 (+40 single supply) V (V–) – 0.5 to (V+) + 0.5 V Differential Current ±0.5 V ±10 mA Output short circuit (3) Continuous Operating temperature –55 to +150 °C Storage temperature –65 to +150 °C Junction temperature +150 °C 4 kV 1 kV Electrostatic Human body model (HBM) discharge (ESD) Charged device model (CDM) ratings: (1) (2) (3) 2 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Transient conditions that exceed these voltage ratings should be current limited to 10 mA or less. Short-circuit to ground, one amplifier per package. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA172 OPA2172 OPA4172 OPA172 OPA2172 OPA4172 www.ti.com SBOS618 – DECEMBER 2013 ELECTRICAL CHARACTERISTICS At TA = +25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS/2, and RL = 10 kΩ connected to VS/2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage ±0.2 Over temperature TA = –40°C to +125°C dVOS/dT Drift TA = –40°C to +125°C PSRR vs power supply TA = –40°C to +125°C ±1 mV ±1.15 mV ±0.3 ±1.5 µV/°C ±1 ±3 µV/V ±8 ±15 pA ±14 nA ±15 pA ±1 nA INPUT BIAS CURRENT IB Input bias current Over temperature IOS TA = –40°C to +125°C Input offset current ±2 Over temperature TA = –40°C to +125°C En Input voltage noise f = 0.1 Hz to 10 Hz 1.2 µVPP en Input voltage noise density f = 100 Hz 8.6 nV/√Hz f = 1 kHz 6 nV/√Hz in Input current noise density f = 1 kHz 1.6 fA/√Hz NOISE INPUT VOLTAGE VCM Common-mode voltage range (1) CMRR Common-mode rejection ratio (V–) – 0.1 V VS = ±2.25 V, (V–) – 0.1 V < VCM < (V+) – 2 V, TA = –40°C to +125°C VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V, TA = –40°C to +125°C (V+) – 2 V V 90 104 dB 110 120 dB INPUT IMPEDANCE Differential 100 || 4 MΩ || pF 6 || 4 1013Ω || pF 130 dB 116 dB 10 MHz 10 V/µs 2 µs To 0.01% (12 bit), VS = ±18 V, G = +1, 10-V step 3.2 µs Overload recovery time VIN × Gain > VS 200 ns Total harmonic distortion + noise VS = +36 V, G = +1, f = 1 kHz, VO = 3.5 VRMS 0.00005 % Common-mode OPEN-LOOP GAIN AOL Open-loop voltage gain (V–) + 0.35 V < VO < (V+) – 0.35 V, RL = 10 kΩ, TA = –40°C to +125°C 110 (V–) + 0.5 V < VO < (V+) – 0.5 V, RL = 2 kΩ, TA = –40°C to +125°C FREQUENCY RESPONSE GBP Gain bandwidth product SR Slew rate tS Settling time THD+N (1) G = +1 To 0.1%, VS = ±18 V, G = +1, 10-V step The input range can be extended beyond (V+) – 2 V up to (V+) + 0.1 V. See the Typical Characteristics and Application Information sections for additional information. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA172 OPA2172 OPA4172 3 OPA172 OPA2172 OPA4172 SBOS618 – DECEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS/2, and RL = 10 kΩ connected to VS/2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT VS = +36 V Voltage output swing from rail VO VS = +4.5V VS = +36 V Over temperature VS = +4.5 V ISC Short-circuit current CLOAD Capacitive load drive ZO Open-loop output impedance RL = 10 kΩ 75 80 mV RL = 2 kΩ 330 400 mV RL = 10 kΩ 10 20 mV RL = 2 kΩ 40 50 mV RL = 10 kΩ 105 110 mV RL = 2 kΩ 480 530 mV RL = 10 kΩ 15 20 mV RL = 2 kΩ 55 70 mV +75/–75 mA See Typical Characteristics f = 1 MHz, IO = 0 A pF Ω 60 POWER SUPPLY VS Specified voltage range IQ Quiescent current per amplifier +4.5 IO = 0 A Over temperature IO = 0 A, TA = –40°C to +125°C 1.6 +36 V 1.8 mA 2 mA TEMPERATURE Specified range –40 +125 °C Operating range –55 +150 °C THERMAL INFORMATION: OPA172 OPA172 THERMAL METRIC (1) D (SO) DBV (SOT23) DCK (SC-70) 8 PINS 5 PINS 5 PINS θJA Junction-to-ambient thermal resistance 126.5 227.9 285.2 θJC(top) Junction-to-case(top) thermal resistance 80.6 115.7 60.5 θJB Junction-to-board thermal resistance 67.1 65.9 78.9 ψJT Junction-to-top characterization parameter 31.0 10.7 0.8 ψJB Junction-to-board characterization parameter 66.6 65.3 77.9 θJC(bottom) Junction-to-case(bottom) thermal resistance N/A N/A N/A (1) 4 UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA172 OPA2172 OPA4172 OPA172 OPA2172 OPA4172 www.ti.com SBOS618 – DECEMBER 2013 PIN CONFIGURATIONS DCK PACKAGE: OPA172 SC-70 (TOP VIEW) IN+ 1 V- 2 IN- 3 5 4 D AND DGK PACKAGES: OPA2172 SO-8 AND MSOP-8 (TOP VIEW) V+ 1 V- 2 +IN 3 NC (1) 1 8 V+ -IN A 2 7 OUT B +IN A 3 6 -IN B V- 4 5 +IN B 5 V+ 4 -IN D AND PW PACKAGES: OPA4172 SO-14 AND TSSOP-14 (TOP VIEW) D PACKAGE: OPA172 SO-8 (TOP VIEW) (1) 1 OUT DBV PACKAGE: OPA172 SOT23-5 (TOP VIEW) OUT OUT A 8 NC(1) -IN 2 7 V+ +IN 3 6 OUT V- 4 5 NC(1) OUT A 1 14 OUT D -IN A 2 13 -IN D +IN A 3 12 +IN D V+ 4 11 V- +IN B 5 10 +IN C -IN B 6 9 -IN C OUT B 7 8 OUT C No internal connection. NOTE: OPA172 D package is production data. All other packages are product preview. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA172 OPA2172 OPA4172 5 OPA172 OPA2172 OPA4172 SBOS618 – DECEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS: TABLE OF GRAPHS Table 1. List of Typical Characteristics 6 DESCRIPTION FIGURE Offset Voltage Production Distribution Figure 1 Offset Voltage Drift Distribution Figure 2 Offset Voltage vs Temperature (VS = ±18 V) Figure 3 Offset Voltage vs Common-Mode Voltage (VS = ±18 V) Figure 4 Offset Voltage vs Common-Mode Voltage (Upper Stage) Figure 5 Offset Voltage vs Power Supply Figure 6 IB vs Common-Mode Voltage Figure 7 Input Bias Current vs Temperature Figure 8 Output Voltage Swing vs Output Current (Maximum Supply) Figure 9 CMRR and PSRR vs Frequency (Referred-to Input) Figure 10 CMRR vs Temperature Figure 11 PSRR vs Temperature Figure 12 0.1-Hz to 10-Hz Noise Figure 13 Input Voltage Noise Spectral Density vs Frequency Figure 14 THD+N Ratio vs Frequency Figure 15 THD+N vs Output Amplitude Figure 16 Quiescent Current vs Temperature Figure 17 Quiescent Current vs Supply Voltage Figure 18 Open-Loop Gain and Phase vs Frequency Figure 19 Closed-Loop Gain vs Frequency Figure 20 Open-Loop Gain vs Temperature Figure 21 Open-Loop Output Impedance vs Frequency Figure 22 Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 23, Figure 24 Positive Overload Recovery Figure 25, Figure 26 Negative Overload Recovery Figure 27, Figure 28 Small-Signal Step Response (10 mV) Figure 29, Figure 30 Small-Signal Step Response (100 mV) Figure 31, Figure 32 Large-Signal Step Response (1 V) Figure 33, Figure 34 Large-Signal Settling Time (10-V Positive Step) Figure 35 Large-Signal Settling Time (10-V Negative Step) Figure 36 No Phase Reversal Figure 37 Short-Circuit Current vs Temperature Figure 38 Maximum Output Voltage vs Frequency Figure 39 EMIRR vs Frequency Figure 40 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA172 OPA2172 OPA4172 OPA172 OPA2172 OPA4172 www.ti.com SBOS618 – DECEMBER 2013 TYPICAL CHARACTERISTICS VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted. 25 Distribution Taken From 47 Amplifiers 1.00 0.90 0.80 0.70 0.60 0.50 0.40 5 0 1.00 0.80 0.60 0.40 0.20 0.00 -0.20 -0.40 -0.60 0 -0.80 5 10 0.30 10 15 0.20 15 Temperature = -40C to 125C 20 0.10 20 0.00 Percentage of Amplifiers (%) Distribution Taken From 5185 Amplifiers -1.00 Percentage of Amplifiers (%) 25 Offset Voltage Drift (µV/C) Offset Voltage (mV) C013 C013 Figure 1. OFFSET VOLTAGE PRODUCTION DISTRIBUTION Figure 2. OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION 250 225 5 Typical Units Shown VS = ±18 V 200 150 100 VOS (V) VOS (V) 0 ±50 VCM =16V VCM = -18.1V 75 50 0 ±75 ±100 ±150 ±150 ±200 ±250 ±75 ±50 ±25 ±225 0 25 50 75 100 125 Temperature (C) 150 ±20 ±15 ±10 0 ±5 5 10 15 VCM (V) C001 Figure 3. OFFSET VOLTAGE vs TEMPERATURE (VS = ±18 V) 20 C001 Figure 4. OFFSET VOLTAGE vs COMMON-MODE VOLTAGE (VS = ±18 V) 500 20 5 Typical Units Shown VS = ±18 V 10 400 Vs = ±2.25V 300 0 5 Typical Units Shown VS = ±2.25V to 18V 200 VOS (V) VOS (mV) 5 Typical Units Shown VS = ±18 V 150 -10 -20 100 0 ±100 ±200 -30 ±300 -40 ±400 ±500 -50 14 15 16 VCM (V) 17 18 0.0 2.0 4.0 Figure 5. Offset Voltage vs Common-Mode Voltage (Upper Stage) 6.0 8.0 10.0 12.0 14.0 16.0 18.0 VSUPPLY (V) C001 C001 Figure 6. OFFSET VOLTAGE vs POWER SUPPLY Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA172 OPA2172 OPA4172 7 OPA172 OPA2172 OPA4172 SBOS618 – DECEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted. 12 8000 6 IbN 4 6000 Input Bias Current (pA) Input Bias Current (pA) 8 2 0 ±2 4000 2000 0 Ios TA = 25°C ±2000 ±4 ±18.0 ±13.5 ±9.0 0.0 ±4.5 4.5 9.0 13.5 ±50 18.0 VCM (V) 25 50 75 100 125 150 C001 Figure 8. INPUT BIAS CURRENT vs TEMPERATURE 160.0 Common-Mode Rejection Ratio (dB), Power-Supply Rejection Ratio (dB) - 40C -18 12 +25°C -18 6 Vout (V) 0 Temperature (C) 18 +85C 18 +125 18 0 -6 +125°C -12 - 40°C 140.0 120.0 100.0 80.0 60.0 +PSRR 40.0 -PSRR 20.0 CMRR 0.0 -18 0 10 20 30 40 50 60 70 80 90 1 100 110 Iout (mA) 10 100 1k 10k 100k Frequency (Hz) C001 Figure 9. OUTPUT VOLTAGE SWING vs OUTPUT CURRENT (Maximum Supply) 1M C012 Figure 10. CMRR AND PSRR vs FREQUENCY (Referred-to-Input) 30 10 20 Power-Supply Rejection Ratio (µV/V) Common-Mode Rejection Ratio (µV/V) ±25 C001 Figure 7. INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE VS = ±2.25V, -99CM 9 10 0 VS = 18 V, -99CM 9 ±10 8 6 4 2 0 ±2 ±75 ±50 ±25 0 25 50 75 100 Temperature (C) Figure 11. CMRR vs TEMPERATURE 8 IB+ IB Ios IbP 10 125 150 ±75 ±50 ±25 0 25 50 75 100 Temperature (C) C001 125 150 C001 Figure 12. PSRR vs TEMPERATURE Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA172 OPA2172 OPA4172 OPA172 OPA2172 OPA4172 www.ti.com SBOS618 – DECEMBER 2013 TYPICAL CHARACTERISTICS (continued) VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted. 400 nV/div 9ROWDJH1RLVH'HQVLW\Q9¥+] 1000 100 10 Peak-to-Peak Noise = 1.20 Vpp 1 Time (1 s/div) 0.1 1 10 Figure 13. 0.1-Hz TO 10-Hz NOISE G = -1 V/V, RL = 10 k -100 G = -1 V/V, RL = 2 k G = -1 V/V, RL = 600 0.0001 -120 VOUT = 3.5 VRMS BW = 80 kHz 0.00001 -140 1k 10k Frequency (Hz) 0.1 Total Harmonic Distortion + Noise (%) Total Harmonic Distortion + Noise (%) G = +1 V/V, RL = 600 100 10k 100k C002 -60 G = +1 V/V, RL = 10 k G = +1 V/V, RL = 2 k G = +1 V/V, RL = 600 G = -1 V/V, RL = 10 k G = -1 V/V, RL = 2 k G = -1 V/V, RL = 600 0.01 -80 0.001 -100 0.0001 -120 f = 1 kHz BW = 80 kHz 0.00001 0.01 0.1 -140 1 10 Output Amplitude (VRMS) C007 Figure 15. THD+N RATIO vs FREQUENCY Total Harmonic Distortion + Noise (dB) G = +1 V/V, RL = 2 k Total Harmonic Distortion + Noise (dB) -80 G = +1 V/V, RL = 10 k 10 1k Figure 14. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY 0.01 0.001 100 Frequency (Hz) C001 C008 Figure 16. THD+N vs OUTPUT AMPLITUDE 2.0 1.8 1.7 1.8 1.6 1.5 IQ (mA) IQ (mA) Vs = ±18V 1.6 Vs = ±2.25V 1.4 1.3 1.4 1.2 1.1 1.2 1.0 ±75 ±50 ±25 0 25 50 75 Temperature (C) 100 125 150 0 4 8 Figure 17. QUIESCENT CURRENT vs TEMPERATURE 12 16 20 24 28 32 Supply Voltage (V) C001 36 C001 Figure 18. QUIESCENT CURRENT vs SUPPLY VOLTAGE Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA172 OPA2172 OPA4172 9 OPA172 OPA2172 OPA4172 SBOS618 – DECEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted. 180 140 25.0 CLOAD = 15 pF 20.0 120 15.0 135 80 Phase 60 90 40 20 10.0 Gain (dB) Open-Loop Gain Phase () Gain (dB) 100 5.0 0.0 ±5.0 45 ±10.0 0 G = +1 G = -10 G = -1 ±15.0 ±20 0 1 10 100 1k 10k 100k 1M ±20.0 1000 10M Frequency (Hz) 10k 100k 1M 10M C004 Frequency (Hz) Figure 19. OPEN-LOOP GAIN AND PHASE vs FREQUENCY 1000 2.0 1.5 AOL (µV/V) C003 Figure 20. CLOSED-LOOP GAIN vs FREQUENCY 100 ZO () 1.0 Vs = 4.5 V 10 0.5 Vs = 36 V 1 0.0 RL = 10k ±0.5 ±75 ±50 0 ±25 0 25 50 75 100 125 10 150 Temperature (C) RI = 1 k + 100M C016 G = +1 40 CL ± 18 V 40 Overshoot (%) Overshoot (%) 10M ROUT + ± 1M 50 OPA172 VIN = 100mV 100k G = -1 + 18 V 50 10k Figure 22. OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY RF = 1 k ± 1k Frequency (Hz) Figure 21. OPEN-LOOP GAIN vs TEMPERATURE 60 100 C001 30 20 20 + 18 V ROUT = 0 10 30 R 25 RO OUT==25 ROUT= 0 10 ± ROUT OPA172 R RO = 25 25 OUT= + VIN = 100mV + RL CL ± 18 V ± R 50 RO OUT==50 0 0p 100p 200p 300p Capacitive Load (F) 400p 500p 0 0p 100p 200p 300p Capacitive Load (F) C013 Figure 23. SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD (100-mV Output Step) 10 RO = 50 50 R OUT= 400p 500p C013 Figure 24. SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD (100-mV Output Step) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA172 OPA2172 OPA4172 OPA172 OPA2172 OPA4172 www.ti.com SBOS618 – DECEMBER 2013 TYPICAL CHARACTERISTICS (continued) VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted. RI = 1 k RF = 10 k + 18 V ± + OPA172 VIN = 2V VOUT + ± VOUT ± 18 V 5 V/div 5 V/div RI = 1 k VOUT RF = 10 k + 18 V ± + OPA172 VIN = 2V VOUT + ± ± 18 V VIN VIN Time (1 s/div) Time (1 s/div) C009 C009 Figure 25. POSITIVE OVERLOAD RECOVERY Figure 26. POSITIVE OVERLOAD RECOVERY (Zoomed In) VIN RI = 1 k VIN RF = 10 k 5 V/div 5 V/div + 18 V VOUT RI = 1 k ± + OPA172 VIN = 2V VOUT + ± ± 18 V RF = 10 k + 18 V VOUT ± + OPA172 VIN = 2V VOUT + ± ± 18 V Time (1 s/div) Time (1 s/div) C010 C010 Figure 27. NEGATIVE OVERLOAD RECOVERY Figure 28. NEGATIVE OVERLOAD RECOVERY (Zoomed In) RL N CL = 10pF + 18 V CL = 10pF ± OPA172 + VIN = 10mV CL ± 18 V 2 mV/div 2 mV/div ± + RI = 1 k RF = 1 k + 18 V + VIN = 10mV ± OPA172 + ± RL CL ± 18 V Time (200 ns/div) Time (200 ns/div) C006 Figure 29. SMALL-SIGNAL STEP RESPONSE (10 mV, G = –1) C014 Figure 30. SMALL-SIGNAL STEP RESPONSE (10 mV, G = +1) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA172 OPA2172 OPA4172 11 OPA172 OPA2172 OPA4172 SBOS618 – DECEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted. + 18 V CL = 10pF RL N CL = 10pF ± OPA172 + + VIN = 100mV 20 mV/div 20 mV/div CL ± 18 V ± RI = 1 k RF = 1 k + 18 V ± + OPA172 VIN = 100mV + ± RL CL ± 18 V Time (200 ns/div) Time (200 ns/div) C006 C014 Figure 31. SMALL-SIGNAL STEP RESPONSE (100 mV, G = –1) Figure 32. SMALL-SIGNAL STEP RESPONSE (100 mV, G = +1) RL N CL = 10 pF + 18 V CL = 10pF ± OPA172 + + VIN = 10V 2 V/div 2 V/div CL ± 18 V ± RI = 1 k RF = 1 k + 18 V ± + OPA172 VIN = 10V + ± RL CL ± 18 V Time (500 ns/div) Time (500 ns/div) C005 C014 Figure 33. LARGE-SIGNAL STEP RESPONSE (10 V, G = –1) Figure 34. LARGE-SIGNAL STEP RESPONSE (10 V, G = +1) 20 G = +1 CL = 10 pF 15 Output Delta from Final Value (mV) Output Delta from Final Value (mV) 20 10 5 0 -5 0.1% Settling = ±10 mV -10 -15 -20 10 5 0 -5 0.1% Settling = ±10 mV -10 -15 -20 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Time (s) 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Time (s) C034 Figure 35. LARGE-SIGNAL SETTLING TIME (10-V Positive Step) 12 G = +1 CL = 10 pF 15 5 C034 Figure 36. LARGE-SIGNAL SETTLING TIME (10-V Negative Step) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA172 OPA2172 OPA4172 OPA172 OPA2172 OPA4172 www.ti.com SBOS618 – DECEMBER 2013 TYPICAL CHARACTERISTICS (continued) VS = ±18 V, VCM = VS/2, RLOAD = 10 kΩ connected to VS/2, and CL = 100 pF, unless otherwise noted. 100 + 18 V ± + ± 37 VPP ± 18 V Sine Wave (±18.5V) VOUT VOUT OPA172 + 75 ISC (mA) 5 V/div ISC, Sink 18V 50 ISC, Source ±18V 25 VIN 0 Time (200 s/div) ±75 ±50 ±25 0 Figure 37. NO PHASE REVERSAL 50 75 100 125 150 C001 Figure 38. SHORT-CIRCUIT CURRENT vs TEMPERATURE 160.0 30 VS = ±15 V 140.0 Maximum output voltage without slew-rate induced distortion. 20 15 VS = ±5 V 10 100.0 80.0 60.0 40.0 VS = ±2.25 V 5 PRF = -10 dBm VSUPPLY = ±18 V VCM = 0 V 120.0 EMIRR IN+ (dB) 25 Output Voltage (VPP) 25 Temperature (C) C011 20.0 0 0.0 10k 100k 1M Frequency (Hz) 10M 10M 100M Figure 39. MAXIMUM OUTPUT VOLTAGE vs FREQUENCY 1G Frequency (Hz) C033 10G C017 Figure 40. EMIRR vs FREQUENCY Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA172 OPA2172 OPA4172 13 OPA172 OPA2172 OPA4172 SBOS618 – DECEMBER 2013 www.ti.com APPLICATION INFORMATION The OPAx172 family of operational amplifiers provide high overall performance, making them ideal for many general-purpose applications. The excellent offset drift of only 1.5 µV/°C (max) provides excellent stability over the entire temperature range. In addition, the device offers very good overall performance with high CMRR, PSRR, AOL and THD. OPERATING CHARACTERISTICS The OPAx172 family of amplifiers is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V). Many of the specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics. EMI REJECTION The OPAx172 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from sources such as wireless communications and densely-populated boards with a mix of analog signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPAx172 benefits from these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure 41 shows the results of this testing on the OPAx172. Table 2 shows the EMIRR IN+ values for the OPAx172 at particular frequencies commonly encountered in real-world applications. Applications listed in Table 2 can be centered on or operated near the particular frequency shown. Detailed information can also be found in Application Report SBOA128, EMI Rejection Ratio of Operational Amplifiers, available for download from www.ti.com. 160.0 140.0 PRF = -10 dBm VSUPPLY = ±18 V VCM = 0 V EMIRR IN+ (dB) 120.0 100.0 80.0 60.0 40.0 20.0 0.0 10M 100M 1G Frequency (Hz) 10G C017 Figure 41. EMIRR Testing Table 2. OPAx172 EMIRR IN+ for Frequencies of Interest 14 FREQUENCY APPLICATION OR ALLOCATION EMIRR IN+ 400 MHz Mobile radio, mobile satellite, space operation, weather, radar, ultrahigh frequency (UHF) applications 47.6 dB 900 MHz Global system for mobile communications (GSM) applications, radio communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications 58.5 dB 1.8 GHz GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) 68 dB 2.4 GHz 802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and medical (ISM) radio band, amateur radio and satellite, Sband (2 GHz to 4 GHz) 69.2 dB 3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 82.9 dB 5.0 GHz 802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite operation, C-band (4 GHz to 8 GHz) 114 dB Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA172 OPA2172 OPA4172 OPA172 OPA2172 OPA4172 www.ti.com SBOS618 – DECEMBER 2013 GENERAL LAYOUT GUIDELINES For best operational performance of the device, good printed circuit board (PCB) layout practices are recommended. Including: • Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable to singlesupply applications. • In order to reduce parasitic coupling, run the input traces as far away from the supply lines as possible. • A ground plane helps distribute heat and reduces EMI noise pickup. • Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring. • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. COMMON-MODE VOLTAGE RANGE The input common-mode voltage range of the OPAx172 series extends 100 mV below the negative rail and within 2 V of the top rail for normal operation. This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within 2 V of the top rail. The typical performance in this range is summarized in Table 3. Table 3. Typical Performance Range (VS = ±18V) PARAMETER MIN Input Common-Mode Voltage TYP (V+) – 2 Offset voltage MAX UNIT (V+) + 0.1 V 5 mV 10 µV/°C Common-mode rejection 70 dB Open-loop gain 60 dB GBW 4 MHz Slew rate 4 V/µs Noise at f = 1 kHz 22 nV/√Hz vs Temperature (TA = –40°C to +125°C) PHASE-REVERSAL PROTECTION The OPAx172 family has an internal phase-reversal protection. Many op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The input of the OPAx172 prevents phase reversal with excessive common-mode voltage. Instead, the output limits into the appropriate rail. This performance is shown in Figure 42. + 18 V ± OPA172 + ± 37 VPP ± 18 V Sine Wave (±18.5V) VOUT VOUT 5 V/div + VIN Time (200 s/div) C011 Figure 42. No Phase Reversal Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA172 OPA2172 OPA4172 15 OPA172 OPA2172 OPA4172 SBOS618 – DECEMBER 2013 www.ti.com CAPACITIVE LOAD AND STABILITY The dynamic characteristics of the OPAx172 have been optimized for commonly-encountered operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT = 50 Ω) in series with the output. Figure 43 and Figure 44 illustrate graphs of small-signal overshoot versus capacitive load for several values of ROUT. Also, refer to Application Bulletin SBOA015 (AB-028), Feedback Plots Define Op Amp AC Performance, available for download from www.ti.com, for details of analysis techniques and application circuits. 60 RI = 1 k RF = 1 k G = -1 + 18 V 50 ± + OPA172 VIN = 100mV + ± Overshoot (%) ROUT CL ± 18 V 40 30 20 ROUT = 0 10 R 25 RO OUT==25 R 50 RO OUT==50 0 0p 100p 200p 300p 400p 500p Capacitive Load (F) C013 Figure 43. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) 50 G = +1 Overshoot (%) 40 30 20 + 18 V ROUT= 0 10 ± ROUT OPA172 R RO = 25 25 OUT= + VIN = 100mV + RL CL ± 18 V ± RO = 50 50 R OUT= 0 0p 100p 200p 300p 400p Capacitive Load (F) 500p C013 Figure 44. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) 16 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA172 OPA2172 OPA4172 OPA172 OPA2172 OPA4172 www.ti.com SBOS618 – DECEMBER 2013 ELECTRICAL OVERSTRESS Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress. These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly. Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful. See Figure 45 for an illustration of the ESD circuits contained in the OPAx172 (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation. TVS + ± RF +VS VDD OPA172 R1 IN- 250 RS IN+ 250 Power supply ESD cell ID VIN RL + ± VSS + ± -VS TVS Figure 45. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse while discharging through a semiconductor device. The ESD protection circuits are designed to provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the protection circuitry is then dissipated as heat. When an ESD voltage develops across two or more amplifier device pins, current flows through one or more steering diodes. Depending on the path that the current takes, the absorption device may activate. The absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPAx172 but below the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates and clamps the voltage across the supply rails to a safe level. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA172 OPA2172 OPA4172 17 OPA172 OPA2172 OPA4172 SBOS618 – DECEMBER 2013 www.ti.com When the operational amplifier connects into a circuit (such as the one Figure 45 depicts), the ESD protection components are intended to remain inactive and do not become involved in the application circuit operation. However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current. Any such current flow occurs through steering-diode paths and rarely involves the absorption device. Figure 45 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (+VS) by 500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that applications limit the input current to 10 mA. If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier, and then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to levels that exceed the operational amplifier absolute maximum ratings. Another common question involves what happens to the amplifier if an input signal is applied to the input while the power supplies +VS or –VS are at 0 V. Again, this question depends on the supply characteristic while at 0 V, or at a level below the input-signal amplitude. If the supplies appear as high impedance, then the operational amplifier supply current can be supplied by the input source through the current-steering diodes. This state is not a normal bias condition; the amplifier most likely will not operate normally. If the supplies are low impedance, then the current through the steering diodes can become quite high. The current level depends on the ability of the input source to deliver current, and any resistance in the input path. If there is any uncertainty about the ability of the supply to absorb this current, add external zener diodes to the supply pins, as shown in Figure 45. Select the zener voltage so that the diode does not turn on during normal operation. However, the zener voltage should be low enough so that the zener diode conducts if the supply pin begins to rise above the safe-operating, supply-voltage level. The OPAx172 input terminals are protected from excessive differential voltage with back-to-back diodes, as shown in Figure 45. In most circuit applications, the input protection circuitry has no effect. However, in low-gain or G = 1 circuits, fast-ramping input signals can forward-bias these diodes because the output of the amplifier cannot respond rapidly enough to the input ramp. If the input signal is fast enough to create this forward-bias condition, limit the input signal current to 10 mA or less. If the input signal current is not inherently limited, an input series resistor can be used to limit the input signal current. This input series resistor degrades the low-noise performance of the OPAx172. Figure 45 shows an example configuration that implements a current-limiting feedback resistor. OVERLOAD RECOVERY Overload recovery is defined as the time it takes for the op amp output to recover from the saturated state to the linear state. The output devices of the op amp enter the saturation region when the output voltage exceeds the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices need time to return back to the normal state. After the charge carriers return back to the equilibrium state, the device begins to slew at the normal slew rate. Thus, the propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time. The overload recovery time for the OPAx172 is approximately 200 ns. 18 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA172 OPA2172 OPA4172 OPA172 OPA2172 OPA4172 www.ti.com SBOS618 – DECEMBER 2013 APPLICATION EXAMPLES The following application examples highlight only a few of the circuits where the OPAx172 can be used. BI-DIRECTIONAL CURRENT SOURCE The improved Howland current pump topology shown in Figure 46 provides excellent performance due to the extremely tight tolerances of the on chip resistors of the INA132. By buffering the output using and OPA172, the output current the circuit is able to deliver is greatly extended. The circuit dc transfer function is show in Equation 1: IOUT = VIN / R1 (1) The OPA172 can also be used as the feedback amplifier because the low bias current will minimize error voltages produced across R1. However, for improved performance, a FET-input device with extremely low offset can be selected, such as the OPA192, OPA140, or OPA188 for the feedback amplifier. 40k 40k SENSE VCC IN- - OUTPUT VIN + + OPA172 + + 40k 40k VEE - REF VCC IN+ INA132 OPA172 R1 + + VEE - I OUT Figure 46. Bidirectional Current Source Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA172 OPA2172 OPA4172 19 OPA172 OPA2172 OPA4172 SBOS618 – DECEMBER 2013 www.ti.com JFET-INPUT LOW-NOISE AMPLIFIER A low-noise composite amplifier can be built adding a low noise JFET pair (Q1 and Q2) as an input preamplifier for the OPA172 as shown in Figure 47. Transistors Q3 and Q4 form a 2-mA current sink that biases each JFET with 1 mA of drain current. Using 3.9-kΩ drain resistors produces a gain of approximately 10 in the input amplifier, making the extremely-low, broadband-noise spectral density of the LSK489 the dominant noise source of the amplifier. The output impedance of the input differential amplifier is large enough that a FET-input amplifier such as the OPA172 provides superior noise performance over bipolar-input amplifiers. The gain of the composite amplifier is given by Equation 2: AV = (1 + R3 / R4 ) (2) R2 3.9k V1 15 R1 3.9k VEE VCC VCC The resistances shown are standard 1% resistor values that produce a gain of approximately 100 (99.26) with 68° of phase margin. Gains less than 10 may require additional compensation methods to provide stability. Seleect low resistor values to minimize the resistor thermal noise contribution to the total output noise. V2 15 VEE OPA172 + VCC Q2 VCC LSK489 R4 11.5 + Q1 R3 1.13k + VO R6 27.4k Q3 MMBT4401 Q4 MMBT4401 R5 300 VEE Figure 47. JFET-Input Low-Noise Amplifier 20 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: OPA172 OPA2172 OPA4172 PACKAGE OPTION ADDENDUM www.ti.com 22-Dec-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) OPA172ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA172 OPA172IDBVR PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OUWQ OPA172IDBVT PREVIEW SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OUWQ OPA172IDCKR PREVIEW SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIU OPA172IDCKT PREVIEW SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SIU OPA172IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA172 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 22-Dec-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jan-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device OPA172IDR Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jan-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA172IDR SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2014, Texas Instruments Incorporated