TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 QUAD INTEGRATED POWER SOURCING EQUIPMENT POWER MANAGER FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • Quad-Port Power Management With Integrated Switches and Sense Resistors Compliant to IEEE 802.3af Standard Operates from a Single 48-V Input Supply Individual Port 15-bit A/D Auto, Semi-Auto and Power Management Operating Modes Controlled Current Ramps for Reduced EMI and Charging of PD's Bulk Capacitance I2C Clock and Oscillator Watchdog Timers Over-Temperature Protection DC and DC Modulated Disconnect Supports Legacy Detection for Non-Compliant PD's Supports AC Disconnect High-Speed 400-kHz I2C Interface Comprehensive Power Management Software Available Operating Temperature Range –40°C to 125°C Ethernet Enterprise Switches Ethernet Hubs SOHO Hubs Ethernet Mid-Spans PSE Injectors DESCRIPTION The TPS2384 is a quad-port power sourcing equipment power manager (PSEPM) and is compliant to the Power-over-Ethernet (PoE) IEEE 802.3af standard. The TPS2384 operates from a single 48-V supply and over a wide temperature range (–40°C to 125°C). The integrated output eliminates two external components per port (FET and sense resistor) and will survive 100-V transients. Four individual 15-bit A/D converters are used to measure port resistance, voltage, current and die temperature making PSE solutions simple and robust. The TPS2384 comes with a comprehensive software solution to meet the most demanding applications which can serve as a core for all PoE system designs. TYPICAL APPLICATION RJ45 Up to 100 m RJ45 of CAT 5 PSE Spare Pair +48 V TPS2384 Optional MSP430 MicroController TPS2375 Singnal Pair SCL SDA - I SDA - O ILIM CLASS DC/DC Converter Singnal Pair +48 V Return Spare Pair Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2007, Texas Instruments Incorporated TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 DESCRIPTION (CONTINUED) The TPS2384 has three internal supply buses (10 V, 6.3 V and 3.3 V) generated from the 48-V input supply. These supplies are used to bias all internal digital and analog circuitry. Each supply has been brought out separately for proper bypassing to insure high performance. The digital supply (3.3 V) is available for powering external loads up to 2 mA. For more demanding loads it is highly recommended to use external buffers to prevent system degradation. When the TPS2384 is initially powered up an internal Power-on-Reset (POR) circuit resets all registers and sets all ports to the off state to ensure that the device is powered up in a known safe operating state. The TPS2384 has three modes of operation; automode (AM), semi-automode (SAM) and power management mode (PMM). • In auto mode the TPS2384 performs discovery, classification and delivery of power autonomously to a compliant PD without the need of a micro-controller. • In semi-automode the TPS2384 operates in automode but users can access the contents of all read status registers and A/D registers through the I2C serial interface. All write control registers are active except for D0 through D3 of Port Control register 1 (Address 0010) for limited port control. The semi-auto mode allows the TPS2384 to detect valid PD's without micro-controller intervention but adds a flexibility to perform power management activities. • Power management mode (with a micro-controller) allows users additional capabilities of discovering non-compliant (legacy) PDs, performing AC Disconnect and advanced power management system control that are based on real time port voltages and currents. All functions in this mode are programmed and controlled through read/write registers over the I2C interface. This allows users complete freedom in detecting and powering devices. A comprehensive software package is available that mates the power of the TPS2384 with the MSP430 micro-controller. TPS2384 integrated output stage provides port power and low-side control. The internal low-side circuitry is designed with internal current sensing so there are no external resistors required. The output design ensures the power switches operate in the fully enhanced mode for low power dissipation. The I2C interface allows easy application of opto-coupler circuitry to maintain Ethernet port isolation when a ground based micro-controller is required. The TPS2384 five address pins (A1–A5) allow the device to be addressed at one of 31 possible I2C addresses. Per-port write registers separately control each port state (discovery, classification, legacy, power up, etc) while the read registers contain status information of the entire process along with parametric values of discovery, classification, and real-time port operating current, voltage and die temperature. The proprietary 15-bit integrating A/D converter is designed to meet the harsh environment where the PSEPM resides. The converter is set for maximum rejection of power line noise allowing it to make accurate measurements of line currents during discovery, classification and power delivery for reliable power management decisions. TheTPS2384 is available in either 64-pin PowerPAD™ down (PAP) or 64-pin PowerPAD™ up (PJD) packages. ORDERING INFORMATION (1) (2) 2 PACKAGED DEVICES (1) TEMPERATURE RANGE TA = TJ TQFP – 64 (PAP) (2) TQFP – 64 (PJD) (2) –40°C to 125°C TPS2384PAP TPS2384PJD The PAP and PJD packages are available taped and reeled. Add R suffix to device type (e.g.TPS2384PAPR) to order quantities of 1000 devices per reel. PAP = PowerPad™ down, PJD = PowerPad™ up. Submit Documentation Feedback TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) VALUE 100 µA V3.3 current sourced 5 mA Applied voltage on CINT#, CT, RBIAS –0.5 to 10 Applied voltage on SCL_I, SDA_I, SDA_O, INTB, A1, A2, A3, A4, A5, MS, PORB, WD_DIS, ALT_A/B, AC_LO, AC_HI –0.5 to 6 Applied voltage on V48, P#, N# –0.5 to 80 TJ Junction operating temperature –40 to 125 Tstg Storage temperature -55 to 150 –55 to 150 Tsol Lead temperature (soldering, 10 sec.) (1) (2) UNIT V10 current sourced V °C 260 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. DISSIPATION RATINGS (1) (1) PACKAGE THERMAL RESISTANCE JUNCTION TO CASE θJC THERMAL RESISTANCE JUNCTION TO AMBIENT θJA PAP 0.38°C/W 21.47°C/W PJD 0.38°C/W 21.47°C/W Thermal Resistance measured using 2-oz copper trace and copper pad solder following layout recommendation in TI Publication PowerPAD Thermally Enhance Package Technical Brief SLMA002. RECOMMENDED OPERATING CONDITIONS PARAMETER VDD Input voltage, V48 TJ Junction temperature MIN TYP MAX 44 48 57 V 125 °C MAX UNIT -40 UNIT ELECTRO STATIC DISCHARGE (ESD) PROTECTION Human body model 1.5 CDM 1 Machine model kV 0.2 ELECTRICAL CHARACTERISTICS V48 = 48 V, RT = 124 kΩ, CT = 220 pF, CINT = 0.027 µF (low leakage), –40°C to 125°C and TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 4 9 12 10 14 UNIT Power Supply V48 quiescent current Off mode (all ports) V48 quiescent current Powered mode (all ports) V10, internal analog supply ILOAD = 0 9.75 10.5 11.5 V3.3, internal digital supply ILOAD = 0 to 3 mA 3 3.3 3.7 V3.3 short circuit current V=0 3 V6.3, internal supply ILOAD = 0 5 6.3 7 V2.5, internal reference supply ILOAD = 0 2.46 2.5 2.54 26 32 Input UVLO Internal POR time out(I2C) After all supplies are good I2C activity is valid Internal POR time out (Port) After all supplies are good Port active to I2C commands Submit Documentation Feedback 12 8 66000 mA V mA V Clock Pulses 3 TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 ELECTRICAL CHARACTERISTICS (continued) V48 = 48 V, RT = 124 kΩ, CT = 220 pF, CINT = 0.027 µF (low leakage), –40°C to 125°C and TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP 400 600 MAX UNIT Port Discovery Port off #P to #N input resistance Discovery open circuit voltage kΩ 22 Discovery 1 voltage loop control 70 µA < IPORT < 3 mA Discovery 2 voltage loop control 70 µA < IPORT < 3 mA Discovery current limit P = N = 48 V Auto-mode discovery resistance acceptance Band 2.8 3 30 4.4 V 8.8 10 4 5 19 26.5 Auto-mode discovery resistance low end rejection 0 15 Auto-mode discovery resistance high end rejection 33 Discovery1,2 A/D conversion scale factor 100 µA < IPORT < 3 mA Discovery1,2 A/D conversion time IPORT= 120 µA 5.30 6.10 mA kΩ 6.75 count/µA ms Port Classification Classification voltage loop controll 100 µA < IPORT < 50 mA 15 17.5 20 Classification current limit P = N = 48 V 50 60 100 V Class 0 to 1 detection threshold 5.5 6.5 7.5 Class 1 to 2 detection threshold 13 14.5 16 Class 2 to 3 detection threshold 21 23 25 Class 3 to 4 detection threshold 31 33 35 Class 4 to 0 detection threshold 45 48 51 375 424 475 Count/m A 18 22 ms 2.6 3.5 4.3 mA 1365 1400 1445 18 22 ms Ω Classification A/D conversion scale factor Classification A/D conversion time IPORT = 50 mA mA Port Legacy Detection Legacy current limit P = N = 48 V Legacy voltage A/D conversion scale factor 100 mV < VPORT < 17.5 V Legacy A/D conversion time 0 V < VPORT < 15 V Count/V Port Powered Mode Port on resistance Over current threshold (ICUT) Output current limit (ILIM) 20 mA < IPORT < 300 mA RBIAS = 124 kΩ, CT = 220 pF, –25 ≤ TJ≤ 105 Disconnect timer current threshold RBIAS = 124 kΩ, CT = 220 pF TMPDO, disconnect detection time RBIAS = 124 kΩ, CT = 220 pF, ILOAD < current threshold 1.3 1.8 375 400 425 450 7.5 300 42.0 42.7 44.0 Port output OV 54 55 56 Over current time out (TOVLD) RBIAS = 124 kΩ, CT = 220 pF 50 75 Short circuit time out (TLIM) RBIAS = 124 kΩ, CT = 220 pF 50 75 Turn--off delay from UV/OV faults RBIAS = 124 kΩ, CT = 220 pF, After port enabled and ramped up Port current A/D conversion scale factor 20 mA < IPORT < 56 V Port curent A/D conversion time IPORT < 300 mA Port voltage A/D conversion time 45 V < VPORT < 56 V Port temperature A/D conversion ms V ms 3 40 Count/m A 31 36.41 18 22 ms 335 353 370 Count/V 18 22 ms (17500 - counts)/16 Submit Documentation Feedback mA 10 400 Port output UV Port voltage A/D conversion scale factor 4 350 °C TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 ELECTRICAL CHARACTERISTICS (continued) V48 = 48 V, RT = 124 kΩ, CT = 220 pF, CINT = 0.027 µF (low leakage), –40°C to 125°C and TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Port Disable Mode Port N voltage P = 48 V 47 V AC LO and AC HI Specification AC_LO, AC_HI – low output voltage 0 0.5 AC_LO – high output voltage 3.0 5.0 AC_HI – high output voltage 5.0 7.0 V Digital I2C DC Specifications SCL, SDA_I, A1–A5 ,WD_DIS, ALTA/B, MS, PORB logic input threshold 1.5 SCL, SDA_I input hysteresis 250 MS, PORB input hysteresis 150 WD_DIS,ALTA/B, MS, PORB input pulldown resistance Input voltage 0.5 to 3 V A1–A5 pull-down current V mV 50 kΩ 10 µA SDA_O logic high leakage Drain = 5 V 100 nA SDA_O logic low ISINK = 10 mA 200 mV INTB logic high leakage Drain = 6 V 10 µA INTB logic low ISINK = 10 mA 200 mV Digital I2C Timing SCL clock frequency Pulse duration 0 SCL high 0.6 SCL low 1.3 Rise time, SCL to SDA 400 kHz 0.300 Fall time, SCL to SDA 0.300 Setup time, SDA to SCL 0.250 Hold time, SCL to SDA 0.300 Bus free time between start and stop 1.3 Setup time, SCL to start condition 0.6 Hold time, start condition to SCL 0.6 Setup time, SCL to stop condition 0.6 Submit Documentation Feedback 0.900 µs 5 TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 TPS2384 SINGLE PORT BLOCK DIAGRAM Diff Amp (Fix Gain) UV/OV Comparators 600 kW Two 8 Bits Status Register Loop Cntri Amp Detect/Class Modes Two 8 Bits Status Register Auto Seq Logic Analog Control Circurty LCA Power Mode Thermal Detector A2D Registers Resistor Voltage Current & Die Temp Max I Thld OVI OVI Thld 6 Submit Documentation Feedback TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 TERMINAL FUNCTIONS TERMINAL NAME NO. PAP I/O DESCRIPTION PDJ Power and Ground V48 60 5 I 48-V input to the device. This supply can have a range of 44 to 57 V. This pin should be decoupled with a 0.1-µF capacitor from V48 to AG1 placed as close to the device as possible. V10 58 7 O 10-V analog supply. The 10-V reference is generated internally and connects to the main internal analog power bus. A 0.1-µF de-coupling capacitor should terminate as close to this node and the AG1 pin as possible. Do not use for an external supply. V6.3 59 6 O 6.3-V analog supply. A 0.1-µF de-coupling capacitor should terminate as close to this pin and the AG1 pin as possible. Do not use for an external supply. V3.3 24 41 O 3.3-V logic supply. The 3.3-V supply is generated internally and connects to the internal logic power bus. A 0.1-µìF de-coupling capacitor should terminate as close to this node and the DG pin as possible. This output can be used as a low current supply to external logic. V2.5 54 11 O 2.5-V reference supply. The V2.5 is generated internally and connects to the internal reference power bus. This pin should not be tied to any external supplies. A 0.1-µF de-coupling capacitor should terminate as close to this node and the RG pin as possible. Do not use for an external supply. AG1 57 8 Analog ground 1. This is the analog ground of the V6.3, V10 and V48 power systems. It should be GND externally tied to the common copper 48-V return plane. This pin should carry the low side of three de-coupling capacitors tied to V48, V10 and V6.3. AG2 61 4 Analog ground 2. This is the analog ground which ties to the substrate and ESD structures of the GND device. It should be externally tied to the common copper 48-V return plane. AG1 and AG2 must be tied together directly for the best noise immunity. DG 23 42 GND Digital ground. This pin connects to the internal logic ground bus. It should be externally tied to the common copper 48-V return plane. RG 56 9 GND Reference ground. This is a precision sense of the external ground plane. The integration capacitor (CINT) and the biasing resistor (RBIAS pin) should be tied to this ground. This ground should also be used to form a printed wiring board ground guard ring around the active node of the integration capacitor (CINT). It should tie to common copper 48-V return plane. Port Analog Signal P1 7 58 I P2 10 55 I P3 39 26 I P4 42 23 I N1 6 59 I N2 11 54 I N3 38 27 I N4 43 22 I RET1 5 60 I RET2 12 53 I RET3 37 28 I RET4 44 21 I CINT1 4 61 I CINT2 13 52 I CINT3 36 29 I CINT4 45 20 I Port Positive. 48-V load sense pin. Terminal voltage is monitored and controlled differentially with respect to each Port N pin. Optionally, if the application warrants, this high-side path can be protected with the use of a self-resetting poly fuse. Port negative. 48-V load return pin. The low side of the load is switched and protected by internal circuitry that limits the current. 48 V return pin. Integration capacitor This capacitor is used for the ramp A/D converter signal integration. Connect A 0.027- µF capacitor from this pin to RG. To minimize errors use a polycarbonate, poly-polypropylene, polystyrene or teflon capacitor type to prevent leakage. Other types of capacitors can be used with increased conversion error. Submit Documentation Feedback 7 TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. PAP I/O DESCRIPTION PDJ Analog Signals This is a dual-purpose pin. When tied to an external capacitor this pin sets the internal clock. When the CT pin is grounded the SYN pin turns from a output to an input (see SYN pin description). CT 53 12 I The timing capacitor and the resistor on the RBIAS pin sets the internal clock frequency of the device. This internal clock is used for the internal state machine, integrating A/D counters, POR time out, faults and delay timers of each port. Using a 220-pF capacitor for CT and a 124-kΩ resistor for RBIAS sets the internal clock to 245 kHz and ensure IEEE 802.3af compliance along with maximizing the rejection of 60-Hz line frequency noise from A/D measurements. RBIAS 55 10 I Bias set resistor. This resistor sets all precision bias currents within the chip. This pin will regulate to 1.25V (V2.5/2) when a resistor is connected between RBIAS and RG. This voltage and RBIAS generate a current which is replicated and used throughout the chip. This resistor also works in conjunction with the capacitors on CT and CINT to set internal timing values. The RBIAS resistor should be connected RG. RBIAS is a high impedance input and care needs to be taken to avoid signal injection from the SYN pin or I2C signals. SYN 52 13 I/O This is a dual purpose pin. When the CT pin is connected to a timing capacitor this output pin is a 0 V to 3.3V pulse of the internal clock which can be used to drive other TPS2384 SYN pins for elimination of a timing capacitor. When the CT pin is grounded this pin becomes an input pin that can be driven from a master TPS2384 or any other clock generator signal. AC_LO 51 14 O Totem-pole output pin for AC Disconnect excitation. AC_HI 50 15 O Totem-pole output pin for AC Disconnect excitation. Digital Signals SCL 25 40 I Serial clock input pin for the I2C interface. SDA_I 26 39 I Serial data input pin for the I2C interface. When tied to the SDA_O pin, this connection becomes the standard bi-directional serial data line (SDA) SDA_O 27 38 O Serial data open drain output for the I2C interface. When tied to the SDA_I pin, this connection becomes the standard bi-directional serial data line (SDA). This is a open drain output that can directly drive opto-coupler. WD_DIS 22 43 I The WD_DIS pin disables the watchdog timer function when connected to 3.3 V. The pin has internal 50-kΩ resistor to digital ground. The watchdog timer monitors the I2C clock pin (SCL) and the internal oscillator activity in power management mode and only the internal oscillator activity in auto mode. INTB 20 45 O This is an open-drain output that goes low if a fault condition occurs on any of the 4 ports. ALTA/B 21 44 I When this input is set to logic low there is no back-off time after a discovery failure. When this pin set to a logic high there is a back-off time (approximately 2 seconds) before initiating another discovery cycle. This pin has an internal 50-kΩ resistor pull-down to digital ground. A1 28 37 I A2 29 36 I A3 30 35 I A4 31 34 I A5 32 33 I MS PORB 8 63 62 2 3 Address 1 through 5 These are the I2C address select inputs. Select the appropriate binary address on these pins by connecting to chip ground for a logic low or tying to the V3.3 pin for a logic high. Each address line has an internal current source pull-down to digital ground. I The MS pin selects either the auto mode (MS low) or the power management mode, PMM, (MS high). This pin can be held low for controller-less standalone applications. When MS is low and the POR timing cycle is complete the chip will sequentially Discover, Classify and Power on each port. When MS is set high the ports are controlled by register setting via the I2C bus. The MS pin has an internal 50-kΩ resistor pull-down to analog ground. I This pin can be used to override the internal POR. When held low, the I2C interface, all the state machines, and registers are held in reset. When all internal and external supplies are within specification, and this pin is set to a logic high level, the POR delay will begin. The I2C interface and registers will become active within 70 µs of this event and communications to read or preset registers can begin. The reset delay for the remainder of the chip then extinguishes in 1 second. This pin has an internal 50-kΩ resistor pull-down to analog ground. Submit Documentation Feedback TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 CONNECTION DIAGRAM TPS2384 64 Pin Power Pad TQFP_PAP (1) NIC = No internal connection. Pins are floating. (2) NIC pins can be tied to the ground plane for improved thermal characteristics and to prevent noise injection from unused pins. (3) NIC pins next to CINT pins should be tied to ground to prevent noise injection into A/D converter. Submit Documentation Feedback 9 TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 POWERPAD OUTLINE LASER MARKER PIN 1 IDENTIFIER TOP VIEW TPS2384 64 PIN POWER PAD UP TQFP - PJD 10 (1) NIC = No internal connection. Pins are floating. (2) NIC pins can be tied to the ground plane for improved thermal characteristics and to prevent noise injection from unused pins. (3) NIC pins next to CINT pins should be tied to ground to prevent noise injection into A/D converter. Submit Documentation Feedback TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 AUTO MODE FUNCTIONAL DESCRIPTION Auto Mode Auto mode (AM, MS = 0) operation is the basic approach for applying power to IEEE compliant PD’s. When AM has been selected the TPS2384 automatically performs the following functions: • Discovery of IEEE 802.3af compliant powered devices (PD's) • Classification • Power delivery • Port over/under voltage detection • Port over current detection (350 mA < IPORT < 400 mA • Port maximum current limit (400 mA < IPORT < 450 mA) • DC Disconnect (5 mA < IPORT < 10 mA) • Thermal shutdown protection (TSD), (TJ > 150°C) • Internal oscillator watchdog In AM the contents of all read registers are available via the I2C interface. In addition all control registers except for the function bits can be written. This supports a semi-automode where the TPS2384 auto detects compliant PD's while a host can access the A/D registers and class information and then implement power management (including turning a port off, responding to faults, etc). The write registers that are still active in AM are: • All ports disable – Common Control register 0001b • Over/Under Voltage Faults – Common Control register 0001b • Software reset – Common Control register 0001b • Disconnect disable – Port Control 1 register 0010b • Discovery fault disable – Port Control 1 register 0010b • Port enable – Port Control 2 register 0011b For Alternative B, semi-auto mode implementations which will manipulate the all Ports Disable or Port Enable bits, please contact the factory for additional application information. Submit Documentation Feedback 11 TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) Auto Mode Functional Description Update Class Register PortPwr Update Reg OVI = Over Current Fault U/O V = Under or Over Voltage Fault TSD = Thermal Shutdown Fault TMPDO = PD Maintain Power Dropout Time Limit TED = Error Delay Timing A2D V/I Measurements Figure 1. The Basic Flow for Auto Mode 12 Submit Documentation Feedback 300 ms <tMPDO<400 ms TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) AM Discovery The TPS2384 uses a four-point measurment technique using two low level probe signals (typically 4.4 V and 8.8 V) during the discovery process to determine whether a valid PD is present. The use of a multipoint detection method for the PD resistor measurement allows accurate detection even when series steering diodes are present. The low level probe voltages also prevent damage to non-802.3 devices. When a valid PD has been detected the TPS2384 moves to classification. If a valid PD has not been detected the TPS2384 continues to cycle through the discovery process. The waveform in Figure 2 shows typical N-pin waveforms for the discovery of a valid PD and the failure to discovery due to a discovery resistor of 15 kΩ and 33 kΩ. Figure 2. Submit Documentation Feedback 13 TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) AM Classification After a successful discovery of a valid PD theTPS2384 enters the classification function that identifies the power level based on the PD's current signature. The classification current level is measured at a reduced terminal voltage of 17.5 V. During classification the power dissipation can be at its highest; therefore, to prevent over temperature shutdown in auto mode only one port classifies at a time. When multiple ports successfully discover and proceed to classification at the same time the auto sequencer processes each request separately allowing only one port to enter classification. Figure 3 shows all 4 ports successfully detecting a valid PD at the same time and than the classification of each port occurring separately. Figure 3. 14 Submit Documentation Feedback TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) Upon completion of classification the port classification register is updated. In AM mode this information is not used but for semi-auto mode the class information can be used for power management. Figure 4 shows actual class currents and the class assignment which were stored in the register. These assignments are compliant with the IEEE 802.3af Standard 4 0 or 1 1 0 or 1 or 2 0 or 2 or 3 2 3 2 1 0 0 10 20 30 40 50 60 Figure 4. Submit Documentation Feedback 15 TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) AM Power Delivery After successfully discovery and classification of a valid PD the power is delivered by controlling the current to the PD until its current requirements are met or until the internal current limit is reached (approximately 425 mA). The power switch is fully enhanced after 500 µs. Figure 5 show the voltage and the current that is being applied to the PD during power-up and reaching the PD load of 250 mA. Figure 5. After power has been applied to the PD the TPS2384 automatically enters the current and voltage sample mode. The sample mode performs 31 current measurements and 1 voltage measurement. Each measurement takes approximately 18 ms to complete. The port remains powered and the current/voltage measurement cycle continues until a fault condition occurs. The current and voltage measurements are both stored in the A/D current and voltage registers and can be accessed through the I2C pins. This allows power management in the AM if it is desired. AM Faults and INTB Output AM faults are: • Port under and over voltage faults • Over current faults • Under current (DC Disconnect) fault • Thermal shutdown (TSD) fault • Watchdog timer faults (disabled via WD_DIS pin) Any one of the first four fault conditions listed above causes the port to shut down, and a 3-bit fault code to be latched into the affected port's Status Read 1 register (addr = 0100b). Watchdog faults cause all four ports to shut down. Faulted ports are temporarily disabled after a fault has been detected and latched. The INTB pin is an open-drain, active-low output which is asserted if a fault condition occurs on any of the four ports. This indication is asserted for any of the port faults which result in a code displayed in the port status register (the faults listed in Table 8). In automode, the fault latch, the status register fault bits, and consequently, INTB assertion, are cleared by expiration of the 750-ms TED timer. 16 Submit Documentation Feedback TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) Over/Under Voltage Fault Over/under voltage faults are only processed after port powerup has completed (voltage/power ramp to PD is done). The TPS2384 measures the voltage between the P and N pin and if this voltage drops below the under voltage threshold (typically 43 V) or increases above the over voltage threshold (typically 55 V) the voltage timer is turned on. When the voltage timer reaches its time-out limit that is set between 2 ms to 5 ms the corresponding port is turned off and the UV/OV fault code generated in the Port Status 1 register. If the over/under voltage condition is removed prior to the voltage timer reaching its limit the timer is reset and waits for the next event. Figure 6 shows a voltage fault lasting for more then 2 ms that has caused the port to shutdown. Figure 6. Submit Documentation Feedback 17 TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) Over Current or Current Limit Faults Over current or current limit faults are conditions when the load current that is being sensed trips either the ICUT comparator (350 mA to 400 mA) or the ILIM comparator (400 mA to 450 mA) and turns on the current fault timer. When the over current timer reaches its time out limit that is set between 50 ms to 75 ms the corresponding port is turned off and the over current fault code generated in the Port Status 1 register. If the over current condition goes away prior to the over current timer reaching its limit the timer is reset and waits for the next event. Figure 7 shows an over current fault lasting more than 50 ms that has caused the port to shut off. Figure 7. 18 Submit Documentation Feedback TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) Under Current Fault (DC Modulated Disconnect) Under current fault (dc modulated disconnect) is a condition when the load current that is being measured drops below 7.5 mA and turns on the disconnect timer. If the disconnect timer reaches its time out limit that is set between 300 ms to 400 ms the corresponding port is turned off and the load disconnect fault code generated in the Port Status 1 register. If the under current condition goes away prior to the disconnect timer reaching its limit the timer is reset and the port remains powered. Figure 8 shows DC Disconnect event. In this setup the load current was set right above the 7.5-mA threshold. The duty cycle of the load was then adjusted until the off period exceeded the disconnect time out, causing turn-off of the port. The time-out period was > 300 ms. Figure 8. Submit Documentation Feedback 19 TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION Power Management Mode (PMM) Power management mode (PMM) has been designed to work efficiently with simple low-cost microcontrollers such as those in the MSP430 family. The power management mode uses 13 self-contained functions to completely control the device operation. You simply write/read through the I2C pins and wait for the function done bit to be set. If an A/D measurement was performed during the function the results can be accessed by going to the read mode and addressing the proper register. 13 Funcitons • • • • • • • • • • • • • 20 Disable: Disable the port and reset all functions. Discovery 1: Enable the Discovery 1 condition which applies a 4.4 V across the PD and measure and store the resulting current. Discovery 2: Enable the Discovery 2 condition which applies a 8.8 V across the PD and measure and store the resulting current. V Sample: Measure the voltage between the P and N pins and store the result in the A/D voltage register. Legacy: Enable the 3.5-mA current source for measuring capacitance and measure the voltage across the P and N terminals and store the result in the A/D voltage register. Classify: Enable the classification condition which applies 17.7 V across the PD and measure and store the resulting current. Rup Pwr: Turn on the output switch while controlling the current being delivered to the PD until the PD current needs are met or the max current is reached. C Sample: Continuous cycle of 31 current measurements and 1 voltage measurement. After each measurement the contents of the appropriate register are updated. Rdwn: Turn off the output switch while controlling current until output current reaches 0 mA. AC LO: Turns on low side output FET and measures voltage between P and N pin and store result in A/D voltage registers. AC HI: Turns on high side output FET and measures voltage between P and N pin and store result in A/D voltage registers. ISample: Measure the current and store the result in the A/D current register. TSample: Measure the internal die temperature and store the result in the A/D temperature register. Conversion times for A/D measurements performed as part of the functions listed above are generally as shown in the typical values in the Electrical Characteristics table. However, conversion time is somewhat dependant on the magnitude of the input signal being measured. Power management mode applications should take precautions to test the A/D DONE bit (MSB of the high byte) of the pertinent results register before accepting or using the returned value. A logic 1 at this bit location indicates the conversion is complete. Also, once an A/D conversion is in process on a given port, subsequent function calls to that port should wait until the currently executing conversion is complete. Commands written prior to completion may cause the results of the initial conversion to be written to the register of the subsequent function. Submit Documentation Feedback Wait for Next Function Call Set Done Bit Submit Documentation Feedback Set Done Bit Wait for Next Function Call Set Done Bit Store Value Discovery I Reg Store Value Discovery I Reg Wait for Next Function Call 4 ms Delay Start A2D Measure Chnl I (18mS) 4mSDelay Start A2D Measure Chnl I (18mS) Apply 8.8V (Imax5mA) To Chnl Apply 4.4V (Imax5mA) To Chnl Enable Control Enable Control Power Down Reset all Functions Discover 2 0010 Discover 1 0001 Disable 0000 Wait for Next Function Call Set Done Bit Store Value V Reg Set Done Bit Wait for Next Function Call Wait for Next Function Call Store Value I Reg Apply 18V (Imax 100mA) To Chnl Measure Chnl I (18mS) Enable Control Classify 0101 Set Done Bit Store Value V Reg Measure Chnl V (18mS) Apply 2.5mA (Vmax 18) to Chnl Enable Control Enable Diff Amp Av 0.107 Measure Chnl V (18 ms) Legacy 0100 V Sample 0011 Wait for Next Function Call Set Done Bit Enable OVR I , Ovr V & Und V Comparators Latch State Power On RampPwr 1.4A/mSec Rup/Pwr 0110 Decoder Control Register I2C Wait for Next Function Call If 0111 Repeat Set Done Bit Clear On Read Measure Chnl V (1 Sample) Store Value V Reg Measure Chnl I (31 Samples) Store Value I Reg C Sample 0111 Wait for Next Function Call Set Done Bit Pwr Off Ramp Down Rdwn 1000 Wait for Next Function Call Wait for Next Function Call Set Done Bit Store Value V Reg Store Value V Reg Set Done Bit Measure Chnl V (18mS) Apply AC HI Voltage AC HI 1010 Measure Chnl V (18mS) Apply AC LOVoltage AC LO 1001 I Sample 1011 Wait for Next Function Call Set Done Bit Measure Chnl I (18mS) Notes: 1. Each Function State remains set until a new function is called. Example Function 1 - Port Voltage remains at 4.4 V and Resistor Register value is held. 2. Times shown are typical and set by RBIAS , and C T . 3. Poll for and verify A/D done indication prior to sending next function call. T Sample 1100 Wait for Next Function Call Set Done Bit Store Value Temp Reg Measure Die Temperature (18mS) www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 TPS2384 POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION (continued) Figure 9. 21 TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION (continued) PMM Discovery 1 PMM Discovery 1 function waveforms for the N and CINT pins are shown in Figure 10. The measurement is being performed using 25-kΩ impedance between the P and N pin. The Discovery 1 voltage is allowed to settle for approximately 5 ms before the A/D begins integrating. The voltage on the CINT pin shows the A/D cycle. There are four distinct regions to any A/D cycle: precharge (to a known starting voltage), charge, coarse discharge, and fine discharge. CINT pin is very high impedance therefore extreme care must be taken to avoid any noise or leakage affecting this pin. For the measurements where CINT voltage is shown a buffer was used to prevent performance degradation. The A/D measurement time is approximately 18 ms. The entire Discovery 1 function takes approximately 22 ms to complete. At the end of the A/D cycle the Discovery 1 current is stored in the Discovery Current Register and the function done bit is set. The applied Discovery 1 voltage level remains until a new function is called. The data for this measurement remains stored in the Discovery Current Register until another Discovery 1 or 2 function is called. Figure 10. 22 Submit Documentation Feedback TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION (continued) PMM Discovery 2 PMM Discovery 2 function waveforms for the N and CINT pins are shown in Figure 11. Again the measurement is being performed using 25 kΩ impedance between the P and N pin. The Discovery 2 function was called after a Discovery 1 function so the voltage ramps from 4.4 V to 8.8 V below the P pin. The Discovery 2 voltage is given 5 ms to settle before the A/D begins to integrate. At the end of the A/D cycle the Discovery 2 current is stored in the Port Discovery Current Register and the function done bit is set. The applied Discovery 2 voltage level remains until a new function is called. The data for this measurement remains stored in the Discovery Current Register until another Discovery 1 or 2 function is called. Figure 11. Submit Documentation Feedback 23 TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION (continued) PMM Classification PMM Classification function looks similar to Discovery 1 and 2 except that the voltage between the P and N pins regulates to approximately 17.5 V. At the end of the A/D cycle the classification current is stored in the Port Current Register and the done bit is set. The applied classification level remains until a new function is called. The data for this measurement remains stored in the Port Current Register until either the Classify or ISample function is called. As indicated in the flow diagram of Figure 1, the TPS2384 in AM only performs classification at one port at a time. Similarly, PMM applications should take care to ensure that only one port per device is put into the classification mode at any one time to limit power dissipation in the package. PMM Legacy PMM Legacy function is used to detect PDs that are non compliant. Legacy detection uses a current source (typically 3.5 mA) as a test current while the A/D measures the average voltage for approximately 18 ms. The waveform shown in Figure 12 is the Legacy function charging a 10-µF capacitor. The capacitance charges to a value that is no greater than 20 V below the P port voltage. As the capacitor is charging the A/D is accumulating counts in the voltage A/D register. Figure 13 shows the relationship between port capacitance and the number of counts. A user can characterize non-compliant PD's signatures and use the Legacy function to recognize these devices. 5000 4500 4000 3500 Count 3000 2500 2000 1500 1000 500 y = 478x - 1.0133 0 0 10 20 30 40 50 60 70 Capacitor - mF Figure 12. 24 Figure 13. Submit Documentation Feedback 80 90 100 110 TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION (continued) PMM Rup Pwru PMM Rup Pwr function turns on the port power by ramping up the current that is being delivered to the load in a controlled fashion. The output current ramps from 0 mA to ILIM (typically 425 mA) in approximately 500 µs. Figure 14 shows the output voltage and current turning on for a 250-mA load. Figure 14. Submit Documentation Feedback 25 TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION (continued) PMM RDWN PMM RDWN function turns off the port power by ramping down the current in a controlled fashion. The output current ramps from ILIM (typically 425 mA) to 0 mA in approximately 300 µs. Figure 15 shows the output voltage and current shutting down for a 250-mA load. t - Time - 100 ms/div Figure 15. 26 Submit Documentation Feedback TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 MISCELLANEOUS FUNCTIONAL DESCRIPTION PMM Faults PMM faults are the same as those shown in the AM Faults and INTB Output section. In PM mode, the port under- and overvoltage and under-current faults can be disabled by writing to the control bits in the appropriate register. Monitoring for these fault conditions is enabled by default after device POR or other reset operation. The enable state of these features can be toggled by writing to the corresponding control bit as defined below and in Table 4 and Table 5. The PMM faults are: • Port under- and over-voltage faults (disable via Common Control register 0001b, bit D2) • Overcurrent fault (cannot be disabled) • Under-current (DC Disconnect) fault (disable via Port Control register 0010b, bit D4) • Thermal shutdown (TSD) fault (cannot be disabled) • Watchdog fault (disable via WD_DIS pin) Any one of these faults causes the port to shutdown. Once a fault has occurred the port can not be repowered until a Disable function is sent. The Disable function clears the fault latch and the fault register. INTB pin operation is essentially the same in PMM as in AM, with the following exceptions: • For load under-current to generate a fault shutdown and status indication, the condition of load current less than the threshold must be detected by the continuous sample (C_SAMPLE) function (0111b). • In PMM only, a Watchdog timer fault also asserts INTB. Watchdog Timer TPS2384 has two watchdog timers. One monitors the I2C clock and the other monitors the internal clock. When automode is selected and the watchdog timer has not been disabled only the internal clock ismonitored. When in power management mode and the watchdog timer has not been disabled then both the I2C and internal clocks are monitored. If there is no I2C clock activity for approximately two seconds then all ports are disabled. There are three means to enable ports after a I2C clock fault and they are: 1. Hard power reset 2. PORB pulse 3. Writing a software reset to the Common Control register In both auto mode and power management mode if the internal oscillator is lost for more than 20 ms all ports are disabled. Loss of these signals is considered catastrophic since the system loses its ability to talk to each port. Therefore the watchdog timers disabling all ports protects the system. This function can be easily over ridden by setting the WD_DIS pin high. Submit Documentation Feedback 27 TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 I2C Interface Description The serial interface used in the TPS2384 is a standard 2-wire I2C slave architecture. The standard SDA line of the I2C architecture is broken out into independent input and output data paths. This feature simplifies earth grounded controller applications that require opto-isolators to keep the 48-V return of the Ethernet power system floating. For applications where opto-isolation is not required, the bidirectional property of the SDA line can be restored by connecting SDA_I to SDA_O. The SCL line is a unidirectional input only line as the TPS2384 is always accessed as a slave device and it never masters the bus. Data transfers that require a data-flow reversal on the SDA line are 4-byte operations. This occurs during a TPS2384 port read cycle where a slave address byte is sent, followed by a port/register address byte write. A second slave address byte is sent followed by the data byte read using the port/register setup from the second byte in the sequence. The I2C interface and the port read write registers are held in active reset until all input voltages are within specifications (V10, V6.3, V3.3 and V2.5) and the internal POR timer has timed out (see electrical specifications). The I2C read cycle consists of the following steps 1 through 14 and is shown in Figure 16: 1. Start Sequence (S) 2. Device address field 3. Write 4. Acknowledge 5. Register/Port address 6. Acknowledge 7. Stop 8. Start 9. Device address field 10. Read 11. Acknowledge 12. Data Transfer 13. Acknowledge 14. Stop Data write transfers to the TPS2384 do not require a data-flow reversal and as such only a 3-byte operation is required. The sequence in this case would be to send a slave device address byte, followed by a write of the port/register address followed by a write of the data byte for the addressed port. The I2C write cycle consists of the following steps 1 through 9 and is also shown in Figure 16: 1. Start Sequence (S) 2. Device address field 3. Write 4. Acknowledge 5. Register/Port address 6. Acknowledge 7. Data for TPS2384 8. Acknowledge 9. Stop 28 Submit Documentation Feedback TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 Start/Stop The high-to-low transition of SDA_I while SCL is high defines the start condition. The low to high transition of SDA_I while SCL is high defines the stop condition. The master device initiates all start and stop conditions. The first serial packet is enclosed within start and stop bits, consists of a 7-bit address field, read/write bit, and the acknowledge bit. The acknowledge bit is always generated by the device receiving the address or data field. Five of the seven address bits are used by the TPS2384. The value of the sixth and seventh bit is ignored and not used by the TPS2384. Chip Address The address field of the TPS2384 is 8 bits long and contains 5 bits of device address select and a read/write bit as and two spare bits per Table 1. The leading two bits are not used and are reserved for future port expansion. The five device address select bits follow this plan. These bits are compared against the hard-wired state of the corresponding device address select pins (A1–A5). When the field contents are equivalent to the pin logic states, the device is addressed. These bits are followed by LSB bit, which is used to set the read or write condition (1 for read and 0 for write). Following a start condition and an address field, the TPS2384 responds with an acknowledge by pulling the SDA_O line low during the 9th clock cycle if the address field is equivalent to the value programmed by the pins. The SDA_O line remains a stable low while the 9th clock pulse is high. START/STOP SEQUENCE SCL STOP CONDITION(P) Clock Data 1 Value R/W Bit Clock Data 0 Value Clock Data 1 Value START CONDITION(S) Clock Data 1 Value SDA Write Cycle SDA_I A0 D7 R3 R2 R1 R0 D2 P1 P0 Ack Bit Register/Port Address D7 D6 D5 D4 D3 D2 D1 D0 Data from Master to TPS2384 R/W Bit R/W Bit Read Cycle A5 A4 A3 A2 A1 DeviceAddress R/W=0 A0 D7 R3 R2 R1 R0 D2 P1 Register/Port Address P0 A7 Start Bit A6 Ack Bit Start Bit SDA_O A7 Ack Bit SDA_I A6 A5 A4 A3 A2 DeviceAddress R/W=1 A1 A0 Data from TPS2384to Master D7 D6 D5 D4 D3 D2 Stop Bit A1 Ack Bit A2 Ack Bit A3 Stop Bit A4 Ack Bit A5 DeviceAddress R/W=0 Start Bit SDA_O A6 Ack Bit A7 D1 D0 Figure 16. I2C Read/Write Cycles Submit Documentation Feedback 29 TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 Chip Addressing Table 1 shows the bit assignments during the addressing cycle. Table 1. Address Selection Field BIT FUNCTION A7 Future expansion (value not compared) A6 Future expansion (value not compared) A5 Device address. Compared with pin A5 A4 Device address. Compared with pin A4 A3 Device address. Compared with pin A3 A2 Device address. Compared with pin A2 A1 Device address LSB. Compared with pin A1 A0 Read/Write Port/Register Cycle After the chip address cycle, the TPS2384 accepts eight bits of port/register select data as defined in Table 2. The SCL line high-to-low transition after the eighth data bit then latches the selection of the appropriate internal register for the follow-on data read or write operation. After latching the eight-bit data field, the TPS2384 pulls the SDA_O line low for one clock cycle, for the acknowledge pulse. Data Write Cycle For a data write sequence, after the Port/Register address cycle, the TPS2384 accepts the eight bits of data as defined in the tables below. The data is latched into the previously selectedWrite Register, and the TPS2384 generates a data acknowledge pulse by pulling the SDA_O line low for one clock cycle. Common register functions act on all ports simultaneously. Per port registers are specific to the target port only. To reset the interface, the host or master subsequently generates a stop bit by releasing the SDA_I line during the clock-high portion of an SCL pulse. Data Read Cycle For a data read sequence, after the register acknowledge bit, themaster device generates a stop condition. This is followed by a second start condition, and retransmitting the device address as described in chip address above. For this cycle, however, the R/W bit is set to a 1 to signal the read operation. The TPS2384 again responds with an acknowledge pulse. The address acknowledge is then followed by sequentially presenting each of the eight data bits on the SDA_O line (MSB first), to be read by the host device on the rising edges of SCL. After eight bits are transmitted, the host acknowledges by pulling the SDA_I line high for one clock pulse. The completed data transfer is terminated with the host generating a stop condition. 30 Submit Documentation Feedback TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 Table 2. Register/Port Addressing Map BIT FUNCTION STATE D7 Unused 0 D6 Register select MSB D5 Register select Bit 2 D4 Register select Bit 1 0000 = Common Read — Port fault status, chip ID and rev. 0001 = Common Control Write — Software reset, ports disable and AC Disc. 0010 = Port Control Write 1 — Function calls; misc. fault disables 0011 = Port Control Write 2 — Port enable; A/D control 0100 = Port Status Read 1 — Fault status; device Class info. 0101 = Port Status Read 2 — Function and other status 0110 = Discovery Current – Lower Bits — A/D resistance results 0111 = Discovery Current – Upper Bits — A/D resistance results 1000 = Voltage – Lower Bits – A/D voltage results 1001 = Voltage – Upper Bits — A/D voltage results 1010 = Current – Lower Bits — A/D current results 1011 = Current – Upper Bits — A/D current results 1100 = Temperature – Lower Bits — A/D temperature results 1101 = Temperature – Upper Bits — A/D temperature results 1110 = unused 1111 = Common Write – Test mode selections — timer disables, discovery control, etc. PRESET STATE 0 D3 Register select LSB D2 Unused 0 D1 Port address MSB D0 Port address LSB 00 = 01 = 10 = 11 = 0000 0 port port port port 1 2 3 4 00 Table 3. Common Read, Register Select = 0000 BIT FUNCTION PRESET STATE D7 Port 4 general Fault status 0 = no fault 1 = port fault (1) (2) 0 D6 Port 3 general Fault status 0 = no fault 1 = port fault(1) (2) 0 D5 Port 2 general Fault status 0 = no fault 1 = port fault (1) (2) 0 D4 Port 1 general Fault status 0 = no fault 1 = port fault (1) (2) 0 Chip rev 00 = 01 = 10 = 11 = Chip ID 00 = TPS23841 01= future use 10 = TPS2384 11 = reserved D3 D2 D1 D0 (1) (2) STATE rev rev rev rev -1 2 3 Varies 10 PMM faults cleared by Disable function. AM faults cleared by TED timer. Submit Documentation Feedback 31 TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 Table 4. Common Write, Register Select = 1111 (Test Register) (1) BIT D7 (1) FUNCTION STATE PRESET STATE Unused 0 0 D6 Thermal shutdown test 0 = normal operation 1 = force TSD condition (all ports off) 0 D5 POR disable 0 = normal POR timing 1 = force POR to a non-reset state 0 D4 Discovery timers 0 = normal (4-ms Discovery 1 and Discovery 2) 1 = timers disable 0 D3 Discovery 1 and 2 0 = normal operation 1 = all 4-port Discovery 1 and Discovery 2 – halt 0 D2 DC Disconnect timer 0 = DC Disconnect timer between 300 ms to 400 ms for loads less than 5 mA (IEEE standard) 1 = DC Disconnect timer 0 ms for loads less than 5 mA 0 D1 TED timer 0 = normal operation 1 = 750-ms TED timer disable 0 D0 Unused 0 0 Test mode select; not intended for end--application use. Table 5. Common Control Write, Register Select = 0001 BIT (1) (2) 32 FUNCTION STATE PRESET STATE D7 Unused 0 0 D6 Unused 0 0 D5 Thermal shutdown fault (1) 0 = active 1 = disable 0 D4 A high 0 = off 1 = AC_HI driver on 0 D3 AC low 0 = off 1 = AC_LO driver on 0 D2 Port over/under voltage faults 0 = active 1 = disable 0 D1 All ports disable (2) 0 = normal operation 1 = all ports shut down (no ramp) 0 D0 Software RESET 0 = normal operation 1 = reset all circuits and start a POR timing cycle 0 Register 0001, bit D5 operation inhibited after device probe. Consult factory for Alternative B, semi-auto mode implementations which write to bit D1. Submit Documentation Feedback TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 Table 6. Port Control Write 1, Register Select = 0010 (One Per Port) BIT FUNCTION STATE PRESET STATE D7 Unused 0 0 D6 Unused 0 0 D5 Discovery fault disable 0 = normal operation 1 = disable internal discovery fault limits (19 kΩ to 29.5 kΩ) 0 D4 DC Disconnect disable 0 = DC Disconnect active 1 = DC Disconnect disable (for AC Disconnect) 0 D3 Function Bit 3 D2 Function Bit 2 D1 Function Bit 1 D0 0000 = Disable function (power down and reset all functions) 0001 = Discovery 1 function 0010 = Discovery 2 function 0011 = port voltage sample function (V sample) 0100 = legacy detection function 0101 = classification function 0110 = ramp up/power function (rup pwr) 0111 = continuous sample function (C sample) 1000 = ramp power down function (Rdwn) 1001 = ac low 1010 = ac high 1011 = port current sample function (I sample) 1100 = die temperature sample function (T sample) 1101 = spare 1110 = spare 1111 = spare Function Bit 0 0000 Table 7. Port Control Write 2, Register Select = 0011 (One Per Port) BIT (1) FUNCTION STATE PRESET STATE D7 Unused 0 0 D6 Unused 0 0 D5 Unused 0 0 0 = normal 1 = port disable 0 Enable (1) D4 Port D3 A/D Start 0 = normal 1 = start A/D (self clearing) 0 D2 A/D Abort 0 = normal 1 = abort 0 D1 Unused 0 0 D0 Unused 0 0 Consult factory for Alternative B, semi-auto mode implementations which write to bit D4. Submit Documentation Feedback 33 TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 Table 8. Port Status Read 1, Register Select = 0100 (One Per Port) BIT FUNCTION STATE PRESET STATE D7 Discovery Status 0 = normal 1 = discovery fail 0 D6 Function Done Bit 0 = normal 1 = function complete (self clearing by a new function write) 0 D5 Port Class D4 Port Class D3 Port Class D2 Fault status (MSB) D1 Fault status D0 Fault status (LSB) 000 = 001 = 010 = 011 = 100 = class class class class class 0 1 2 3 4 000 = 001 = 010 = 011 = 100 = 101 = 110 = 111 = no faults UV/OV fault thermal shutdown fault (TSD) overload current > 50-ms fault load disconnect reserved for future reserved for future reserved for future 000 000 Table 9. Port Status Read 2, Register Select = 0101 (One Per Port) BIT 34 FUNCTION STATE PRESET STATE D7 Unused 0 0 D6 Unused 0 0 D5 Unused 0 0 D4 Watch dog timer 0 = not active 1 = active 0 D3 A/D status 0 = not active 1 = active (conversion in process) 0 D2 Function status (MSB) D1 Function status D0 Function status (LSB) 000 = 001 = 010 = 011 = 100 = 101 = 110 = 111 = disabled searching power delivery fault test other fault undefined undefined Submit Documentation Feedback 000 TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 A/D Results Registers (Discovery Current, Voltage, Current and Temperature) Table 10. Discovery Current — Lower Bits, Register Select = 0110 (One Per Port) BIT FUNCTION D7 A/D bit 7 D6 A/D bit 6 D5 A/D bit 5 D4 A/D bit 4 D3 A/D bit 3 D2 A/D bit 2 D1 A/D bit 1 D0 A/D bit 0 STATE A/D lower bits PRESET STATE 0 Table 11. Discovery Current — Upper Bits, Register Select = 0111 (One Per Port) BIT FUNCTION STATE PRESET STATE D7 Resistor measurement complete 0 = measurement active (bit set low at the start of Discovery 1 or Discovery 2) 1 = measurement complete (bit set high after A/D is completed during Discovery 1 or Discovery 2) 0 D6 A/D bit 14 A/D upper bits 0 D5 A/D bit 13 D4 A/D bit 12 D3 A/D bit 11 D2 A/D bit 10 D1 A/D bit 9 D0 A/D bit 8 Table 12. Voltage — Lower Bits, Register Select = 1000 (One Per Port) BIT FUNCTION D7 A/D bit 7 D6 A/D bit 6 D5 A/D bit 5 D4 A/D bit 4 D3 A/D bit 3 D2 A/D bit 2 D1 A/D bit 1 D0 A/D bit 0 STATE A/D lower bits PRESET STATE 0 Submit Documentation Feedback 35 TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 Table 13. Voltage — Upper Bits, Register Select = 1001 (One Per Port) BIT FUNCTION STATE PRESET STATE D7 Voltage measurement complete 0 = measurement active (bit set low when A/D begins a voltage measurement) 1 = measurement complete (bit set high after A/D has completed a voltage measurement) 0 D6 A/D bit 14 A/D upper bits 0 D5 A/D bit 13 D4 A/D bit 12 D3 A/D bit 11 D2 A/D bit 10 D1 A/D bit 9 D0 A/D bit 8 Table 14. Current — Lower Bits, Register Select = 1010 (One Per Port) BIT FUNCTION D7 A/D bit 7 D6 A/D bit 6 D5 A/D bit 5 D4 A/D bit 4 D3 A/D bit 3 D2 A/D bit 2 D1 A/D bit 1 D0 A/D bit 0 STATE A/D lower bits PRESET STATE 0 Table 15. Current — Upper Bits, Register Select = 1011 (One Per Port) BIT 36 FUNCTION STATE PRESET STATE D7 Current measurement complete 0 = measurement active (bit set low when A/D begins a current measurement) 1 = measurement complete (bit set high after A/D has completed a current measurement) 0 D6 A/D bit 14 A/D upper bits 0 D5 A/D bit 13 D4 A/D bit 12 D3 A/D bit 11 D2 A/D bit 10 D1 A/D bit 9 D0 A/D bit 8 Submit Documentation Feedback TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 Table 16. Temperature — Lower Bits, Register Select = 1100 (One Per Port) BIT FUNCTION D7 A/D bit 7 D6 A/D bit 6 D5 A/D bit 5 D4 A/D bit 4 D3 A/D bit 3 D2 A/D bit 2 D1 A/D bit 1 D0 A/D bit 0 STATE A/D lower bits PRESET STATE 0 Table 17. Temperature — Upper Bits, Register Select = 1101 (One Per Port) BIT FUNCTION STATE PRESET STATE D7 Temperature measurement complete 0 = measurement active (bit set low when A/D begins a temperature measurement) 1 = measurement complete (bit set high after A/D has completed a temperature measurement) 0 D6 A/D bit 14 A/D upper bits 0 D5 A/D bit 13 D4 A/D bit 12 D3 A/D bit 11 D2 A/D bit 10 D1 A/D bit 9 D0 A/D bit 8 Submit Documentation Feedback 37 TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 TPS2384 AC DRIVE APPLICATION SCHEMATIC AC_HI and LOW w/o External FET Configurations Figure 17. 38 Submit Documentation Feedback TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 TPS2384 AC DRIVE APPLICATION SCHEMATIC (continued) TPS2384 System Block Diagram NOTE: A fuse may be required to provide additional protection if isolation is lost or the low-side current sense fails. Figure 18. Submit Documentation Feedback 39 TPS2384 www.ti.com SLUS634D – NOVEMBER 2004 – REVISED MARCH 2007 TPS2384 AC DRIVE APPLICATION SCHEMATIC (continued) TPS2384 Basic 4 PORT (PMM) Isolated Configuration with AC Disconnect TPS2384 basic 4-port isolated configuration with AC Disconnect (PAP pinout shown). Function 7.5K Auto 68uF + 0.1uF 220pF 124K 0.1uF 0.1uF 0.1uF - 7.5K 7.5K 7.5K SYN AC_HI AC_LO Ct V2.5 RG Rbias AG1 V48 V6.3 V10 MS RJ45-5 Xformer 1 2 48 3 46 47 CINT4 45 RET4 44 4 CINT1 0.027uF 5 RET1 6 N1 7 P1 8 TPS2384 Quad PSEController N4 43 P4 42 P2 P3 39 11 N2 N3 38 RET3 37 CINT3 36 A5 A4 A3 A2 A1 SDA_O SDA_I SCL V3 34 33 DG INT ALTA/B WD_DIS 15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 3.9K 9.1K 0.5W 48V BUS 9.1K 0.1uF 3.9K 270 270 270 3.9K 3.9K SDA_OU T INT SCL Open Drain SDA_IN Open Drain POR Open Drain GND CPU Figure 19. 40 3.9K NEG 0.5W V DD CPU 0.027uF 35 16 POS RJ45-5 Xformer RJ45-5 Xformer 40 10 12 RET2 13 CINT 2 14 220nF 0.027uF 41 9 0.027uF 220nF RJ45-5 Xformer 220nF PORB AG2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Submit Documentation Feedback 220nF PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) (3) Top-Side Markings (4) TPS2384PAP ACTIVE HTQFP PAP 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 TPS2384PAP TPS2384PAPG4 ACTIVE HTQFP PAP 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 TPS2384PAP TPS2384PAPR ACTIVE HTQFP PAP 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 TPS2384PAP TPS2384PAPRG4 ACTIVE HTQFP PAP 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 TPS2384PAP TPS2384PJD ACTIVE HTQFP PJD 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 TPS2384PJD TPS2384PJDG4 ACTIVE HTQFP PJD 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 TPS2384PJD TPS2384PJDR ACTIVE HTQFP PJD 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 TPS2384PJD TPS2384PJDRG4 ACTIVE HTQFP PJD 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 TPS2384PJD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS2384PAPR HTQFP PAP 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 TPS2384PJDR HTQFP PJD 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2384PAPR HTQFP PAP 64 1000 367.0 367.0 45.0 TPS2384PJDR HTQFP PJD 64 1000 367.0 367.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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