SN65HVD101 SN65HVD102 www.ti.com SLLSE84A – MAY 2011 – REVISED MARCH 2013 IO-LINK PHY for Device Nodes Check for Samples: SN65HVD101, SN65HVD102 FEATURES 1 • • • • • • • Configurable CQ Output: Push-Pull, High-Side, or Low-Side for SIO Mode Remote Wake-Up Indicator Current Limit Indicator Power-Good Indicator Overtemperature Protection Reverse Polarity Protection Configurable Current Limits • • • • 9-V to 36-V Supply Range Tolerant to 50-V Peak Line Voltage 3.3-V/5-V Configurable Integrated LDO (SN65HVD101 ONLY) 20-pin QFN Package, 4 mm × 3.5 mm APPLICATIONS • Suitable for IO-Link Device Nodes DESCRIPTION The SN65HVD101 and ‘HVD102 IO-LINK PHYs implement the IO-LINK interface for industrial point-to-point communication. When the device is connected to an IO-Link master through a 3-wire interface, the master can initiate communication and exchange data with the remote node while the SN65HVD10X acts as a complete physical layer for the communication. The IO-LINK driver output (CQ) can be used in push-pull, high-side, or low-side configurations using the EN and TX input pins. The PHY receiver converts the 24-V IO-LINK signal on the CQ pin to standard logic levels on the RX pin. A simple parallel interface is used to receive and transmit data and status information between the PHY and the local controller. The SN65HVD101 and 'HVD102 implement protection features for overcurrent, overvoltage and overtemperature conditions. The IO-Link driver current limit can be set using an external resistor. If a short-circuit current fault occurs, the driver outputs are internally limited, and the PHY generates an error signal (SC). These devices also implement an overtemperature shutdown feature that protects the device from high-temperature faults. The SN65HVD102 operates from a single external 3.3-V or 5-V local supply. The SN65HVD101 integrates a linear regulator that generates either 3.3 V or 5 V from the IO-Link L+ voltage for supplying power to the PHY as well as a local controller and additional circuits. The SN65HVD101 and 'HVD102 are available in the 20-pin RGB package (4 mm × 3,5 mm QFN) for spaceconstrained applications. VCC OUT VCC VCC IN SET L+ SUPPLY VOLTAGE CONTROL PWR_OK RX CQ TX Voltage Timers EN WAKE CUR_OK Control Logic Voltage Detectors L- Over Current Over Current Timers Detectors TEMPERATURE SENSE TEMP_OK ILIM_ADJ GND L- 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2013, Texas Instruments Incorporated SN65HVD101 SN65HVD102 SLLSE84A – MAY 2011 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PIN DESCRIPTIONS The definitions below define the functionality for each pin. Type: I Input Type: O CMOS Output Type: I/O Input/Output Type: OD Open Drain Output Type: A Analog Type: P Power PIN FUNCTIONS SIGNAL NAME TYPE PIN DESCRIPTION IO-LINK Interface L+ P 10 IO-Link supply voltage (24V nominal) CQ I/O 12 IO-Link data signal (bi-directional) L– P 14 IO-Link ground (connect to GND on board) Local Controller Interface CUR_OK OD 15 High-CQ-current fault indicator output signal from PHY to the microcontroller, a LOW level indicates overcurrent condition WAKE OD 16 Wake up indicator from the PHY to the local controller RX O 17 PHY data output to the local controller TX I 18 PHY data input from the local controller EN I 20 Driver enable control from the local controller Power Supply Pins VCC IN A 7 Voltage supply input (HVD102) Voltage sense feedback input for voltage regulator (HVD101) - connect to pin 8 either directly or through a current boost transistor. VCC OUT P 8 Output voltage from the voltage regulator (HVD101) - connect to pin 7 either directly or through a current boost transistor. No connect (HVD102) GND P 3, 6, 13 Ground pins Special connect pins VCC SET I 1 If this pin is left floating then the Vcc supply is 5V. If this pin is connected to GND, then the Vcc supply is 3.3V ILIMADJ A 4 Sets the CQ Output Current. A resistor RSET is connected to this pin. The output current is defined as VREF / (RINT + RSET ) × KSET. PWR_OK OD 5 Power Good signal. A high impedance on this pin indicates that the L+ and Vcc outputs are at correct levels. Temp_OK OD 19 Temperature Good signal. A high impedance on this pin indicates that the internal temperature is at a safe level. If the internal device temperature reaches a level approaching the thermal shutdown temperature, this pin will go to an active low state. NC 2 2, 9, 11 No Connect. Leave these pins floating (open) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SN65HVD101 SN65HVD102 SN65HVD101 SN65HVD102 www.ti.com SLLSE84A – MAY 2011 – REVISED MARCH 2013 L- GND CQ NC CUR_OK L- GND CQ NC HVD102 (Top View) CUR_OK HVD101 (Top View) 15 14 13 12 11 15 14 13 12 11 WAKE 16 10 L+ WAKE 16 10 L+ RX 17 9 NC RX 17 9 NC TX 18 8 Vcc OUT TX 18 8 NC TEMP_OK 19 7 Vcc IN EN 20 2 3 4 5 PWR_OK 6 GND 1 ILIM_ADJ GND 5 GND NC 4 PWR_OK 3 ILIM_ADJ 2 Vcc SET 6 GND 1 NC EN 20 7 Vcc IN Vcc SET TEMP_OK 19 In normal operation, the PHY sets the output state of the CQ pin when the driver is enabled. During fault conditions, the driver may be disabled by internal circuits. Table 1. Driver Function EN TX CQ COMMENT L or OPEN X Z PHY is in ready-to-receive state H L H PHY CQ is sourcing current (high-side drive) H H or OPEN L PHY CQ is sinking current (low-side drive) Table 2. Receiver Function CQ Voltage RX VCQ < VTHL H Comment Normal receive mode, input low VTHL < VCQ < VTHH ? Indeterminate output, may be either H or L VTHH < VCQ L Normal receive mode, input high OPEN H Failsafe output high Table 3. Wake Up Function EN TX CQ VOLTAGE WAKE L X X Z PHY is in ready-to-receive state COMMENT H L VTHH < VCQ (tWU) L PHY receives High-level wake-up request from Master H X VTHL < VCQ < VTHH ? Indeterminate output, may be either H or L H H VCQ < VTHL (tWU) L PHY receives Low-level wake-up request from Master Table 4. Current Limit Indicator Function CQ CURRENT CUR_OK |ICQ| < IO(LIM) Z COMMENT Normal operation |ICQ| > IO(LIM) L CQ current is at the internal limit Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SN65HVD101 SN65HVD102 Submit Documentation Feedback 3 SN65HVD101 SN65HVD102 SLLSE84A – MAY 2011 – REVISED MARCH 2013 www.ti.com Table 5. Temperature Indicator Function Internal Temperature Overtemp (Internal) TEMP_OK not overtemp Z Normal operation T < TWARN TWARN < T↑ < TSD TSD < T Comment not overtemp L Temperature warning overtemp disable L Overtemp disable not overtemp L Temperature recovery TWARN < T↓ < TRE Table 6. Power Supply Indicator Function VL+ VCC PWR_OK Comment VL+ < VPG1 VPOR2 < VCC < VPG2 L Both supplies too low VPG1 < VL+ VPOR2 < VCC < VPG2 L VCC too low VL+ < VPG1 VPG2 < VCC L VL+ too low VPG1 < VL+ VPG2 < VCC Z Both supplies correct THERMAL INFORMATION SN65HVD10x THERMAL METRIC (1) RGB PACKAGE UNITS 20 PINS θJA Junction-to-ambient thermal resistance 33.8 θJCtop Junction-to-case (top) thermal resistance 36.6 θJB Junction-to-board thermal resistance 10.3 ψJT Junction-to-top characterization parameter 0.4 ψJB Junction-to-board characterization parameter 10.3 θJCbot Junction-to-case (bottom) thermal resistance TSTG Storage temperature (1) °C/W 2.3 65 to 150 °C For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE MIN L+, CQ Line voltage – steady state –40 Line Voltage – transient, pulse width <100us UNIT MAX +40 (2) (3) V +50 V VCC Supply voltage –0.3 6 V TX, EN, VCC_SET, ILIMADJ, Input voltage –0.3 6 V RX, CUR_OK, WAKE, PWR_OK Output voltage –0.3 6 V RX, CUR_OK, WAKE, PWR_OK Output current TBD Tstg Storage temperature –65 TJ Die temperature ESD HBM (all pins) V IO (1) (2) (3) 4 mA 150 °C 180 °C 2 kV Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with reference to the GND pin, unless otherwise specified. GND pin and L- line should be at the same DC potential Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SN65HVD101 SN65HVD102 SN65HVD101 SN65HVD102 www.ti.com SLLSE84A – MAY 2011 – REVISED MARCH 2013 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX VL+ Line voltage (1) 9 24 30 V VCC Logic supply voltage (3.3V nominal) 3 3.3 3.6 V VCC Logic supply voltage (5V nominal) 4.5 5 5.5 V VIL Logic low input voltage 0.8 V VIH Logic high input voltage IO Logic output current 2 V –4 4 mA 20 mA 100 450 mA 0 20 kΩ ICC(OUT) Logic supply current (HVD101) IO(LIM) CQ driver output current limit RSET External resistor for CQ current limit CCOMP Compensation capacitor for voltage regulator (HVD101) Signaling rate TA Ambient temperature TJ Junction temperature PD Power dissipation (1) 3.3 µF IO-Link mode 1/tBIT UNIT 250 SIO mode 10 kbps –40 105 °C –40 150 °C see Thermal Characteristics table These devices will operate with line voltage as low as 9V and as high as 36V, however, the parametric performance is optimized for the IO-Link specified supply voltage range of 18V to 30V. DEVICE CHARACTERISTICS over all operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT –100 100 µA 1.5 3 V VL+ < 18 3.5 V 18 < VL+ 2 V VL+ < 18 2.5 V 3 V VL+ < 18 3.5 V 18 < VL+ 2 V VL+ < 18 2.5 V 2 µs Driver Characteristics IIN Input current (TX, EN) VIN = 0V to VCC ICQ = –250 mA VRQH Residual voltage across the driver high side switch ICQ = –200 mA ICQ = 250 mA VRQL Residual voltage across the driver low side switch ICQ = 200 mA tPLH, tPHL Driver propagation delay tP(skew) Driver propagation delay skew tPZH, tPZL Driver disable delay tr , tf Driver output rise, fall time |tr – tf | Difference in rise and fall time |IO(LIM)| Driver output current limit KSET Scale factor for current limit I(OZ) CQ leakage current with EN = L 18 < VL+ 1.5 1 TX to CQ 18V < VL+ < 30 V Driver enable delay (EN to CQ) tPHZ, tPLZ 18 < VL+ 9V < VL+ < 18 V 18V < VL+ < 30 V VL+ < 18 V 0.2 Figure 1, Figure 2, Figure 3, RL = 2 kΩ, CL = 5 nF RSET = 0 Ω 18V < VL+ µs 5 µs 8 µs 5 µs 8 µs 896 ns 300 ns RSET = 20 kΩ 60 95 130 mA RSET = 0 kΩ 300 400 480 mA 2 µA 10.5 13 V 8 11.5 V See the Typical Characterisitics VCQ = 8 V –2 RECEIVERS CHARACTERISTICS VTHH Input threshold “H” VTHL Input threshold “L” VHYS Receiver Hysteresis (VTHH – VTHL) 18 V < VL+ < 30 V Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SN65HVD101 SN65HVD102 0.5 1 Submit Documentation Feedback V 5 SN65HVD101 SN65HVD102 SLLSE84A – MAY 2011 – REVISED MARCH 2013 www.ti.com DEVICE CHARACTERISTICS (continued) over all operating conditions (unless otherwise noted) PARAMETER VTHH Input threshold “H” VTHL Input threshold “L” VHYS Receiver Hysteresis (VTHH–VTHL) TEST CONDITIONS 9 V < VL+ < 18 V TYP MAX UNIT (1) Note (2) V Note (3) Note (4) V 0.25 V RX IOL = 4 mA 0.4 OD outputs IOL = 1 mA 0.4 VOL Output low voltage VOH Output high voltage RX IOH = –4 mA IOZ Output leakage current OD outputs Output in Z state, VO = VCC tWU1 Wake-up recognition begin tWU2 Wake-up recognition end tWAKE Wake-up output delay tND Noise suppression time tpR MIN Note V VCC–0.5 V .03 See Figure 6 1 45 60 75 85 100 135 µA µs 155 (5) Receiver propagation delay See Figure 4 18 V < VL+ 300 VL+ < 18 V 250 ns 600 ns 800 ns PROTECTION THRESHOLDS TSD Shutdown temperature TRE Re-enable temperature TWARN Thermal warning temperature (TEMP_OK) tpSC Current limit indicator delay 85 175 µs VPG1 VL+ threshold for PWR_OK 8 10 V (6) Die Temperature VCC Set = GND 160 175 190 110 125 140 120 135 150 2.45 2.75 3 3.9 4.25 4.6 °C VPG2 VCC threshold for PWR_OK VPOR1 Power-on Reset for VL+ 6 V VPOR2 Power-on Reset for VCC 2.5 V VCC Set = OPEN V VOLTAGE REGULATOR CHARACTERISTICS (HVD101) VCC_SET is OPEN Voltage regulator output 18 V < VL+ < 30 V Voltage regulator output 9 V < VL+ < 18 V Voltage regulator drop-out voltage (VL+ – VCC) ICC = 20 mA load current Line regulation 9 V < VL+ < 30 V, IVCC = 1 mA Load regulation VL+ = 24 V, IVCC = 100 µA to 20 mA PSRR 100 kHz, IVCC = 20 mA VCC VCC_SET to GND VCC_SET is OPEN VCC_SET to GND 4.5 5 5.5 3 3.3 3.6 4.5 5 5.5 3 3.3 3.6 3.2 3.9 4 1.3% 30 V V V mV/V 5% 40 dB SUPPLY CURRENT Quiescent supply current, Driver disabled IL+ Dynamic supply current, Driver disabled Dynamic supply current, Driver enabled (1) (2) (3) (4) (5) (6) 6 No Load L+ = 24V, No Load 1/tBIT = 250 kbps HVD102 1 2 HVD101 1.3 3 HVD101 2 HVD102 1.5 See Typical Characteristics mA mA mA VTHH(min) = 5V + (11/18)[VL+ - 9V] VTHH(max) = 6.5V + (13/18)[VL+ - 9V] VTHL(min) = 4V + (8/18)[VL+ -9V] VTHL(max) = 6V + (11/18)[VL+ -9V] Noise suppression time is defined in the IO-Link standard as the permissible duration of a receive signal above/below the detection threshold without detection taking place. TRE is always less than TWARN so TEMP_OK is de-asserted (high impedance) when the device is re-enabled Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SN65HVD101 SN65HVD102 SN65HVD101 SN65HVD102 www.ti.com SLLSE84A – MAY 2011 – REVISED MARCH 2013 14 13 VTHH Receiver Thresholds - V 12 11 10 9 VTHL 8 7 6 5 4 8 12 16 20 VL+ (V) 24 28 32 Figure 1. Receiver Threshold Boundaries PARAMETER MEASUREMENT L+ RL TX CQ RL CL EN Figure 2. Test Circuit for Driver Switching VOH TX 80% 50% tPLH tPHL CQ VL+ VCQ 80% 20% VCQ 50% 20% VOL 0V tr tf Figure 3. Waveforms for Driver Output Switching Measurements Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SN65HVD101 SN65HVD102 Submit Documentation Feedback 7 SN65HVD101 SN65HVD102 SLLSE84A – MAY 2011 – REVISED MARCH 2013 www.ti.com PARAMETER MEASUREMENT (continued) EN 50% 50% EN tPZH tPLZ tPZL tPHZ 80% 50% CQ 50% CQ 20% Figure 4. Waveform for Driver Enable/Disable Time Measurements 50% CQ tPHL tPLH RX 50% Figure 5. Receiver switching measurements 8 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SN65HVD101 SN65HVD102 SN65HVD101 SN65HVD102 www.ti.com SLLSE84A – MAY 2011 – REVISED MARCH 2013 APPLICATION INFORMATION SN65HVD101 VCC VCC IN VCC SET L+ MICRO CONTROLLER TX EN RX PWR_OK SENSOR CUR_OK WAKE IOLINK MASTER CQ LGND LIM ADJ Figure 6. Application Example With VCC = 3.3 V N-Switch SIO Mode Set TX pin High and use EN pin as the control to realize the function of N-switch (low-side driver) on the CQ pin. EN L H TX H H CQ Hi-Z N-Switch P-Switch SIO Mode Set TX pin Low and use EN pin as the control to realize the function of P-switch (high-side driver) on the CQ pin. EN L H TX L L CQ Hi-Z P-Switch Push-Pull / Communication Mode Set TX pin Low and use EN pin as the control to realize the function of P-switch (high-side driver) on the CQ pin. EN L H H TX X H L CQ Hi-Z N-Switch P-Switch Wake up detection The device may be in IO-Link mode or SIO mode. If the device is in SIO mode and the master node wants to initiate communication with the device node, the master drives the CQ line to the opposite of its present state, and will either sink or source the wake up current (IQWU is typically up to 500 mA) for the wake-up duration (TWU is typically 80 µs) depending on the CQ logic level as per the IO-LINK specification. The SN65HVD1XX IO-LINK PHY detects this wake-up condition and communicates to the local microcontroller via the WAKE pin. The IOLink Communication Specification requires the device node to switch to receive mode within 500 microseconds after receiving the Wake Up signal. For over-current conditions shorter or longer than a valid Wake-Up pulse, the WAKE pin will remain in a highimpedance (inactive) state. This is illustrated in Figure 7, and discussed in the following paragraph. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SN65HVD101 SN65HVD102 Submit Documentation Feedback 9 SN65HVD101 SN65HVD102 SLLSE84A – MAY 2011 – REVISED MARCH 2013 www.ti.com EN = H, TX = L CQ Over-current caused by transient EN = H, TX = H < 45 ms CQ RX RX WAKE WAKE CUR_OK CUR_OK CQ 80 ms ± 5 ms RX Wake-Up Pulse from Master Node CQ WAKE tPWAKE tPWAKE CUR_OK Over-current caused by fault condition 80 ms ± 5 ms RX WAKE CQ < 45 ms CUR_OK > 250 ms CQ RX RX WAKE WAKE CUR_OK > 250 ms CUR_OK tPSC tPSC Figure 7. Over-Current and Wake Conditions Current Limit Indication, Short Circuit Current Detection If the output current at CQ remains at the internally set current limit IO(LIM) for a duration longer than a wake-up pulse (longer than 80 usec) the CUR_OK pin will be driven to a logic LOW state. The CUR_OK pin will return to the high-impedance (inactive) state when the CQ pin is no longer in a current limit condition. The state diagram shown in Figure 8 illustrates the various states and under what conditions the device transitions from one state to another. 10 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SN65HVD101 SN65HVD102 SN65HVD101 SN65HVD102 www.ti.com SLLSE84A – MAY 2011 – REVISED MARCH 2013 EN Receive Only CUR_OK = Z WAKE = Z Driver is OFF Receive and Transmit CUR_OK = Z WAKE = Z Driver is ON EN* CQ NOT at ILIM CQ at ILIM for t WU1< t < t WU2 and RX•7; CQ at ILIM for longer than tWU2 T > TSD CQ at ILIM for longer than tWU2 EN* Wake WAKE = L CUR_OK = Z Driver is ON T < TRE T > TSD T > TSD Thermal Shutdown CUR_OK =Z WAKE = Z Driver is OFF T > TSD Current Fault WAKE = Z CUR_OK = L Driver is ON EN* Figure 8. State Diagram Over Temperature detection If the internal temperature of the device exceeds the over-temperature threshold (θTSD), then the CQ driver and voltage regulator (HVD101) will be internally disabled. When the temperature falls below the temperature threshold the internal circuit re-enables the voltage regulator (HVD101) and the output driver, subject to the state of the EN and TX pins. CQ Current Limit Adjustment The CQ driver output current limit can be set using an external resistor on the LIMADJ pin. The current limit is given by: I(LIM) = I_Ref × KSET space where I_Ref = VREF / (RINT + RSET) Note that both the positive and negative current limits are set by a single resistor value. If no RSET is used (LIMADJ is tied directly to GND) then the current limit is set to the maximum value of 400 mA. Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SN65HVD101 SN65HVD102 Submit Documentation Feedback 11 SN65HVD101 SN65HVD102 SLLSE84A – MAY 2011 – REVISED MARCH 2013 www.ti.com 450 400 350 Current Limit 300 250 200 150 100 50 0 0 5000 10000 15000 20000 25000 Radjust Figure 9. Typical Current Limit Characteristics Over-Voltage and Reverse Polarity protection Reverse polarity protection is included in the device. Any combination of voltages between 0 and 40V may be applied at the pins L+, CQ and L- without causing device damage. For protection against higher levels of faults, including transient over-voltage conditions, external protection devices can be added as shown in Figure 10. This will protect the device against high-power transients, and will also stand-off a steady-state reverse polarity fault of up to 33V. Figure 10. 12 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SN65HVD101 SN65HVD102 SN65HVD101 SN65HVD102 www.ti.com SLLSE84A – MAY 2011 – REVISED MARCH 2013 Table 7. Suggested External Protection Components Device Function Part-No. Manufacturer XCVR I/O Link transceiver SN65HVD101 Texas Instruments R 1Ω, 0.25W MELF resistor MMA02040B1008FB300 Vishay TVS Bidirectional 1500W TVS SMCJ33CA Bourns CS 2.2uF, 100V, X7R, 10% HMK325B7225KN-T Taiyo Yuden CB 0.1uF, 100V, X7R, 10% C2012X7R2A104K TDK CHV 4700 pF, 2kV, X7R, 10% 1812B472K202NT Nocacap Voltage Regulator (Not available in the SN65HVD102) The SN65HVD101 integrates a linear voltage regulator which supplies power to external components as well as to the PHY itself. The voltage regulator is specified for L+ voltages in the range of 9V to 30V with respect to GND. The output voltage can be set using the VccSET pin. When this pin is left open (floating) then the output voltage is 5V. When it is connected to GND then the output voltage is 3.3V. The integrated voltage regulator can supply a maximum current of 20 mA to external components. When more supply current is needed, an external transistor can be connected as shown in Figure 11 and Figure 12. L+ +24VDC HVD101 Q1 VCC_OUT L- 1PF ILOAD VLOAD VCC_IN VCC_SET GND RLOAD +24V RTN VCC_IN = GND (+3.3VDC OPERATION) Figure 11. Example Circuit for Boosted 3.3V-Supply Current Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SN65HVD101 SN65HVD102 Submit Documentation Feedback 13 SN65HVD101 SN65HVD102 SLLSE84A – MAY 2011 – REVISED MARCH 2013 www.ti.com L+ +24VDC HVD101 Q1 VCC_OUT L- 1PF ILOAD VLOAD VCC_IN VCC_SET RLOAD +24V RTN GND VCC_IN = VCC_SET (+5VDC OPERATION) Figure 12. Example Circuit for Boosted 5V-Supply Current Incandescent Lamp Loads The resistance of an incandescent lamp filament varies strongly with temperature. The initial (cold-filament) resistance of tungsten-filament lamps is less than 10% of the steady-state (hot-filament) resistance. For example, a 100-watt, 120-volt lamp has a resistance of 144 Ω when lit, but the cold resistance is much lower (about 9.5 Ω). The initial “in-rush” current is therefore high compared to the steady-state current. Within 3 to 5 ms the current falls to approximately twice the hot current. For typical general-service lamps, the current reaches steady-state conditions in less than about 100 milliseconds. The ‘HVD10x CQ output will remain at the selected current-limit as the filament warms up, and then will stay at the steady-state current level. For example, a 6W, 24VDC indicator lamp has a steady-state current of 250 mA. However, the initial in-rush current could be over 2 Amps if unlimited. If the HVD10x current limit is set to 350 mA, this current will warm up the filament during the initial lamp turn-on, and the final current will be below the current limit. If the CQ output current is at the limit for longer than tSC, the SC output will be active. The local controller can disable the CQ driver if the high current is not expected, or can re-check the SC output after 100 ms if the load is known to be incandescent. SN65HVD101 Replaces ELMOS E981.10 The SN65HVD101 can replace the ELMOS E981.10 Basic IO-Link transceiver with a minimum of board reconfiguration. See the SN65HVD101 Evaluation Module for board design guidelines to accommodate both devices. 14 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SN65HVD101 SN65HVD102 SN65HVD101 SN65HVD102 20 Vcc SET W AKE RX TX EN SLLSE84A – MAY 2011 – REVISED MARCH 2013 (SPEED) TEMP_ Ok www.ti.com 16 1 15 CUR _OK (SILIM ) L- SN 65 HVD 101 GND GND Exposed Pad GND ILIMADJ 5 11 6 NC NC Vcc O UT Vcc SENS 10 L+ PWR _OK CQ Figure 13. Comparison of HVD10x Pin-out to E981.10 Pin-out REVISION HISTORY Changes from Original (May 2011) to Revision A • Page Changed the devices From: Product Preview To: Production .............................................................................................. 1 Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SN65HVD101 SN65HVD102 Submit Documentation Feedback 15 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) SN65HVD101RGBR ACTIVE VQFN RGB 20 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 105 HVD101 SN65HVD101RGBT ACTIVE VQFN RGB 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 105 HVD101 SN65HVD102RGBR ACTIVE VQFN RGB 20 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 105 HVD102 SN65HVD102RGBT ACTIVE VQFN RGB 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 105 HVD102 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN65HVD101RGBR VQFN RGB 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1 SN65HVD101RGBT VQFN RGB 20 250 180.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1 SN65HVD102RGBR VQFN RGB 20 1000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1 SN65HVD102RGBT VQFN RGB 20 250 180.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65HVD101RGBR VQFN RGB 20 1000 367.0 367.0 35.0 SN65HVD101RGBT VQFN RGB 20 250 210.0 185.0 35.0 SN65HVD102RGBR VQFN RGB 20 1000 367.0 367.0 35.0 SN65HVD102RGBT VQFN RGB 20 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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