DS15BA101 www.ti.com SNLS234J – OCTOBER 2006 – REVISED APRIL 2013 DS15BA101 1.5 Gbps Differential Buffer with Adjustable Output Voltage Check for Samples: DS15BA101 FEATURES DESCRIPTION • • • • • • • The DS15BA101 is a high-speed differential buffer for cable driving, level translation, signal buffering, and signal repeating applications. Its fully differential signal path ensures exceptional signal integrity and noise immunity and it drives both differential and single-ended transmission lines at data rates in excess of 1.5 Gbps. 1 2 Data Rates from DC to 1.5+ Gbps Differential or Single-ended Input Adjustable Output Amplitude Single 3.3V Supply Industrial -40°C to +85°C Temperature Low Power: 150 mW (typ) at 1.5 Gbps Space-saving 3 x 3 mm WSON-8 Package APPLICATIONS Output voltage amplitude is adjustable via a single external resistor for level translation and cable driving applications into 50-ohm single-ended and 100-ohm differential mode impedances. • • • • The DS15BA101 is powered from a single 3.3V supply and consumes 150 mW (typ) at 1.5 Gbps. It operates over the full −40°C to +85°C industrial temperature range and is available in a space saving 3x3 mm WSON-8 package. Cable Extension Applications Level Translation Signal Buffering and Repeating Security Cameras Typical Application Serializer LVPECL 50-ohm Coaxial Cable (i.e. Belden 9914) CML DS15BA101 150 Mbps to 1.5 Gbps DS15EA101 Max Cable Loss ~ 35 dB @ 750 MHz Deserializer 100-ohm Differential Cable (i.e. CAT5e/6/7, Twinax) LVDS 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated DS15BA101 SNLS234J – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) −0.5V to 3.6V Supply Voltage −0.3V to VCC+0.3V Input Voltage (all inputs) Output Current 28 mA −65°C to +150°C Storage Temperature Range Junction Temperature +150°C Lead Temperature (Soldering 4 Sec) Package Thermal Resistance +260°C θJA WSON-8 +90.7°C/W θJC WSON-8 +41.2°C/W ESD Rating (HBM) 5 kV ESD Rating (MM) 250V (1) "Absolute Maximum Ratings" are those parameter values beyond which the life and operation of the device cannot be ensured. The stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of "Electrical Characteristics" specifies acceptable device operating conditions. Recommended Operating Conditions Supply Voltage (VCC – GND): 3.3V ±5% Operating Free Air Temperature (TA) DS15BA101SD −40°C to +85°C DC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (1) (2) Symbol Parameter Conditions Reference VICM Input Common Mode Voltage See Note (3) IN+, IN- VID Differential Input Voltage Swing VOS Output Common Mode Voltage VOUT Output Voltage ICC (1) (2) (3) (4) 2 Supply Current OUT+, OUT- Min Typ Max Units 0.8 VCC – VID/2 V 100 2000 mVP−P VCC – VOUT/2 V Single-ended, 25Ω load RVO = 953Ω 1%, 400 mVP-P Single-ended, 25Ω load RVO = 487Ω 1%, 800 mVP-P See Note (4) 45 49 mA Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated referenced to GND. Typical values are stated for VCC = +3.3V and TA = +25°C. Specification is ensured by characterization. Maximum ICC is measured at VCC = +3.465V and TA = +70°C. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS15BA101 DS15BA101 www.ti.com SNLS234J – OCTOBER 2006 – REVISED APRIL 2013 AC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1). Symbol Parameter Conditions (2) DRMAX Maximum Data Rate See Note tLHT Output Low to High Transition Time 20% – 80% (3) tHLT Output High to Low Transition Time tPLHD Propagation Low to High Delay See Note (2) tPHLD Propagation High to Low Delay See Note (2) tTJ Total Jitter 1.5 Gbps (1) (2) (3) Reference Min Typ IN+, IN- 1.5 2.0 OUT+, OUT- Max Units Gbps 120 220 ps 120 220 ps 0.95 1.10 1.35 ns 0.95 1.10 1.35 ns 26 psP-P Typical values are stated for VCC = +3.3V and TA = +25°C. Specification is ensured by characterization. Specification is ensured by characterization and verified by test. CONNECTION DIAGRAM IN+ 1 8 OUT+ IN- 2 DAP 7 OUT- GND 3 (GND) 6 GND RVO 4 5 VCC Figure 1. 8-Pad WSON See NGQ Package PIN DESCRIPTIONS Pin # Name Description 1 IN+ Non-inverting input pin. 2 IN- Inverting input pin. 3 GND Circuit common (ground reference). 4 RVO Output voltage amplitude control. Connect a resistor to VCC to set output voltage. 5 VCC Positive power supply (+3.3V). 6 GND Circuit common (ground reference). 7 OUT- Inverting output pin. 8 OUT+ Non-inverting output pin. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS15BA101 3 DS15BA101 SNLS234J – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com DEVICE OPERATION INPUT INTERFACING The DS15BA101 accepts either differential or single-ended input. The inputs are self-biased, allowing for simple AC or DC coupling. DC-coupled inputs must be kept within the specified common-mode range. The IN+ and INpins are self-biased at approximately 2.1V with VCC = 3.3V. The following three figures illustrate typical DCcoupled interface to common differential drivers. 100: Differential T-Line OUT+ IN+ 100: LVDS DS15BA101 IN- OUT- Figure 2. Typical LVDS Driver DC-Coupled Interface to DS15BA101 Input CML3.3V or CML2.5V VCC 50: 50: OUT+ 100: Differential T-Line IN+ 100: DS15BA101 IN- OUT- Figure 3. Typical CML Driver DC-Coupled Interface to DS15BA101 Input 100: Differential T-Line OUT+ IN+ 100: LVPECL DS15BA101 IN- OUT50: 50: Figure 4. Typical LVPECL Driver DC-Coupled Interface to DS15BA101 Input OUTPUT INTERFACING The DS15BA101 uses current mode outputs. Single-ended output levels are 400 mVP-P into AC-coupled 100Ω differential cable (with RVO = 953Ω) or into AC-coupled 50Ω coaxial cable (with RVO = 487Ω). Output level is controlled by the value of the RVO resistor connected between the RVO and VCC. The RVO resistor should be placed as close as possible to the RVO pin. In addition, the copper in the plane layers below the RVO network should be removed to minimize parasitic capacitance. The following figure illustrates typical DC-coupled interface to common differential receivers and assumes that the receivers have high impedance inputs. While most receivers have a common mode input range that can accomodate CML signals, it is recommended to check respective receiver's datasheet prior to implementing the suggested interface implementation. 4 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS15BA101 DS15BA101 www.ti.com SNLS234J – OCTOBER 2006 – REVISED APRIL 2013 VCC 50: 50: 100: Differential T-Line OUT+ IN+ DS15BA101 CML or LVPECL or LVDS 100: IN- OUT- Figure 5. Typical DS15BA101 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver CABLE EXTENDER APPLICATION The DS15BA101 together with the DS15EA101 form a cable extender chipset optimized for extending serial data streams from serializer/deserializer (SerDes) pairs and field programmable gate arrays (FPGAs) over 100Ω differential (i.e. CAT5e/6/7 and twinax) and 50Ω coaxial cables. Setting correct DS15BA101 output amplitude and proper cable termination are keys for optimal operation. The following two figures show recommended chipset configuration for 100Ω differential and 50Ω coaxial cables. VCC VCC 50: 953: 50: 0.1 PF 0.1 PF 100: Differential TP Cable RVO IN+ 100: 1 PF 1 PF OUT+ IN+ 100: DS15BA101 DS15EA101 1 PF 1 PF IN- OUT- IN- OUT+ OUT- CAP+ CAP- 1 PF Figure 6. Cable Extender Chipset Connection Diagram for 100Ω Differential Cables VCC VCC 50: 487: 50: 0.1 PF 0.1 PF 50: Coaxial Cable IN+ 100: RVO OUT+ 1 PF 1 PF IN+ 50: DS15BA101 OUT+ DS15EA101 1 PF IN- IN- OUT25: OUT- CAP+ CAP- 1 PF Figure 7. Cable Extender Chipset Connection Diagram for 50Ω Coaxial Cables Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS15BA101 5 DS15BA101 SNLS234J – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com REFERENCE DESIGN There is a complete reference design (P/N: DriveCable02EVK) available for evaluation of the cable extender chipset (DS15BA101 and DS15EA101). For more information, visit http://www.ti.com/tool/drivecable02evk. Typical Performance 6 Figure 8. 1.5 Gbps Differential DS15BA101 Output RVO = 953Ω, H:100 ps / DIV, V:100 mV / DIV Figure 9. 1.5 Gbps Single-ended DS15BA101 Output RVO = 487Ω, H:100 ps / DIV, V:100 mV / DIV Figure 10. 2.0 Gbps Differential DS15BA101 Output RVO = 953Ω, H:100 ps / DIV, V:100 mV / DIV Figure 11. 2.0 Gbps Single-ended DS15BA101 Output RVO = 487Ω, H:100 ps / DIV, V:100 mV / DIV Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS15BA101 DS15BA101 www.ti.com SNLS234J – OCTOBER 2006 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision I (April 2013) to Revision J • Page Changed layout of National Data Sheet to TI format ............................................................................................................ 6 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS15BA101 7 PACKAGE OPTION ADDENDUM www.ti.com 12-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) DS15BA101SD/NOPB ACTIVE WSON NGQ 8 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 BA101 DS15BA101SDE/NOPB ACTIVE WSON NGQ 8 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 BA101 DS15BA101SDX/NOPB ACTIVE WSON NGQ 8 4500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 BA101 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS15BA101SD/NOPB WSON NGQ 8 DS15BA101SDE/NOPB WSON NGQ DS15BA101SDX/NOPB WSON NGQ SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 8 250 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 8 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS15BA101SD/NOPB WSON NGQ 8 1000 213.0 191.0 55.0 DS15BA101SDE/NOPB WSON NGQ 8 250 213.0 191.0 55.0 DS15BA101SDX/NOPB WSON NGQ 8 4500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NGQ0008A SDA08A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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