TI BQ25570RGRR

bq25570
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SLUSBH2B – MARCH 2013 – REVISED SEPTEMBER 2013
Ultra Low Power Harvester Power Management IC with Boost Charger, and Nano-Powered
Buck Converter
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FEATURES
1
•
•
•
•
Ultra Low Power DC/DC Boost Charger
– Cold-start Voltage: VIN ≥ 330 mV
– Continuous Energy Harvesting From VIN as
low as 120 mV
– Input Voltage Regulation Prevents
Collapsing High Impedance Input Sources
– Full Operating Quiescent Current of 488 nA
(typical)
– Ship Mode with < 5 nA From Battery
Energy Storage
– Energy can be Stored to Re-chargeable Liion Batteries, Thin-film Batteries, Supercapacitors, or Conventional Capacitors
Battery Charging and Protection
– Internally Set Undervoltage Level
– User Programmable Overvoltage Levels
Battery Good Output Flag
– Programmable Threshold and Hysteresis
– Warn Attached Microcontrollers of Pending
Loss of Power
– Can be Used to Enable or Disable System
Loads
•
•
Programmable Step Down Regulated Output
(Buck)
– High Efficiency up to 98%
– Supports Peak Output Current up to 110
mA (typical)
Programmable Maximum Power Point Tracking
(MPPT)
– Provides Optimal Energy Extraction From a
Variety of Energy Harvesters including
Solar Panels, Thermal and Piezo Electric
Generators
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
Energy Harvesting
Solar Charger
Thermal Electric Generator (TEG) Harvesting
Wireless Sensor Networks (WSN)
Low Power Wireless Monitoring
Environmental Monitoring
Bridge and Structural Health Monitoring (SHM)
Smart Building Controls
Portable and Wearable Health Devices
Entertainment System Remote Controls
DESCRIPTION
The bq25570 is a highly integrated energy harvesting Nano-Power management solution that is well suited for
meeting the special needs of ultra low power applications. The product is specifically designed to efficiently
acquire and manage the microwatts (µW) to milliwatts (mW) of power generated from a variety of DC sources
like photovoltaic (solar) or thermal electric generators. The bq25570 is the first device of its kind to implement a
highly efficient boost converter/charger with a nano-powered buck converter targeted toward products and
systems, such as wireless sensor networks (WSN) which have stringent power and operational demands. The
design of the bq25570 starts with a dc/dc boost converter/charger that requires only microwatts of power to begin
operating. Once started, the boost converter/charger can effectively extract power from low voltage output
harvesters such as thermoelectric generators (TEGs) or single or dual cell solar panels. The boost converter can
be started with VIN as low as 330 mV, and once started, can continue to harvest energy down to VIN = 100 mV
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
bq25570
SLUSBH2B – MARCH 2013 – REVISED SEPTEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION CONTINUED
The bq25570 also implements a programmable maximum power point tracking sampling network to optimize the
transfer of power into the device. The fraction of open circuit voltage that is sampled and held can be controlled
by pulling VOC_SAMP high or low (80% or 50% respectively) or by using external resistors. This sampled
voltage is maintained via internal sampling circuitry and held with an external capacitor (CREF) on the
VREF_SAMP pin. For example, solar cells typically operate with a maximum power point (MPP) of 80% of their
open circuit voltage. Connecting VOC_SAMP to VSTOR sets the MPPT threshold to 80% and results in the IC
regulating the voltage on the solar cell to ensure that the VIN_DC voltage does not fail below the voltage on
CREF which equals 80% of the solar panel's open circuit voltage. Alternatively, an external reference voltage can
be provided by a MCU to produce a more complex MPPT algorithm. In addition to the boost charging front end,
the bq25570 provides the system with an externally programmable regulated supply via the buck converter. The
regulated output has been optimized to provide high efficiency across low output currents (< 10 µA) to high
currents (~110 mA).
The bq25570 is designed with the flexibility to support a variety of energy storage elements. The availability of
the sources from which harvesters extract their energy can often be sporadic or time-varying. Systems will
typically need some type of energy storage element, such as a re-chargeable battery, super capacitor, or
conventional capacitor. The storage element will make certain constant power is available when needed for the
systems. The storage element also allows the system to handle any peak currents that can not directly come
from the input source.
To prevent damage to a customer’s storage element, both maximum and minimum voltages are monitored
against the internally set under-voltage (UV) and user programmable over-voltage (OV) levels.
To further assist users in the strict management of their energy budgets, the bq25570 toggles the battery good
(VBAT_OK) flag to signal an attached microprocessor when the voltage on an energy storage battery or
capacitor has dropped below a pre-set critical level. This should trigger the reduction of load currents to prevent
the system from entering an under voltage condition. There is also independent enable signals to allow the
system to control when to run the regulated output or even put the whole IC into an ultra-low quiescent current
sleep state.
All the capabilities of bq25570 are packed into a small foot-print 20-lead 3.5mm x 3.5 mm QFN package (RGR).
2
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SLUSBH2B – MARCH 2013 – REVISED SEPTEMBER 2013
TYPICAL APPLICATION SCHEMATIC
CSTOR
VOC_SAMP
L1
CIN
+
VSTOR
BAT
VBAT
LBOOST
VREF_SAMP
LBUCK
Boost
Controller
+
-
VSS
System
Load
VSS
Cold Start
VBAT
GPIO2
VOUT_EN
GPIO3
VBAT_OK
ROV2
VBAT_OV
EN
VRDIV
GPIO1
OK_HYST
Nano-Power
Management
Host
OK_PROG
VSTOR
COUT
Buck
Controller
MPPT
VIN_DC
L2
VOUT
CREF
VOUT_SET
Solar
Cell
CBYP
ROK3
bq25570
ROUT2
ROK2
ROV1
ROUT1
ROK1
ORDERING INFORMATION
(1)
PART NO.
PACKAGE
bq25570
QFN RGR
ORDERING NUMBER
(TAPE AND REEL) (1)
PACKAGE
MARKING
QUANTITY
bq25570RGRR
B5570
3000
bq25570RGRT
B5570
250
The RGR package is available in tape on reel. Add R suffix to order quantities of 3000 parts per reel, T suffix for 250 parts per reel.
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bq25570
SLUSBH2B – MARCH 2013 – REVISED SEPTEMBER 2013
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
VIN_DC, VOC_SAMP, VREF_SAMP, VBAT_OV, VRDIV, OK_HYST,
OK_PROG, VBAT_OK, VBAT, VSTOR, LBOOST, EN, VOUT_EN,
VOUT_SET, LBUCK, VOUT (2)
Input voltage
UNIT
MIN
MAX
–0.3
5.5
V
Peak Input Power, PIN_PK
400
mW
Operating junction temperature range, TJ
–40
125
°C
Storage temperature range, TSTG
–65
150
°C
(1)
(2)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS/ground terminal.
THERMAL INFORMATION
bq25570
THERMAL METRIC (1) (2)
θJA
Junction-to-ambient thermal resistance
34.6
θJCtop
Junction-to-case (top) thermal resistance
49.0
θJB
Junction-to-board thermal resistance
12.5
ψJT
Junction-to-top characterization parameter
0.5
ψJB
Junction-to-board characterization parameter
12.6
θJCbot
Junction-to-case (bottom) thermal resistance
1.0
(1)
(2)
UNITS
RGR (20 PINS)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
spacing
RECOMMENDED OPERATING CONDITIONS
MIN
VIN(DC)
DC input voltage into VIN_DC (1)
(2)
NOM
MAX
0.12
4.0
2.0
5.5
VBAT, VOUT
Voltage range
CIN
Capacitance on VIN_DC pin
4.7
CSTOR
Capacitance on VSTOR pin
4.7
COUT
Capacitance on VOUT pin
10
CBAT
Capacitance or battery with at least the same equivalent capacitance on
VBAT pin
CREF
Capacitance on VREF_SAMP that stores the samped VIN reference
ROC1 + ROC2
ROK 1 + ROK 2 + ROK3
UNIT
V
V
µF
µF
22
µF
100
µF
9
10
11
nF
Total resistance for setting for MPPT reference if needed
18
20
22
MΩ
Total resistance for setting VBAT_OK threshold voltage.
11
13
15
MΩ
ROUT1 + ROUT2
Total resistance for setting VOUT threshold voltage.
11
13
15
MΩ
ROV1 + ROV2
Total resistance for setting VBAT_OV voltage.
11
13
15
MΩ
L1
Inductance on LBOOST pin
22
L2
Inductance on LBUCK pin
4.7
TA
Operating free air ambient temperature
–40
85
°C
TJ
Operating junction temperature
–40
105
°C
(1)
(2)
4
µH
10
µH
Maximum input power ≤ 400 mW. Cold start has been completed
VBAT_OV setting must be higher than VIN_DC
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SLUSBH2B – MARCH 2013 – REVISED SEPTEMBER 2013
ELECTRICAL CHARACTERISTICS
Over recommended temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply for
conditions of VSTOR = 4.2 V, VOUT = 1.8 V. External components, CIN = 4.7 µF, L1 = 22 µH, CSTOR= 4.7 µF, L2 = 10 µH,
COUT = 22 µF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4000
mV
285
mA
400
mW
330
400
mV
1.73
1.9
V
BOOST CHARGER
VIN(DC)
DC input voltage into VIN_DC
Cold-start completed
120
I-CHG(CBC_LIM)
Cycle-by-cycle current limit of charger
0.5V < VIN < 4.0 V; VSTOR
= 4.2 V
PIN
Input power range for normal charging
VBAT_OV > VSTOR >
VSTOR_CHGEN
VIN(CS)
Minimum input voltage for cold start
circuit to start charging VSTOR
VBAT < VBAT_UV; VSTOR
= 0 V; 0°C < TA < 85°C
VSTOR_CHGEN
Voltage on VSTOR when cold start
operation ends and normal charger
operation commences
PIN(CS)
Minimum cold-start input power for
VSTOR to reach VSTOR(CHGEN) and
allow normal charging to commence
VSTOR < VSTOR(CHGEN)
5
µW
tBAT_HOT_PLUG
Time for which switch between VSTOR
and VBAT closes when battery is hot
plugged into VBAT
Battery resistance = 300
Ω, Battery voltage = 3.3V
50
ms
VIN_DC = 0V; VSTOR =
2.1V; TJ = 25°C
488
230
0.005
1.6
QUIESCENT CURRENTS
EN = 0, VOUT_EN = 1 - Full operating
mode
IQ
EN = 0, VOUT_EN = 0 - Partial standby
mode
VIN_DC = 0V; VSTOR =
2.1V; –40°C < TJ < 85°C
VIN_DC = 0V; VSTOR =
2.1V; TJ = 25°C
EN = 1, VOUT_EN = x - Ship mode
900
445
VIN_DC = 0V; VSTOR =
2.1V; –40°C < TJ < 85°C
VBAT = 2.1 V; TJ = 25°C;
VSTOR = VIN_DC = 0 V
700
615
815
1
VBAT = 2.1 V; –40°C < TJ
< 85°C; VSTOR = VIN_DC
=0V
nA
5
30
MOSFET RESISTANCES
RDS(ON)-BAT
ON resistance of switch between VBAT
and VSTOR
Charger low side switch ON resistance
RDS(ON)_CHG
Charger high side switch ON resistance
Charger low side switch ON resistance
Charger high side switch ON resistance
Buck low side switch ON resistance
RDS(ON)_BUCK
Buck high side switch ON resistance
Buck low side switch ON resistance
Buck high side switch ON resistance
VBAT = 4.2 V
VBAT = 4.2 V
VBAT = 2.1 V
VBAT = 4.2 V
VBAT = 2.1 V
0.95
1.50
0.70
0.90
2.30
3.00
0.80
1.00
3.70
4.80
0.80
1.00
1.60
2.00
1.00
1.20
2.40
2.90
Ω
Ω
Ω
fSW_CHG
Maximum charger switching frequency
1.0
MHz
fSW_BUCK
Maximum buck switching frequency
500
kHz
TTEMP_SD
Junction temperature when charging is
discontinued
125
C
VBAT_OV > VSTOR >
1.8V
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ELECTRICAL CHARACTERISTICS (continued)
Over recommended temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply for
conditions of VSTOR = 4.2 V, VOUT = 1.8 V. External components, CIN = 4.7 µF, L1 = 22 µH, CSTOR= 4.7 µF, L2 = 10 µH,
COUT = 22 µF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BATTERY MANAGEMENT
VBAT_OV
Programmable voltage range for
overvoltage threshold
VBAT increasing
Battery over-voltage hysteresis (internal)
VBAT decreasing;
VBAT_OV = 5.25V
VBAT_UV
Under-voltage threshold
VBAT decreasing
VBAT_UV_HYST
Battery under-voltage hysteresis (internal) VBAT increasing
VBAT_OK_HYST
Programmable voltage range of digital
signal indicating VSTOR (=VBAT) is OK
VBAT_OV_HYST
VBAT_OK_PROG
VBAT_ACCURACY
VBAT_OK(H)
VBAT_OK(L)
VBAT increasing
Programmable voltage range of digital
signal indicating VSTOR (=VBAT) is OK
VBAT decreasing
Overall Accuracy for threshold values
VBAT_OV, VBAT_OK
Selected resistors are 0.1%
tolerance
VBAT_OK (High) threshold voltage
VBAT_OK (Low) threshold voltage
2.2
1.91
5.5
V
24
55
mV
1.95
2.0
V
15
32
mV
VBAT_UV
VBAT_OV
V
VBAT_UV
VBAT_OK
_HYST –
50
mV
-2
2
%
Load = 10 µA
VSTOR –
200
mV
Load = 10 µA
100
mV
ENABLE THRESHOLDS
EN(H)
Voltage for EN high setting. Relative to
VBAT.
VBAT = 4.2V
EN(L)
Voltage for EN low setting
VBAT = 4.2V
VOUT_EN(H)
Voltage for VOUT_EN High setting.
Relative to VSTOR.
VSTOR = 4.2V
VOUT_EN(L)
Voltage for VOUT_EN Low setting.
VSTOR = 4.2V
VBAT –
0.2
V
0.3
VSTOR –
0.2
V
V
0.3
V
BIAS and MPPT CONTROL STAGE
VOC_SAMPLE
Time period between two MPPT samples
VOC_STLG
Settling time for MPPT sample
measurement of VIN_DC open circuit
voltage
Device not switching
VIN_REG
Regulation of VIN_DC during charging
0.5 V < VIN < 4 V; IIN(DC)
= 10 mA
MPPT_80
Voltage on VOC_SAMP to set MPPT
threshold to 0.80 of open circuit voltage of
VIN_DC
MPPT_50
Voltage on VOC_SAMP to set MPPT
threshold to 0.50 of open circuit voltage of
VIN_DC
VBIAS
Internal reference for the programmable
voltage thresholds
6
16
s
256
ms
10%
VSTOR –
0.015
V
15
VSTOR ≥ VSTOR_CHGEN
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1.205
1.21
1.217
mV
V
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SLUSBH2B – MARCH 2013 – REVISED SEPTEMBER 2013
ELECTRICAL CHARACTERISTICS
Over recommended ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply
for conditions of VSTOR = 4.2 V, VOUT = 1.8 V. External components, CIN = 4.7 µF, L1 = 22 µH, CSTOR = 4.7 µF, L2 = 10 µH,
COUT = 22 µF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BUCK CONVERTER
VOUT
Output regulation (excluding resistor
tolerance error)
IOUT = 10 mA;
1.3 V < VOUT < 3.3 V
Output line regulation
IOUT = 10 mA;
VSTOR = 2.1 V to 5.5 V,
COUT = 22 µF
0.09
%/V
Output load regulation
IOUT = 100 µA to 95 mA,
VSTOR = 3.6 V, COUT =
22 µF
-0.01
%/mA
Output ripple
VSTOR = 4.2V, IOUT = 1
mA,
COUT = 22 μF
30
mVpp
Programmable voltage range for output
voltage threshold
2
VSTOR
– 0.2 (1)
1.3
IOUT
Output Current
VSTOR = 3.3V; VOUT =
1.8 V
tSTART-STBY
Startup time with EN low and VOUT_EN
transition to high (Standby Mode)
tSTART-SHIP
I-BUCK(CBC-LIM)
(1)
–2
93
%
V
110
mA
COUT = 22 µF
250
μs
Startup time with VOUT_EN high and EN
transition from high to low (Ship Mode)
COUT = 22 µF
100
ms
Cycle-by-cycle current limit of buck
converter
2.4 V < VSTOR < 5.5 V;
1.3 V < VOUT < 3.3 V
160
185
205
mA
The dropout voltage can be computed as the maximum output current times the buck high side resistance.
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DEVICE INFORMATION
VSS
1
VIN_DC
2
VOC_SAMP
3
VREF_SAMP
EN
LBOOST
VSTOR
VBAT
NC
LBUCK
RGT PACKAGE
(TOP VIEW)
20
19
18
17
16
15
VSS
14
VOUT
13
VBAT_OK
4
12
VOUT_SET
5
11
OK_PROG
9
10
OK_HYST
VBAT_OV
8
NC
7
VRDIV
6
VOUT_EN
bq25570
RGR
3.5x3.5mm
Figure 1. bq25570 3.5mm x 3.5mm QFN-20 Package
PIN FUNCTIONS
PIN
NO.
8
NAME
I/O TYPE
DESCRIPTION
1
VSS
Input
Power ground for the boost converter.
2
VIN_DC
Input
DC voltage input from energy harvesting source. Connect at least a 4.7 µF capacitor as
close as possible between this pin and pin 1.
3
VOC_SAMP
Input
Sampling pin for MPPT network. Connect to VSTOR to sample at 80% of input soure open
circuit voltage. Connect to GND for 50% or connect to the mid-point of external resistor
divider between VIN_DC and GND.
4
VREF_SAMP
Input
5
EN
Iinput
Active low digital programming input for enabling/disabling the IC. Connect to GND to
enable the IC.
6
VOUT_EN
Input
Active high digital programming input for enabling/disabling the buck converter. Connect to
VSTOR to enable the buck converter.
7
VBAT_OV
Input
Connect to the mid-point of external resistor divider between VRDIV and GND for setting
the VBAT overvoltage threshold.
8
VRDIV
Output
Sample and hold circuit output for the reference set by the MPPT per VOC_SAMP.
Connect a 0.01 µF capacitor from this pin to GND.
Connect high side of resistor divider networks to this biasing voltage.
9
NC
Input
Connect to ground using the IC's PowerPad.
10
OK_HYST
Input
Connect to the mid-point of external resistor divider between VRDIV and GND for setting
the VBAT_OK hystersis threshold.
11
OK_PROG
Input
Connect to the mid-point of external resistor divider between VRDIV and GND for setting
the VBAT_OK threshold.
12
VOUT_SET
Input
Connect to the mid-point of external resistor divider between VRDIV and GND for setting
the VOUT regulation set point.
13
VBAT_OK
Output
Digital output for battery good indicator. Internally referenced to the VSTOR voltage.
14
VOUT
Output
Buck converter output. Connect at least 22 µF output capacitor between this pin and pin 15
(VSS).
15
VSS
Supply
Power ground for the buck converter and analog/signal ground for the resistor dividers and
VREF_SAMP capacitor.
16
LBUCK
I/O
Inductor connection for the buck converter switching node. Connect at least a 4.7 µH
inductor between this pin and pin 14 (VOUT).
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PIN FUNCTIONS (continued)
PIN
NO.
NAME
17
NC
18
VBAT
19
VSTOR
20
LBOOST
I/O TYPE
Input
I/O
Output
I/O
DESCRIPTION
Connect to ground using the IC's PowerPad.
Connect a rechargeable storage element with at least 100uF of equivalent capacitance
between this pin and either VSS pin.
Connection for the output of the boost converter/charger. Connect at least a 4.7 µF
capacitor in parallel with a 0.1 µF capacitor as close as possible to between this pin and pin
1 (VSS).
Inductor connection for the boost converter switching node. Connect a 22 µH inductor
between this pin and pin 2 (VIN_DC).
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TYPICAL APPLICATION CIRCUITS
VBAT_OV = 3.11 V, VBAT_OK = 2.39 V, VBAT_OK_HYST = 2.80 V, VOUT=1.80V, MPPT (V OC) = 80%
L1 = 22 µH, L2 = 10 µH, CIN = CSTOR = 4.7 µF, CBYP=0.1 µF, CREF = 10 nF, COUT = 22 µF
ROK1 = 5.62 MΩ, ROK2 = 5.49 MΩ, ROK3 = 1.87 MΩ, ROV1 = 7.5 MΩ, ROV2 = 5.36 MΩ,
ROUT1= 8.66 MΩ, ROUT2 = 4.22 MΩ
CSTOR
VOC_SAMP
L1
CIN
+
VSTOR
BAT
VBAT
LBOOST
VREF_SAMP
LBUCK
Boost
Controller
+
VSS
VIN_DC
COUT
Buck
Controller
MPPT
System
Load
VSS
Cold Start
VBAT
GPIO2
VOUT_EN
GPIO3
VBAT_OK
ROV2
VBAT_OV
EN
VRDIV
GPIO1
OK_HYST
Nano-Power
Management
Host
OK_PROG
VSTOR
L2
VOUT
CREF
-
ROK3
VOUT_SET
Solar
Cell
CBYP
bq25570
ROUT2
ROK2
ROV1
ROUT1
ROK1
Figure 2. Typical Solar Application Circuit
10
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SLUSBH2B – MARCH 2013 – REVISED SEPTEMBER 2013
VBAT_OV = 4.18V, VBAT_OK = 3.5 V, VBAT_OK_HYST = 3.7 V, VOUT=2.5V, MPPT (V OC) = 50%
L1 = 22 µH, L2 = 10 µH, CIN = CSTOR = 4.7 µF, CBYP=0.1 µF, CREF = 10 nF, COUT = 22 µF
ROK1 = 4.22 MΩ, ROK2 = 8.06 MΩ, ROK3 = 0.698 MΩ, ROV1 = 6.04 MΩ, ROV2 = 7.87 MΩ,
ROUT1 = 6.19 MΩ, ROUT2 = 6.65 MΩ
CBYP
CSTOR
VOC_SAMP
L1
CIN
+
VSTOR
BAT
VBAT
LBOOST
VREF_SAMP
LBUCK
Boost
Controller
TEG
VOUT
CREF
VSS
Buck
Controller
MPPT
VIN_DC
VSTOR
L2
System
Load
COUT
VSS
Cold Start
VBAT
GPIO3
VBAT_OK
ROV2
VOUT_SET
VOUT_EN
OK_HYST
GPIO2
VBAT_OV
EN
VRDIV
GPIO1
OK_PROG
Nano-Power
Management
Host
ROK3
bq25570
ROUT2
ROK2
ROUT1
ROV1
ROK1
(1)
See the Capacitor Selection section for guidance on sizing CSTOR
Figure 3. Typical TEG Application Circuit
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VBAT_OV = 3.31 V, VBAT_OK = 2.82 V, VBAT_OK_HYST = 3.12 V, VOUT = 1.30V, MPPT (V OC) = 40%
L1 = 22 µH, L2 = 10 µH, CIN = CSTOR = 4.7 µF, CBYP=0.1 µF, CREF = 10 nF, COUT = 22 µF
ROK1 = 4.99 MΩ, ROK2 = 6.65 MΩ, ROK3 = 1.24 MΩ, ROV1 = 6.98 MΩ, ROV2 = 5.76 MΩ
ROUT1 = 12.1 MΩ, ROUT2 = 0.909 MΩ, ROC1 = 8.06 MΩ, ROC2 = 12 MΩ
CSTOR
ROC2
L1
CIN
Vibration
Element
+
BAT
ROC1
VOC_SAMP
MA4X79600LCT-ND
CBYP
VSTOR
VBAT
LBOOST
VREF_SAMP
LBUCK
Boost
Controller
VOUT
CREF
VSS
Buck
Controller
MA4X79600LCT-ND
MPPT
VIN_DC
VSTOR
L2
System
Load
COUT
VSS
Cold Start
VBAT
Nano-Power
Management
GPIO1
ROV2
ROK3
VOUT_SET
OK_HYST
VBAT_OK
OK_PROG
VOUT_EN
GPIO3
VBAT_OV
Host GPIO2
VRDIV
EN
bq25570
ROUT2
ROK2
ROUT1
ROV1
ROK1
(1)
See the Capacitor Selection section for guidance on sizing CSTOR
Figure 4. Typical Externally Set MPPT Application Circuit
12
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VBAT_OV = 3.11 V, VBAT_OK = 2.39 V, VBAT_OK_HYST = 2.80 V, VOUT=1.80V, MPPT (V OC) = 80%
L1 = 22 µH, L2 = 10 µH, CIN = CSTOR = 4.7 µF, CBYP=0.1 µF, CREF = 10 nF, COUT = 22 µF
ROV1 = 7.5 MΩ, ROV2 = 5.36 MΩ
ROUT1= 8.66 MΩ, ROUT2 = 4.22 MΩ,
CSTOR
VOC_SAMP
L1
CIN
+
VSTOR
BAT
VBAT
LBOOST
VREF_SAMP
LBUCK
Boost
Controller
+
-
VSS
System
Load
VSS
Cold Start
VBAT
GPIO2
VOUT_EN
GPIO3
VBAT_OK
VBAT_OV
EN
VRDIV
GPIO1
OK_HYST
Nano-Power
Management
Host
OK_PROG
VSTOR
COUT
Buck
Controller
MPPT
VIN_DC
L2
VOUT
CREF
VOUT_SET
Solar
Cell
CBYP
bq25570
ROUT2
ROV2
VSTOR
ROV1
ROUT1
Figure 5. Typical VBAT_OK Disabled Application Circuit
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HIGH-LEVEL FUNCTIONAL BLOCK DIAGRAM
VSTOR
LBST
VBAT
LBUCK
PFM Buck
Controller
VOUT
VOUT_SET
PFM Boost Charger
Controller
VOUT_EN
VSS
VSS
Cold-start
Unit
VIN_DC
Enable
Enable
Interrupt
VBAT_OK
VOC_SAMP
OK_PROG
BAT_SAVE
+
VREF
VREF_SAMP
+
MPPT
Controller
Battery Threshold
Control
OT
OK
OK_HYST
UV
OV
Temp
Sensing
Element
+
+
Vref
Bias Reference &
Oscillator
VREF
VBAT_UV
EN
VBAT_OV
VRDIV
Figure 6. High-Level Functional Diagram
14
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TYPICAL CHARACTERISTICS
Table of Graphs
Unless otherwise noted, graphs were taken using Figure 2 with CIN = 4.7µF, L1 = Coilcraft 22µH LPS4018,
CSTOR = 4.7µF, L2 = Toko 10 µH DFE252012C, COUT = 22µF, VBAT_OV=4.2V, VOUT=1.8V
vs. Input Voltage
Charger Efficiency (η) (1)
vs. Input Current
VSTOR Quiescent Current
vs. VSTOR Voltage
VBAT Quiescent Current
vs. VBAT Voltage
Buck Efficiency (η)
Normalized Buck Output Voltage
Buck Maximum Output Current
vs. Input Voltage
FIGURE
IN= 10 µA
Figure 7
IN= 100 µA
Figure 8
IIN = 10 mA
Figure 9
VIN = 2.0 V
Figure 10
VIN = 1.0 V
Figure 11
VIN = 0.5 V
Figure 12
VIN = 0.2 V
Figure 13
EN = 1, VOUT_EN = X (Ship Mode)
Figure 14
EN = 0, VOUT_EN = 0 (Standby Mode)
Figure 15
EN = 0, VOUT_EN = 1 (Active Mode)
Figure 16
vs. Output Current
Figure 17
vs. Input Voltage
Figure 18
vs. Output Current
Figure 19
vs. Input Voltage
Figure 20
vs. Temperature
Figure 21
VOUT = 1.8V - 100mV
Figure 22
vs. Output Current
Figure 23
vs. Input Voltage
Figure 24
vs.Output Current
Figure 25
vs. Input Voltage
Figure 26
Startup by taking EN low (from
ship mode)
VBAT = 3.4-V charged Li coin cell; VIN_DC
= 1.0 V power supply; MPPT=50%; ZIN =
100Ω
ROUT = open
Figure 27
Startup by taking EN low (from
ship mode), including VOUT
VBAT = 3.4-V charged Li coin cell; VIN_DC
= 1.0 V power supply; MPPT=50%; ZIN =
100Ω
ROUT = 90 Ω
Figure 28
Startup by taking VOUT_EN high
(from Standby mode)
VBAT = 3.2-V charged Li coin cell; VIN_DC
= 2.0 V power supply; MPPT=50%; ZIN =
100Ω
ROUT = 90 Ω
Figure 29
MPPT Operation
VBAT = 3.2-V charged Li coin cell; VIN_DC
= 2.0 V power supply; ZIN = 100Ω
VOC_SAMP = VSTOR to GND to
VSTOR
Figure 30
100mA Load Transient on VOUT
VBAT = 3.9-V charged 0.5F super cap;
VIN_DC = 2.0 V power supply;
MPPT=50%; ZIN=100Ω
ROUT = open to 18 Ω to open
Figure 31
ROUT = open to 36 Ω to open
Figure 32
Buck Major Switching Frequency
Buck Output Ripple
50mA Load Transient on VOUT
Charger Operational Waveform
during 50mA Load Transient
Buck Operational Waveform
during 50mA Load Transient
VRDIV Waveform
VRDIV Waveform - Zoom
VBAT_OK Operation
Charging a Super Cap on VBAT
Charging a Super Cap on VOUT
(1)
VBAT = 3.2-V charged Li coin cell; VIN_DC
= 2.0 V power supply; MPPT=50%; ZIN =
100Ω
Figure 33
ROUT = 36 Ω
Figure 34
Figure 35
VSTOR = 4.2V; VOUT = 1.8V
Figure 36
VSTOR ramped from 0 V to 4.2 V to 0 V
VIN_DC = sourcemeter with compliance =
1.2 V and ISC = 1.0 mA
Figure 37
VBAT = 120 mF super capacitor
Figure 38
VOUT = 120 mF super capacitor
Figure 39
See SLUA691 for an explanation on how to take these measurements. Because the MPPT feature cannot be disabled on the bq25570,
these measurements need to be taken in the middle of the 16 s sampling period.
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100
100
90
90
IIN = 10PA
80
80
70
Efficiency (%)
Efficiency (%)
70
60
50
40
30
IIN = 100 PA
60
50
40
30
20
VSTOR = 2.0 V
VSTOR = 3.0 V
VSTOR = 5.5 V
20
VSTOR = 2.0 V
10
10
VSTOR = 3.0 V
0
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
Input Voltage (V)
Input Voltage (V)
Figure 7. Charger Efficiency vs Input Voltage
Figure 8. Charger Efficiency vs Input Voltage
100.00
100
90
90.00
IIN = 10 mA
70
Efficiency (%)
Efficiency (%)
80
60
50
40
VSTOR = 2.0 V
VSTOR = 3.0 V
VSTOR = 5.5 V
30
20
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
80.00
VIN = 2 V
70.00
60.00
VSTOR = 2.2 V
VSTOR = 3.0 V
VSTOR = 5.5 V
50.00
40.00
0.01
0.1
Input Voltage (V)
Figure 9. Charger Efficiency vs Input Voltage
100.00
100
90.00
90
100
VIN = 0.5 V
80
Efficiency (%)
Efficiency (%)
10
Figure 10. Charger Efficiency vs Input Current
80.00
VIN = 1 V
70.00
60.00
50.00
40.00
VSTOR = 2.0 V
VSTOR = 3.0 V
VSTOR = 5.5 V
30.00
20.00
0.01
0.1
1
10
100
70
60
50
40
VSTOR = 1.8 V
VSTOR = 3.0 V
VSTOR = 5.5 V
30
20
0.01
Input Current (mA)
0.1
1
10
100
Input Current (mA)
Figure 11. Charger Efficiency vs Input Current
16
1
Input Current (mA)
Figure 12. Charger Efficiency vs Input Current
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1600
90
VIN = 0.2 V
Efficiency (%)
80
70
60
50
VSTOR = 3.0 V
40
VSTOR = 2.0 V
30
Input Quiescent Current (nA)
100
TA
TA =
= 85C
85oC
1400
TA
TA = 25C
25oC
1200
TA
TA = -40C
-40oC
1000
800
600
400
200
VSTOR = 5.5 V
20
0
0.0
0.1
1.0
10.0
100.0
2
3
Input Current (mA)
Figure 13. Charger Efficiency vs Input Current
5
Figure 14. VSTOR Quiescent Current vs VSTOR Voltage:
Standby Mode
700
2000
o
TA =
85C
T
A = 85 C
Input Quiescent Current (nA)
TA =
= 25C
o
T
A 25 C
Input Quiescent Current (nA)
4
Input Voltage (V)
oC
TA = 85
85C
T
A
1500
TA
T
A=
oC
-40C
-40
1000
500
600
T
25oC
TA
A = 25C
500
T
= -40C
-40oC
TA
A=
400
300
200
100
0
0
2
3
4
2
5
3
4
5
Input Voltage (V)
Input Voltage (V)
Figure 15. VSTOR Quiescent Current vs VSTOR Voltage:
Active Mode
Figure 16. VBAT Quiescent Current vs VBAT Voltage: Ship
Mode
100
100
90
95
80
90
70
Efficiency (%)
Efficiency (%)
VOUT = 1.8V
VOUT = 1.8V, TA = 25oC
60
VSTOR = 2.1V
VSTOR = 3.6V
VSTOR = 5.5V
50
40
0.001
0.01
0.1
1
10
100
85
80
IOUT = 0.01mA
IOUT = 0.1mA
IOUT = 1mA
IOUT = 10mA
IOUT = 100mA
75
70
2.0
3.0
Output Current (mA)
4.0
5.0
Input Voltage (V)
Figure 17. Buck Efficiency vs Output Current
Figure 18. Buck Efficiency vs Input Voltage
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1.02
1.004
VOUT = 1.8V
VOUT = 1.8V
Normalized VOUT
Normalized VOUT
1.002
1
IOUT = 0.001mA
IOUT = 0.1mA
IOUT = 10mA
0.998
IOUT = 0.01mA
IOUT = 1mA
IOUT = 90mA
0.996
1.01
1
0.99
VSTOR = 5.5V
0.994
VSTOR = 3.6V
0.992
2.0
3.0
4.0
0.98
0.001
5.0
VSTOR = 2.1V
0.01
0.1
VSTOR Voltage (V)
Figure 19. Normalized Buck Output Voltage vs Input Voltage
1.02
10
100
Figure 20. Normalized Buck Output Voltage vs Output
Current
170
IOUT = 0.01mA
IOUT = 1mA
IOUT = 70mA
VOUT = 1.8V
1.01
1
0.99
o
TA =
= 85C
T
A 85 C
VOUT = 1.8V - 100 mV
160
Output Current (mA)
Normalized VOUT
1
Output Current (mA)
oC
TA
25C
T
A = 25
150
oC
T
TA
0C
A=0
140
o
T
TA
-40CC
A = -40
130
120
110
100
90
0.98
80
-40 -30 -20 -10
0
10
20
30
40
50
60
70
2
80
3
Temperature (oC)
Figure 21. Normalized Buck Output Voltage vs Temperature
120
VOUT = 1.8V
Major Switching Frequency (kHz)
Major Switching Frequency (kHz)
5
Figure 22. Buck Maximum Output Current vs Input Voltage
120
100
80
60
40
VSTOR= 2.1V
VSTOR = 3V
VSTOR = 4.2V
VSTOR = 5.5V
20
0
0
10
20
30
40
50
60
VOUT = 1.8V
100
80
IOUT
IOUT
IOUT
IOUT
60
= 0.5mA
= 5mA
= 100mA
= 50mA
40
20
0
70
80
90
100
2.1
Output Current (mA)
2.6
3.1
3.6
4.1
4.6
5.1
VSTOR Voltage (V)
Figure 23. Buck Major Switching Frequency vs Output
Current
18
4
VSTOR Voltage (V)
Figure 24. Buck Major Switching Frequency vs Input
Voltage
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45
45
40
40
35
30
25
20
VOUT = 1.8V
15
10
VSTOR = 2.1V
VSTOR = 3V
VSTOR = 4.2V
VSTOR = 5.5V
5
0
0
10
20
30
40
50
60
70
80
90
100
Output Voltage Ripple (mV)
Output Voltage Ripple (mV)
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VOUT = 1.8V
35
30
25
20
15
10
IOUT
IOUT
IOUT
IOUT
5
0
2.1
Output Current (mA)
2.6
3.1
3.6
4.1
4.6
= 0.5mA
= 5mA
= 50mA
= 100mA
5.1
VSTOR Voltage (V)
Figure 25. Buck Output Voltage Ripple vs Output Current
Figure 26. Buck Output Voltage Ripple vs Input Voltage
Figure 27. Startup by taking EN low (from Ship mode)
Figure 28. Startup by taking EN low (from Ship mode),
including VOUT
Figure 29. Startup by taking VOUT_EN high (from Standby
mode)
Figure 30. MPPT Operation
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Figure 31. 100mA Load Transient on VOUT
Figure 32. 50 mA Load Transient on VOUT
Figure 33. Charger Operational Waveforms during 50mA
Load Transient
Figure 34. Buck Operational Waveforms during 50mA Load
Transient
Figure 35. VRDIV Waveform
Figure 36. VRDIV Waveform - Zoom
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Figure 37. VBAT_OK Operation
Figure 38. Charging a Super Cap on VBAT
Figure 39. Charging a Super Cap on VOUT
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DETAILED DESCRIPTION
Boost Charger Overview
The bq25570 includes both an ultra low quiescent current, efficient synchronous boost converter/charger and
buck converter. The boost converter is intended to be powered from a high impedance DC source, such as a
solar panel, TEG or piezoelectric module; therefore, it regulates its input voltage (VIN_DC) in order to prevent the
input source from collapsing. The boost converter monitors its output voltage (VSTOR) and stops switching when
VSTOR reaches a resistor programmable threshold level. The buck converter is powered from VSTOR. Both
converters are based on a switching regulator architecture which maximizes efficiency while minimizing start-up
and operation power. Both use pulse frequency modulation (PFM) to maintain efficiency, even under light load
conditions. In addition, the boost converter implements battery protection features so that either rechargeable
batteries or capacitors can be used as energy storage elements at the storage element output (VBAT). Figure 6
is a high-level functional block diagram which highlights most of the major functional blocks inside the bq25570.
Enable Controls
There are two enable pins for the bq25570 in order to maximize the flexibility of control for the system. EN high
voltage is relative to VBAT and VOUT_EN is relative to VSTOR. When taken high (relative to VBAT), the EN pin
shuts down the IC completely including the boost converter, battery management circuitry and buck converter. It
also turns off the PFET that connects VBAT to VSTOR. This mode can be described as ship mode, because it
will put the IC in the lowest leakage state and provide a long storage period without discharging the battery
attached to VBAT. If it is not desired to control EN, it is recommended that this pin be tied to VSS, or system
ground. When EN is low, VOUT_EN is used to enable and disable the buck converter. The table below
summarizes the functionailty.
Table 1. Enable Functionality Table
EN PIN
VOUT_EN
PIN
0
0
Partial standby mode. Buck switching converter is off, but VBAT_OK indication is on
0
1
Buck mode and VBAT_OK enabled
1
x
Full standby mode. Switching converter and VBAT_OK indication is off (ship mode)
FUNCTIONAL STATE
Startup Operation
The bq25570 has two circuits for boosting the input voltage, a low-power cold-start circuit, drawing power
excluxively from VIN_DC when ≥ VIN(CS), and the high efficiency main boost converter, with the bias rails
drawing power from VSTOR when ≥ VSTOR_CHGEN and the power stage drawing power from VIN_DC when ≥
VIN(DC) minimum. When EN = 0 and VSTOR ≤ VSTOR_CHGEN, there are two options for charging the VSTOR
capacitor capacitor, CSTOR, to VSTOR_CHGEN for the main boost converter to turn on. The first option is to
allow the cold start circuit to charge VSTOR to VSTOR_CHGEN. Due to the body diode of the PFET connecting
VSTOR and VBAT, the cold start circuit must charge both the capacitor on CSTOR and the storage element
connected to VBAT up to VSTOR_CHGEN. When a rechargeable battery with an open protector is attached, the
charge time is typically short due to the minimum charge needed to close the FET. When large, discharged
super capacitors are attached, the charge time can be signficant. The second option is to connect a storage
element, charged above VSTOR_CHGEN, to VBAT. Assuming the voltages on VSTOR and VBAT are both
below 100mV, when a charged storage element is attached (i.e. hot-plugged) to VBAT, the IC turns on the
internal PFET between the VSTOR and VBAT pins for tBAT_HOT_PLUG in order to charge CSTOR to
VSTOR_CHGEN. If a system load tied to VSTOR prevents the storage element from charging VSTOR within
tBAT_HOT_PLUG, it is recommended to add an external PFET between the system load and VSTOR. An inverted
VBAT_OK signal can be used to drive the gate of this system-isolating PFET. Once the VSTOR pin voltage
reaches the internal under voltage threshold (VBAT_UV), the internal PFET stays on and the main boost
converter / charger begins to charge the storage element if there is sufficient power available at the VIN_DC pin,
as explained below. If VSTOR does not reach VBAT_UV within 50ms, then the PFET turns off and the cold-start
boost converter turns on, also as explained below.
22
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Boost Charger Cold-Start Operation (VSTOR < VSTOR_CHGEN and VIN_DC > VIN(CS) )
If the attached storage element does not charge CSTOR above VSTOR_CHGEN, VIN_DC ≥ VIN(CS) and EN =
0, the cold-start circuit turns on. The cold-start circuit is essentially an unregulated boost converter with lower
efficiency compared to the main boost converter. The energy harvester must supply sufficient power for the IC to
exit cold start. See the Energy Harvester Selection applications section for guidance.
When the CSTOR voltage reaches VSTOR_CHGEN, the main boost regulator starts up. The VSTOR voltage
from the main boost regulator is compared against the battery undervoltage threshold (VBAT_UV). When the
VBAT_UV threshold is reached, the PMOS switch between VSTOR and VBAT turns on, which allows the energy
storage element attached to VBAT to charge up. Cold start is not as efficient as the main boost regulator. If there
is not sufficient power available, it is possible that the cold start circuit continuously runs and the VSTOR output
does not increase above VSTOR_CHGEN for the main boost conveter to start up. The battery management
thresholds are explained later is this section. See the Energy Harvester Selection applications section for
guidance on minimum input power requirements.
Main Boost Converter / Charger Operation (VSTOR > VSTOR_CHGEN and VIN_DC > VIN(DC) )
The main boost converter charges the storage element attached at VBAT with the energy available from the high
impedance input source. For the first 32 ms (typical) after the main converter is turned ON (assuming EN is low),
the charger is disabled to let the input rise to its open-circuit voltage. This is needed to get the reference voltage
which will be used for the remainder of the charger operation till the next MPPT sampling cycle turns ON. The
boost converter employs pulse frequency modulation (PFM) mode of control to regulate the voltage at VIN_DC
close to the desired reference voltage. The reference voltage is set by the MPPT control scheme as described in
the next section. Input voltage regulation is obtained by transferring charge from the input to VSTOR only when
the input voltage is higher than the voltage on pin VREF_SAMP. The current through the inductor is controlled
through internal current sense circuitry. The peak current in the inductor is dithered internally to pre-determined
levels in order to maintain high efficiency of the converter across a wide input current range. The converter
transfers up to a maximum of 100 mA average input current (200mA typical peak inductor current). The boost
converter is disabled when the voltage on VSTOR reaches the OV condition to protect the battery connected at
VBAT from overcharging. In order for the battery to charge to VBAT_OV, the input power must exceed the power
needed for the load on VSTOR. See the Energy Harvester Selection applications section for guidance on
minimum input power requirements.
Maximum Power Point Tracking
Maximum power point tracking (MPPT) is implemented in order to maximize the power extracted from an energy
harvester source. MPPT is performed by periodically sampling a ratio of the open-circuit voltage of the energy
harvester and using that as the reference voltage (VREF_SAMP) to the boost converter. Internally, the boost
converter indirectly modulates the impedance of the energy transfer circuitry by regulating the input voltage
(VIN_DC) to the sampled reference voltage (VREF_SAMP). A new reference voltage is obtained every 16 s
(typical) by periodically disabling the charger for 256 ms (typical) and sampling a ratio of the open-circuit voltage.
For solar harvesters, the maximum power point is typically 70%-80% and for thermoelectric harvesters, the
MPPT is typically 50%. Tying VOC_SAMP to VSTOR internally sets the MPPT regulation point to 80%. Tying
VOC_SAMP to GND internally sets the MPPT regulation point to 50%. If need, the exact ratio for MPPT can be
optimized to meet the needs of the input source being used by connecting external resistors ROC1 and ROC2
between VRDIV and GND with mid-point at VOC_SAMP.
The reference voltage is set by the following expression:
æ
ö
R OC1
VREF_SAMP = VIN_DC(OpenCircuit) ç
÷
è R OC1 + R OC2 ø
(1)
Storage Element / Battery Management
In this section the battery management functionality of the bq25570 integrated circuit (IC) is presented. The IC
has internal circuitry to manage the voltage across the storage element and to optimize the charging of the
storage element. For successfully extracting energy from the source, two different threshold voltages must be
programmed using external resistors, namely battery good threshold (VBAT_OK) and over voltage (OV)
threshold. The two user programmable threshold voltages and the internally set undervoltage threshold
determine the IC's region of operation. Figure 40 show plots of the voltage at the VSTOR pin and the various
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threshold voltages for two use cases 1) when a depleted battery is attached and the charger enters cold start
and 2) when a batttery charged above VBAT_UV is attached. For the best operation of the system, the
VBAT_OK should be used to determine when a load can be applied or removed. A detailed description of the
three voltage thresholds and the procedure for designing the external resistors for setting the three voltage
thresholds are described next.
Voltage (V)
5.5V
VBAT_OV
BOOST CONVERTER OFF
VSTOR=VBAT
MAIN BOOST
CONVERTER
ON
VBAT_OK_HYS
VBAT_OK
VBAT_OK
(VSTOR rising)
VBAT_UV
VSTOR
VSTOR_CHGEN
VDIODE
VBAT
COLD START ON
0V
VIN_DC > 330mV
time
Figure 40. Charger Operation after a Depleted Storage Element is Attached
5.5V
VBAT_OV
BOOST CONVERTER OFF
Voltage (V)
VSTOR=VBAT
VBAT_OK_HYS
MAIN BOOST
CONVERTER
ON
VBAT_OK
VBAT_UV
VBAT_OK
(VSTOR rising)
0V
Attach Storage Element
time
Figure 41. Charger Operation after a Partially Charged Storage Element is Attached
When no input source is attached, the VSTOR node should be discharged to ground before attaching a storage
element. Hot-plugging a storage element that is charged (e.g., the battery protector is closed) and with the
VSTOR node above ground results in the PFET between VSTOR and VBAT remaining off until an input source
is attached. In addition, if a system load attached to VSTOR has fast transients that could pull VSTOR below
VBAT_UV, the internal PFET switch will turn off in order to recharge the CSTOR capacitor to VSTOR_CHGEN.
See the application section for guidance on sizing the VSTOR and/or VBAT capacitance to account for
transients. If the voltage applied at VIN_DC is greater than VSTOR or VBAT then current may flow until the
voltage at the input is reduced or the voltage at VSTOR and VBAT rise. This is considered an abnormal condition
and the boost converter/charger does not operate.
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Battery Undervoltage Protection
To prevent rechargeable batteries from being deeply discharged and damaged, and to prevent completely
depleting charge from a capacitive storage element, the IC has an internally set undervoltage (VBAT_UV)
threshold plus an internal hysteresis voltage (VBAT_UV_HYST). The VBAT_UV threshold voltage when the
battery voltage is decreasing is internally set to 1.95V (typical). The undervoltage threshold when battery voltage
is increasing is given by VBAT_UV plus VBAT_UV_HYST. For most applications, the system load should be
connected to the VSTOR pin while the storage element should be connected to the VBAT pin. Once the VSTOR
pin voltage goes above the VBAT_UV_HYST threshold, the VSTOR pin and the VBAT pins are shorted. The
switch remains closed until the VSTOR pin voltage falls below VBAT_UV. The VBAT_UV threshold should be
considered a fail safe to the system and the system load should be removed or reduced based on the VBAT_OK
signal.
Battery Overvoltage Protection
To prevent rechargeable batteries from being exposed to excessive charging voltages and to prevent over
charging a capacitive storage element, the over-voltage (VBAT_OV) threshold level must be set using external
resistors. This is also the voltage value to which the charger will regulate the VSTOR/VBAT pin when the input
has sufficient power. The VBAT_OV threshold when the battery voltage is rising is given by Equation 2:
æ
ö
R
3
VBAT_OV = VBIAS ç 1 + OV2 ÷
2
R
OV 1 ø
è
(2)
The sum of the resistors is recommended to be no higher than 13 MΩ that is, ROV1 + ROV2 = 13 MΩ. The
overvoltage threshold when battery voltage is decreasing is given by OV_HYST. It is internally set to the over
voltage threshold minus an internal hysteresis voltage denoted by VBAT_OV_HYST. Once the voltage at the
battery exceeds VBAT_OV threshold, the boost converter is disabled. The charger will start again once the
battery voltage falls below the VBAT_OV_HYST level. When there is excessive input energy, the VBAT pin
voltage will ripple between the VBAT_OV and the VBAT_OV_HYST levels. SLUC484 provides help on sizing
and selecting the resistors.
CAUTION
If VIN_DC is higher than VSTOR and VSTOR is equal to VBAT_OV, the input VIN_DC
is pulled to ground through a small resistance to stop further charging of the attached
battery or capacitor. It is critical that if this case is expected, the impedance of the
source attached to VIN_DC be higher than 20 Ω and not a low impedance source.
Battery Voltage within Operating Range (VBAT_OK Output)
The IC allows the user to set a programmable voltage independent of the overvoltage and undervoltage settings
to indicate whether the VSTOR voltage (and therefore the VBAT voltage when the PFET between the two pins is
turned on) is at an acceptable level. When the battery voltage is decreasing the threshold is set by Equation 3:
æ
ö
R
VBAT_OK_PROG = VBIAS ç 1 + O K2 ÷
R OK1 ø
è
(3)
When the battery voltage is increasing, the threshold is set by Equation 4:
æ
R
+ R O K3 ö
VBAT_OK_HYST = VBIAS ç 1 + OK2
÷
R O K1
è
ø
(4)
The sum of the resistors is recommend to be no higher than approximately i.e., ROK1 + ROK2 + ROK3= 13 MΩ. The
logic high level of this signal is equal to the VSTOR voltage and the logic low level is ground. The logic high level
has ~20 KΩ internally in series to limit the available current to prevent MCU damage until it is fully powered. The
VBAT_OK_PROG threshold must be greater than or equal to the UV threshold. For the best operation of the
system, the VBAT_OK should be setup to drive an external PFET between VSTOR and the system load in order
to determine when the load can be applied or removed to optimize the storage element capacity. SLUC484
provides help on sizing and selecting the resistors.
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Step Down (Buck) Converter Operation
The buck regulator takes input power from VSTOR, steps it down and provides a regulated voltage at the OUT
pin. It employs pulse frequency modulation (PFM) control to regulate the voltage close to the desired reference
voltage. The reference voltage is set by the user programmed resistor divider. The current through the inductor is
controlled through internal current sense circuitry. The peak current in the inductor is controlled to maintain high
efficiency of the converter across a wide input current range. The converter delivers an output current up to
110mA typical with a peak inductor current of 200 mA. The buck regulator is disabled when the voltage on
VSTOR drops below the VBAT_UV condition. The buck regulator continues to operate in pass (100% duty cycle)
mode, passing the input voltage to the output, as long as VSTOR is greater than VBAT_UV and less than VOUT.
Programming OUT Regulation Voltage
To set the proper output regulation voltage and input voltage power good comparator, the external resistors must
be carefully selected.
The OUT regulation voltage is then given by Equation 5:
æR
+ ROUT1 ö
VOUT = VBIAS ç OUT2
÷
ROUT1
è
ø
(5)
Note that VBIAS is nominally 1.21V per the electrical specification table. The sum of the resistors is
recommended to be no greater than 13 MΩ , that is, ROUT1 + ROUT2 = 13 MΩ. Higher resistors may result in poor
output voltage regulation and/or input voltage power good threshold accuracies due to noise pickup via the high
impedance pins or reduction of effective resistance due to parasitic resistances created from board assembly
residue. See Layout Considerations section for more details. SLUC484 provides help on sizing and selecting the
resistors.
Buck Converter Startup Behavior
The bq25570 buck converter has two startup responses: 1) from the ship-mode state (EN transitions from high to
low), and 2) from the standby state (VOUT_EN transitions from low to high). The first startup response out of the
ship-mode state has the longest time duration due to the internal circuitry being disabled. This response is shown
in Figure 28. The startup time takes approximately 100ms due to the internal Nano-Power management circuitry
needing to first, complete the 64 ms sample and hold cycle.
Startup from the standby state is shown in Figure 29. This response is much faster due to the internal circuitry
being pre-enabled. The startup time from this state is entirely dependent on the size of the output capacitor. The
larger the capacitor, the longer it will take to charge during startup. With COUT = 22 µF, the startup time is
approximately 400 µs. The buck converter can startup into a pre-biased output voltage.
Steady State Operation and Cycle by Cycle Behavior
Steady state operation for the boost charger is shown in Figure 33 and for the buck converter in
Figure 34. These plots highlight the inductor current waveform, the VSTOR and VOUT voltage ripple, and the
LBOOST and LBUCK switching nodes, respectively. The converters both use hysteretic control and pulse
frequency modulation (PFM) switching in order to maintain high efficiency at light load. As long as the VIN_DC
voltage is above the MPPT regulation set point (i.e. voltage at VREF_SAMP), the boost converter's low-side
power FET turns on and draws current until it reaches its respective peak current limit. These switching bursts
continue until VSTOR reaches the VBAT_OV threshold. The buck converter high-side power FET also turns on
and draws current until it reaches its respective peak current limit, with its switching bursts continuing until VOUT
reaches the VOUT_SET point. This cycle-by-cycle minor switching frequency is a function of each converter's
inductor value, peak current limit and voltage levels on each side of each inductor.
Once each respective capacitor, CSTOR for the boost and COUT for the buck, droops below a minimum value,
the hysteretic switching repeats. The DC voltages on CSTOR and COUT have a ripple voltage riding on top,
caused by each capacitor charging due to the switching bursts and then discharging to a minimum value. The
major frequency and duty cycle of CSTOR's ripple are a function of the VIN_DC regulation, VSTOR system load
and/or VBAT charging current, L1 inductance value and CSTOR capacitance value. The major frequency and
26
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duty cycle of COUT's ripple are a function of the VSTOR voltage, VOUT system load, L2 inductance value and
COUT capacitance value. At heavier output loads (larger output current), the time the converter is off is smaller
when compared to light load conditions. Figure 23 and Figure 24 show the major switching frequency versus load
current and VSTOR voltage, respectively, for the buck converter. Figure 25 and Figure 26 show the output
voltage ripple with COUT = 22 µF versus load current and VSTOR voltage, respectively, for the buck converter.
Nano-Power Management and Efficiency
The high efficiency of the bq25570 converters is achieved via the proprietary Nano-Power management circuitry
and algorithm. This feature essentially samples and holds all references in order to reduce the average quiescent
current. That is, the internal circuitry is only active for a short period of time and then off for the remaining period
of time at the lowest feasible duty cycle. A portion of this feature can be observed in Figure 35 where the VRDIV
node is monitored. Here the VRDIV node provides a connection to the VSTOR voltage (first pulse) and then
generates the reference levels for the VBAT_OV, VBAT_OK and VOUT_SET resistor dividers for a short period
of time. The divided down values at each pin are sampled and held for comparison against VBIAS as part of the
hysteretic control. Since this biases a resistor string, the current through these resistors is only active when the
Nano-Power management circuitry makes the connection—hence reducing the overall quiescent current due to
the resistors. This process repeats every 64 ms.
The bq25570's boost charger efficiency is shown for various input power levels in Figure 7 through Figure 13.
The bq25570's buck converter efficiency versus output current is plotted in Figure 17 and versus input voltage in
Figure 18. All data points were captured by averaging the overall input current. This must be done due to the
periodic biasing scheme implemented via the Nano-Power management circuitry. In order to properly measure
the resulting input current when calculating the output to input efficiency, the input current efficiency data was
gathered using a source meter set to average over at least 50 samples.
Thermal Shutdown
Rechargeable Li-ion batteries need protection from damage due to operation at elevated temperatures. The
application should provide this battery protection and ensure that the ambient temperature is never elevated
greater than the expected operational range of 85°C.
The bq25570 uses an integrated temperature sensor to monitor the junction temperature of the device. Once the
temperature threshold is exceeded, the boost converter/charger is disabled and charging ceases. Once the
temperature of the device drops below this threshold, the boost charger resumes operation. To avoid unstable
operation near the overtemp threshold, a built-in hysteresis of approximately 5°C has been implemented. Care
should be taken to not over discharge the battery in this condition since the boost converter/charger is disabled.
However, if the supply voltage drops to the VBAT_UV setting, then the switch between VBAT and VSTOR will
open and protect the battery even if the device is in thermal shutdown.
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APPLICATION INFORMATION
Energy Harvester Selection
The energy harvesting source (e.g., solar panel, TEG, vibration element) must provide a minimum level of power
for the IC to operate as designed. The IC's minimum input power required to exit cold start can be estimated as
PIN > [([email protected] X 1.8V) + (1.8V2 / RSTOR(CS))] / 0.05
where [email protected] is the storage element leakage current at 1.8V and
RSTOR(CS) is the equivalent resitive load on VSTOR during cold start and 0.05 is an estimate of the worst case
efficiency of the cold start circuit.
Once the IC is out of cold start and the system load has been activated (e.g., using the VBAT_OK signal), the
energy harvesting element must provide the main boost charger with at least enough power to meet the average
system load. Assuming RSTOR(AVG) represents the average resistive load on VSTOR, the simplified equation
below gives an estimate of the IC's minimum input power needed during system operation:
PIN X ηEST > PLOAD = (VBAT_OV2 / RSTOR(AVG) + VBAT_OV * [email protected]_OV)
where ηEST can be derived from the datasheet efficiency curves for the given input voltage and current and
VBAT_OV. The simplified equation above assumes that, while the harvester is still providing power, the system
goes into low power or sleep mode long enough to charge the storage element so that it can power the system
when the harvester eventually is down. Refer to SLUC461 for a design example that sizes the energy harvester.
Storage Element Selection
In order for the charge management circuitry to protect the storage element from over-charging or discharging,
the storage element must be connected to VBAT pin and the system load tied to the VSTOR pin. Many types of
elements can be used, such as capacitors, super capacitors or various battery chemistries. A storage element
with 100uF equivalent capacitance is required to filter the pulse currents of the PFM switching converter. The
equivalent capacitance of a battery can be computed as computed as
CEQ = 2 x mAHrBAT(CHRGD) x 3600 s/Hr / VBAT(CHRGD)
In order for the storage element to be able to charge VSTOR capacitor (CSTOR) within the tVB_HOT_PLUG (50 ms
typical) window at hot-plug; therefore preventing the IC from entering cold start, the time constant created by the
storage element's series resistance (plus the resistance of the internal PFET switch) and equivalent capacitance
must be less than tVB_HOT_PLUG . For example, a battery's resistance can be computed as
RBAT = VBAT / IBAT(CONTINUOUS) from the battery specifications.
The storage element must be sized large enough to provide all of the system load during periods when the
harvester is no longer providing power. The harvester is expected to provide at least enough power to fully
charge the storage element while the system is in low power or sleep mode. Assuming no load on VSTOR (i.e.,
the system is in low power or sleep mode), the following equation estimates charge time from voltage VBAT1 to
VBAT2 for given input power is
PIN x ηEST X tCHRG = 1/2 X CEQ X (VBAT22 - VBAT12)
Refer to SLUC461 for a design example that sizes the storage element.
Note that if there are large load transients or the storage element has significant impedance then it may be
necessary to increase the CSTOR capacitor from the 4.7uF minimum or add additional capacitance to VBAT in
order to prevent a droop in the VSTOR voltage. See below for guidance on sizing capacitors.
Inductor Selection
The boost charger and the buck converter each need an appropriately sized inductor for proper operation. The
inductor's saturation current should be at least 25% higher than the expected peak inductor currents
recommended below if system load transients on VSTOR and/or VOUT are expected. Since this device uses
hysteretic control for both the boost charger and buck converter, both are considered naturally stable systems
(single order transfer function).
28
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Boost Charger Inductor Selection
For boost charger to operate properly, an inductor of appropriate value must be connected between LBOOST,
pin 20, and VIN_DC, pin 2. The boost converter internal control circuitry is designed to control the switching
behavior with a nominal inductance of 22 µH ± 20%. The inductor must have a peak current capability of > 300
mA with a low series resistance (DCR) to maintain high efficiency.
A list of inductors recommended for this device is shown in Table 2.
Table 2.
INDUCTANCE (µH)
DIMENSIONS (mm)
PART NUMBER
MANUFACTURER
22
4.0x4.0x1.7
LPS4018-223M
Coilcraft
22
3.8x3.8x1.65
744031220
Wuerth
Buck Converter Inductor Selection
For buck converter to operate properly, an inductor of appropriate value must be connected between LBUCK, pin
16, and VOUT, pin 14. The buck converter internal control circuitry is designed to control the switching behavior
with a nominal inductance of 10 µH ± 20%. The inductor must have a peak current capability of > 200 mA with a
low series resistance (DCR) to maintain high efficiency. The speed of the peak current detect circuit sets the
inductor's lower bound to 4.7 µH. When using a 4.7 uH, the peak inductor current will increase when compared
to that of a 10 µH inductor, resulting in slightly higher major frequency.
A list of inductors recommended for this device is shown in Table 3.
Table 3.
INDUCTANCE (µH)
DIMENSIONS (mm)
PART NUMBER
10
2.0 x 2.5 x 1.2
DFE252012C-H-100M
MANUFACTURER
Toko
10
4.0x4.0x1.7
LPS4018-103M
Coilcraft
10
2.8x2.8x1.35
744029100
Wuerth
10
3.0x3.0x1.5
74438335100
Wuerth
10
2.5x2.5x1.2
74479889310
Wuerth
4.7
2.0 x 2.5 x 1.2
DFE252012R-H-4R7M
Toko
Capacitor Selection
In general, all the capacitors need to be low leakage. Any leakage the capacitors have will reduce efficiency,
increase the quiescent current and diminish the effectiveness of the IC for energy harvesting.
VREF_SAMP Capacitance
The MPPT operation depends on the sampled value of the open circuit voltage and the input regulation follows
the voltage stored on the CREF capacitor. This capacitor is sensitive to leakage since the holding period is
around 16 seconds. As the capacitor voltage drops due to any leakage, the input regulation voltage also drops
preventing proper operation from extraction the maximum power from the input source. Therefore, it is
recommended that the capacitor be an X7R or COG low leakage capacitor.
VIN_DC Capacitance
Energy from the energy harvester input source is initially stored on a capacitor, CIN, connected to VIN_DC, pin
2, and VSS, pin 1. For energy harvesters which have a source impedance which is dominated by a capacitive
behavior, the value of the harvester capacitor should scaled according to the value of the output capacitance of
the energy source, but a minimum value of 4.7 µF is recommended.
VSTOR Capacitance
Operation of the bq25570 requires two capacitors to be connected between VSTOR, pin 19, and VSS, pin 1. A
high frequency bypass capacitor of at 0.01 µF should be placed as close as possible between VSTOR and VSS.
In addition, a low ESR capacitor of at least 4.7 µF should be connected in parallel.
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VOUT Capacitance
The output capacitor is chosen based on transient response behavior and ripple magnitude. The lower the
capacitor value, the larger the ripple will become and the larger the droop will be in the case of a transient
response. It is recommended to use at least a 22 µF output capacitor between VOUT, pin 14 and VSS, pin 15,
for most applications.
Additional Capacitance on VSTOR or VBAT
If there are large, fast system load transients and/or the storage element has high resistance, then the CSTOR
capacitors may momentarily discharge below the VBAT_UV threshold in response to the transient. This causes
the bq25570 to turn off the PFET switch between VSTOR and VBAT and turn on the boost converter. The
CSTOR capacitors may further discharge below the VSTOR_CHGEN threshold and cause the bq25570 to enter
Cold Start. For instance, some Li-ion batteries or thin-film batteries may not have the current capacity to meet the
surge current requirements of an attached low power radio. To prevent VSTOR from drooping, either increasing
the CSTOR capacitance or adding additional capacitance in parallel with the storage element is recommended.
For example, if boost charger is configured to charge the storage element to 4.2 V and a 500 mA load transient
of 50 µs duration infrequently occurs, then, solving I = C x dv/dt for CSTOR gives :
CSTOR ≥ 500 mA x 50 µs/(4.2 V – 1.8 V) = 10.5 µF
(6)
Note that increasing CSTOR is the recommended solution but will cause the boost charger to operate in the less
efficient cold start mode for a longer period at startup compared to using CSTOR = 4.7 µF. If longer cold start run
times are not acceptable, then place the additional capacitance in parallel with the storage element.
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LAYOUT CONSIDERATIONS
As for all switching power supplies, the PCB layout is an important step in the design, especially at high peak
currents and high switching frequencies. If the layout is not carefully done, the boost converter/charger and buck
converter could show stability problems as well as EMI problems. Therefore, use wide and short traces for the
main current path and for the power ground paths. The input and output capacitors as well as the inductors
should be placed as close as possible to the IC. For the boost converter / charger, first priority are the output
capacitors, including the 0.1uF bypass capacitor (CBYP), followed by CSTOR, which should be placed as close
as possible between VSTOR, pin 19, and VSS, pin 1. Next, the input capacitor, CIN, should be placed as close
as possible between VIN_DC, pin 2, and VSS, pin 1. Last in priority is the boost converter inductor, L1, which
should be placed close to LBOOST, pin 20, and VIN_DC, pin 2. For the buck converter, the output capacitor
COUT should be placed as close as possible between VOUT, pin 14, and VSS, pin 15. The buck converter
inductor (L2) should be placed as close as possible beween the switching node LBUCK, pin 16, and VOUT, pin
14. It is best to use vias and bottom traces for connecting the inductors to their respective pins instead of the
capacitors.
To minimize noise pickup by the high impedance voltage setting nodes (VBAT_OV, OK_PROG, OK_HYST,
VOUT_SET), the external resistors should be placed so that the traces connecting the midpoints of each divider
to their respective pins are as short as possible. When laying out the non-power ground return paths (e.g. from
resistors and CREF), it is recommended to use short traces as well, separated from the power ground traces and
connected to VSS pin 15. This avoids ground shift problems, which can occur due to superimposition of power
ground current and control ground current. The PowerPad should not be used as a power ground return path.
The remaining pins are either NC pins, that should be connected to the PowerPad as shown below, or digital
signals with minimal layout restrictions. See the EVM user's guide for an example layout (SLUUAA7).
In order to maximize efficiency at light load, the use of voltage level setting resistors > 1MΩ is recommended. In
addition, the sample and hold circuit output capacitor on VREF_SAMP must hold the voltage for 16s. During
board assembly, contaminants such as solder flux and even some board cleaning agents can leave residue that
may form parasitic resistors across the physical resistors/capacitors and/or from one end of a resistor/capacitor
to ground, especially in humid, fast airflow environments. This can result in the voltage regulation and threshold
levels changing significantly from those expected per the installed components. Therefore, it is highly
recommended that no ground planes be poured near the voltage setting resistors or the sample and hold
capacitor. In addition, the boards must be carefully cleaned, possibly rotated at least once during cleaning, and
then rinsed with de-ionized water until the ionic contamination of that water is well above 50 MOhm. If this is not
feasible, then it is recommended that the sum of the voltage setting resistors be reduced to at least 5X below the
measured ionic contamination.
THERMAL CONSIDERATIONS
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below.
• Improving the power-dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB
• Introducing airflow in the system
For more details on how to use the thermal parameters in the Thermal Table, check the Thermal Characteristics
Application Note (SZZA017) and the IC Package Thermal Metrics Application Note (SPRA953).
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REVISION HISTORY
Changes from Original (March 2013) to Revision A
•
Changed the data sheet from a Product Brief to Production data ........................................................................................ 3
Changes from Revision A (September 2013) to Revision B
•
32
Page
Page
Changed values in the THERMAL INFORMATION table ..................................................................................................... 4
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
BQ25570RGRR
ACTIVE
VQFN
RGR
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ570
BQ25570RGRT
ACTIVE
VQFN
RGR
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ570
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ25570RGRR
VQFN
RGR
20
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
BQ25570RGRT
VQFN
RGR
20
250
180.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ25570RGRR
VQFN
RGR
20
3000
367.0
367.0
35.0
BQ25570RGRT
VQFN
RGR
20
250
210.0
185.0
35.0
Pack Materials-Page 2
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