TI SN74LVC86AQPWREP

SN74LVC86A-EP
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCAS752B – DECEMBER 2003 – REVISED JULY 2007
FEATURES
•
•
•
•
•
•
•
(1)
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of –40°C
to 125°C and –55°C to 125°C
Enhanced Diminishing Manufacturing Sources
(DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
Operates From 2 V to 3.6 V
Inputs Accept Voltages to 5.5 V
•
•
•
Max tpd of 4.6 ns at 3.3 V
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) >2 V at
VCC = 3.3 V, TA = 25°C
D OR PW PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4B
4A
4Y
3B
3A
3Y
DESCRIPTION/ORDERING INFORMATION
The SN74LVC86A quadruple 2-input exclusive-OR gate is designed for 2.7-V to 3.6-V VCC operation.
The device performs the Boolean function Y = A ⊕ B or Y = AB + AB in positive logic.
A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced
in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the
output.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 125°C
–55°C to 125°C
(1)
(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
SOIC – D
Reel of 2500
SN74LVC86AQDREP
LVC86AE
TSSOP – PW
Reel of 2000
SN74LVC86AQPWREP
LVC86AE
SOIC – D
Reel of 2500
SN74LVC86AMDREP
LVC86AM
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
FUNCTION TABLE
(EACH GATE)
INPUTS
A
B
OUTPUT
Y
L
L
L
L
H
H
H
L
H
H
H
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated
SN74LVC86A-EP
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCAS752B – DECEMBER 2003 – REVISED JULY 2007
EXCLUSIVE-OR LOGIC
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
EXCLUSIVE OR
=1
These five equivalent exclusive-OR symbols are valid for an SN74LVC86A gate in positive logic; negation may be shown at any two ports.
LOGIC-IDENTITY ELEMENT
=
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
EVEN-PARITY ELEMENT
2k
ODD-PARITY ELEMENT
2k + 1
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
V
(2)
–0.5
6.5
V
–0.5
VCC + 0.5
VI
Input voltage range
VO
Output voltage range (2) (3)
IIK
Input clamp current
VI < 0 V
–50
mA
IOK
Output clamp current
VO < 0 V
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCC or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
2
UNIT
D package
86
PW package
113
–65
150
V
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
Submit Documentation Feedback
SN74LVC86A-EP
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCAS752B – DECEMBER 2003 – REVISED JULY 2007
Recommended Operating Conditions
(1)
Operating
MIN
MAX
2
3.6
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VCC = 2.7 V to 3.6 V
VIL
Low-level input voltage
VCC = 2.7 V to 3.6 V
0.8
V
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Data retention only
2
V
V
VCC = 2.7 V
–12
VCC = 3 V
–24
VCC = 2.7 V
12
VCC = 3 V
24
9
Operating free-air temperature
(1)
1.5
Q suffix
–40
125
M suffix
–55
125
mA
mA
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 μA
VOH
II
ICC
ΔICC
MAX
UNIT
VCC – 0.2
2.7 V
2.2
3V
2.4
IOH = –24 mA
3V
2.2
IOL = 100 μA
2.7 V to 3.6 V
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
3V
0.55
V
0.2
V
VI = 5.5 V or GND
3.6 V
±5
μA
VI = VCC or GND, IO = 0
3.6 V
10
μA
500
μA
One input at VCC – 0.6 V, Other inputs at VCC or GND
Ci
(1)
2.7 V to 3.6 V
IOH = –12 mA
VOL
MIN TYP (1)
VCC
2.7 V to 3.6 V
VI = VCC or GND
3.3 V
5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A
Y
tpd
VCC = 2.7 V
MIN
VCC = 3.3 V
± 0.3 V
MAX
MIN
MAX
5.6
1
4.6
UNIT
ns
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance per gate
TEST
CONDITIONS
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
f = 10 MHz
7.5
8.5
Submit Documentation Feedback
UNIT
pF
3
SN74LVC86A-EP
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCAS752B – DECEMBER 2003 – REVISED JULY 2007
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
2.7 V
2.7 V
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
1.5 V
1.5 V
6V
6V
50 pF
50 pF
500 Ω
500 Ω
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VM
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VOH
Output
VI
Output
Control
VM
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + V∆
VOL
tPHZ
VM
VOH - V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
4
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LVC86AMDREP
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC86AQDREP
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC86AQPWREP
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
V62/04670-01XE
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
V62/04670-01YE
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
V62/04670-02XE
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC86A-EP :
SN74LVC86A
• Catalog:
SN74LVC86A-Q1
• Automotive:
• Military: SN54LVC86A
NOTE: Qualified Version Definitions:
- TI's standard catalog product
• Catalog
Automotive
- Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Military - QML
certified for Military and Defense Applications
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74LVC86AMDREP
Package Package Pins
Type Drawing
SOIC
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74LVC86AQDREP
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74LVC86AQPWREP
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC86AMDREP
SOIC
D
14
2500
333.2
345.9
28.6
SN74LVC86AQDREP
SOIC
D
14
2500
333.2
345.9
28.6
SN74LVC86AQPWREP
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
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