ADC774 ® Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER FEATURES formance. It is complete with a self-contained +10V reference, internal clock, digital interface for microprocessor control, and three-state outputs. ● COMPLETE 12-BIT A/D CONVERTER WITH REFERENCE, CLOCK, AND 8-, 12-, or 16BIT MICROPROCESSOR BUS INTERFACE ● ALTERNATE SOURCE FOR HI774 A/D CONVERTER: 8.5µs Conversion Time, 150ns Bus Access Time ● FULLY SPECIFIED FOR OPERATION ON ±12V OR ±15V SUPPLIES ● NO MISSING CODES OVER TEMPERATURE: 0°C to +75°C: ADC774J, K –55°C to +125°C: ADC774SH, TH The reference circuit, containing a buried zener, is lasertrimmed for minimum temperature coefficient. The clock oscillator is current-controlled for excellent stability over temperature. Full-scale and offset errors may be externally trimmed to zero. Internal scaling resistors are provided for the selection of analog input signal ranges of 0V to +10V, 0V to +20V, ±5V, and ±10V. The converter may be externally programmed to provide 8- or 12-bit resolution. The conversion time for 12 bits is factory set for 8.5µs maximum. DESCRIPTION Output data are available in a parallel format from TTLcompatible three-state output buffers. Output data are coded in straight binary for unipolar input signals and bipolar offset binary for bipolar input signals. The ADC774 is a 12-bit successive approximation analog-to-digital converter, utilizing state-of-the-art CMOS and laser-trimmed bipolar die custom-designed for freedom from latch-up and for optimum AC per- The ADC774, available in both industrial and military temperature ranges, requires supply voltages of +5V and ±12V or ±15V. It is packaged in a 28-pin plastic DIP, or a hermetic side-brazed ceramic DIP. Control Inputs Control Logic Status Bipolar Offset 10V Range Reference Input Comparator 12-Bit D/A Converter Reference Output International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • © 1988 Burr-Brown Corporation Three-State Buffers Successive Approximation Register Clock 20V Range Parallel Data Output 10V Reference • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 PDS-835E Printed in U.S.A. March, 1992 SPECIFICATIONS ELECTRICAL TA = +25°C, VCC = +12V or +15V, VEE = –12V or –15V, VLOGIC = +5V unless otherwise specified. ADC774J, ADC774SH PARAMETER MIN TYP ADC774K, ADC774TH MAX RESOLUTION MIN TYP 12 MAX UNITS * Bits * * V V kΩ kΩ INPUTS ANALOG Voltage Ranges: Unipolar Bipolar Impedance: 0 to +10V, ±5V ±10V, 0V to +20V DIGITAL (CE, CS, R/C, AO, 12/8) Over Temperature Range Voltages: Logic 1 Logic 0 Current Capacitance 3.75 7.5 +2 –0.5 –5 0 to +10, 0 to +20 ±5, ±10 5 10 0.1 5 6.25 12.5 * * +5.5 +0.8 +5 * * * * * * * * * * V V µA pF ±1/2 * ±4 LSB LSB LSB * % of FS(2) Bits LSB ±1 ±1 ±1/2 ±3/4 LSB LSB ±0.47 ±0.75 ±0.22 ±0.5 ±0.37 ±0.5 ±0.12 ±0.25 % of FS % of FS % of FS % of FS Bits * * TRANSFER CHARACTERISTICS ACCURACY At +25°C Linearity Error Unipolar Offset Error (Adjustable to Zero) Bipolar Offset Error (Adjustable to Zero) Full-Scale Calibration Error(1) (Adjustable to Zero) No Missing Codes Resolution (Diff. Linearity) Inherent Quantization Error TMIN to TMAX Linearity Error: J, K Grades S, T Grades Full-Scale Calibration Error Without Initial Adjustment (1) : J, K Grades S, T Grades Adjusted to Zero at +25°C: J, K Grades S, T Grades No Missing Codes Resolution (Diff. Linearity) ±1 ±2 ±10 ±0.25 11 12 ±1/2 * 11 12 TEMPERATURE COEFFICIENTS (TMIN to TMAX)(3) Unipolar Offset: J, K Grades S, T Grades Max Change: All Grades Bipolar Offset: All Grades Max Change: J, K Grades S, T Grades Full-Scale Calibration: J, K Grades S, T Grades Max Change: J, K Grades S, T Grades ±10 ±5 ±2 ±10 ±2 ±4 ±45 ±50 ±9 ±20 ±5 ±2.5 ±1 ±5 ±1 ±2 ±25 ±25 ±5 ±10 ppm/°C ppm/°C LSB ppm/°C LSB LSB ppm/°C ppm/°C LSB LSB POWER SUPPLY SENSITIVITY Change in Full-Scale Calibration +13.5V < VCC <+16.5V or +11.4V < VCC < +12.6V –16.5V < VEE <–13.5V or –12.6V < VEE < –11.4V +4.5V < VLOGIC <+5.5V ±2 ±2 ±1/2 ±1 ±1 * LSB LSB LSB * • µs µs * V V µA pF CONVERSION TIME (4,5) 8-Bit Cycle 12-Bit Cycle 5 7.5 5.3 8.5 * • OUTPUTS DIGITAL (DB11 – DB0, STATUS) (Over Temperature Range) Output Codes: Unipolar Bipolar Logic Levels: Logic 0 (ISINK = 1.6mA) Logic 1 (ISOURCE = 500µA) Leakage, Data Bits Only, High-Z State Capacitance +2.4 –5 Unipolar Straight Binary (USB) Bipolar Offset Binary (BOB) +0.4 * +5 * 0.1 5 ® ADC774 2 * * * SPECIFICATIONS (CONT) ELECTRICAL TA = +25°C, VCC = +12V or +15V, VEE = –12V or –15V, VLOGIC = +5V unless otherwise specified. ADC774J, ADC774SH PARAMETER ADC774K, ADC774TH MIN TYP MAX MIN TYP MAX UNITS +9.9 2.0 +10 +10.1 * * * * V mA * * * 3.5 15 9 325 +16.5 –16.5 +5.5 5 20 15 450 * * * * * * * * * * * V V V mA mA mA mW +75 +125 +150 * * * * * * °C °C °C INTERNAL REFERENCE VOLRAGE Voltage Source Current Available for External Loads (6) POWER SUPPLY REQUIREMENTS Voltage: VCC VEE VLOGIC Current: ICC IEE ILOGIC Power Dissipation (±15V Supplies) +11.4 –11.4 +4.5 ` TEMPERATURE RANGE (Ambient: TMIN , TMAX ) Specifications: J, K Grades S, T Grades Storage 0 –55 –65 *Same specification as ADC774JH, JP, SH. NOTES: (1) With fixed 50Ω resistor from Ref Out to Ref In. This parameter is also adjustable to zero at +25C. (2) FS in this specification table means Full Scale Range. That is, for a ±10V input range FS means 20V; for a 0V to +10V range, FS means 10V. The term Full Scale for these specification instead of Full-Scale Range is used to be consistent with other vendors' specifications tables. (3) Using internal reference. (4) See “Controlling the ADC774” section for detailed information concerning digital timing. (5) The Harris HI-774 uses a subranging/error correction technique that allows one to begin conversion before a preceding sample-hold or multiplexer has settled to ±1/2LSB. For 12-bit accurate conversions, the input transient to the ADC774 must settle to less than ±1/2LSB before conversion is started. The ADC774 is compatible with HI-774 in all other respects. (6) External loading must be constant during conversion. The reference output requires no buffer amplifier with either ±12V or ±15V power supplies. PIN CONFIGURATION Top View DIP AO 4 R/C 5 CE 6 +V CC 7 Ref Out 8 Analog Common 9 Ref In 10 Control Logic Clock 10V Reference 12-Bit D/A Converter 12 Bits Comparator V EE 11 Bipolar Offset 12 10V Range 13 20V Range 14 10kΩ 5Ω 5Ω 12 Bits Nibble A CS 3 Nibble B 2 Nibble C 12/8 Power-up Reset Three-State Buffers and Control 1 Successive Approximation Register +5VDC Supply (VLOGIC ) 28 STATUS 27 DB11 (MSB) 26 DB10 25 DB9 24 DB8 23 DB7 22 DB6 21 DB5 20 DB4 19 DB3 18 DB2 17 DB1 16 DB0 (LSB) 15 Digital Common The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 ADC774 ABSOLUTE MAXIMUM RATINGS BURN-IN SCREENING Burn-in screening is available for both plastic and ceramic package ADC774s. Burn-in duration is 160 hours at the temperature (or equivalent combination of time and temperature) indicated below: Plastic “-BI” models: +85°C Ceramic “-BI” models: +125°C All units are 100% electrically tested after burn-in is completed. To order burn-in, add “-BI” to the base model number (e.g. ADC774KP-BI). See Ordering Information for pricing. VCC to Digital Common ......................................................... 0V to +16.5V VEE to Digital Common .......................................................... 0V to –16.5V VLOGIC Digital Common .............................................................. 0V to +7V Analog Common to Digital Common .................................................... ±1V Control Inputs (CE, CS, AO, 12/8, R/C) to Digital Common .............................................. –0.5V to VLOGIC +0.5V Analog Inputs (Ref In, Bipolar Offset, 10VIN ) to Analog Common ...................................................................... ±16.5V 20VIN to Analog Common .................................................................. ±24V Ref Out .......................................................... Indefinite Short to Common, Momentary Short to VCC Max Junction Temperature ............................................................ +165°C Power Dissipation ........................................................................ 1000mW Lead Temperature (soldering,10s) ................................................. +300°C Thermal Resistance, θJA : Ceramic ................................................ 50°C/W Plastic ................................................. 100°C/W CAUTION: These devices are sensitive to electrostatic discharge. Appropriate I.C. handling procedures should be followed. PACKAGE INFORMATION MODEL ADC774JP ADC774KP ADC774JH ADC774KH ADC774SH ADC774TH ADC774JP-BI ADC774KP-BI ADC774JH-BI ADC774KH-BI ADC774SH-BI ADC774TH-BI PACKAGE PACKAGE DRAWING NUMBER(1) 28-Pin Plastic DIP 28-Pin Plastic DIP 28-Pin Ceramic DIP 28-Pin Ceramic DIP 28-Pin Ceramic DIP 28-Pin Ceramic DIP 28-Pin Plastic DIP 28-Pin Plastic DIP 28-Pin Ceramic DIP 28-Pin Ceramic DIP 28-Pin Ceramic DIP 28-Pin Ceramic DIP 215 215 149 149 149 149 215 215 149 149 149 149 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ORDERING INFORMATION MODEL ADC774JP ADC774KP ADC774JH ADC774KH ADC774SH ADC774TH PACKAGE TEMPERATURE RANGE LINEARITY ERROR MAX (TMINTO TMAX) Plastic DIP Plastic DIP Ceramic DIP Ceramic DIP Ceramic DIP Ceramic DIP 0°C TO +75°C 0°C to +75°C 0°C to +75°C 0°C to +75°C –55°C to +125°C –55°C to +125°C ±1LSB ±1/2LSB ±1LSB ±1/2LSB ±1LSB ±3/4LSB PACKAGE TEMPERATURE RANGE BURN-IN TEMP (160 HOURS)(1) Plastic DIP Plastic DIP Ceramic DIP Ceramic DIP Ceramic DIP Ceramic DIP 0°C to +75°C 0°C to +75°C 0°C to +75°C 0°C to +75°C –55°C to +125°C –55°C to +125°C +85°C +85°C +125°C +125°C +125°C +125°C BURN-IN SCREENING OPTION See text for details. MODEL ADC774JP-BI ADC774KP-BI ADC774JH-BI ADC774KH-BI ADC774SH-BI ADC774TH-BI ® ADC774 4 CONTROLLING THE ADC774 Conversion is initiated by a high-to-low transition of R/C. The three-state data output buffers are enabled when R/C is high and STATUS is low. Thus, there are two possible modes of operation; conversion can be initiated with either positive or negative pulses. In either case the R/C pulse must remain low for a minimum of 50ns. This is an abridged data sheet. For Discussion of Specifications, Installation, Calibration refer to ADC574A data sheet or order PDS-835. The Burr-Brown ADC774 can be easily interfaced to most microprocessor systems and other digital systems. The microprocessor may take full control of each conversion, or the converter may operate in a stand-alone mode, controlled only by the R/C input. Full control consists of selecting an 8- or 12-bit conversion cycle, initiating the conversion, and reading the output data when ready—choosing either 12 bits all at once, or 8 bits followed by 4 bits in a left-justified format. The five control inputs (12/8, CS, AO, R/C, and CE) are all TTL-/CMOS-compatible. The functions of the control inputs are described in Table I. The control function truth table is listed in Table II. tHRL R/C tDS STS tC tHDR DB11–DB0 Data Valid tHS High-Z State Data Valid FIGURE 1. R/C Pulse Low—Outputs Enabled After Conversion. Read footnote 5 to the Electrical Specifications table if using ADC774 to replace the HI-774. STAND-ALONE OPERATION For stand-alone operation, control of the converter is accomplished by a single control line connected to R/C. In this mode CS and AO are connected to digital common and CE and 12/8 are connected to VLOGIC (+5V). The output data are presented as 12-bit words. The stand-alone mode is used in systems containing dedicated input ports which do not require full bus interface capability. R/C tHRH tDS STS tDDR DB11– High-Z DB0 tC tHDR High-Z State Data Valid FIGURE 2. R/C Pulse High—Outputs Enabled Only While R/C Is High. PIN DESIGNATION DEFINITION FUNCTION CE (Pin 6) Chip Enable (active high) Must be high (“1”) to either initiate a conversion or read output data. 0-1 edge may be used to initiate a conversion. CS (Pin 3) Chip Select (active low) Must be low (“0”) to either initiate a conversion or read output data. 1-0 edge may be used to initiate a conversion. R/C (Pin 5) Read/Convert (“1” = read) (“0” = convert) Must be low (“0”) to initiate either 8- or 12-bit conversions. 1-0 edge may be used to initiate a conversion. Must be high (“1”) to read output data. 0-1 edge may be used to initiate a read operation. AO (Pin 4) Byte Address Short Cycle In the start-convert mode, AO selects 8-bit (AO = “1”) or 12-bit (AO = “0”) conversion mode. When reading output data in two 8-bit bytes, AO = “0” accesses 8 MSBs (high byte) and AO = “1” accesses 4 LSBs and trailing “0s” (low byte). 12/8 (Pin 2) Data Mode Select (“1” = 12 bits) (“0” = 8 bits) When reading output data, 12/8 = “1” enables all 12 output bits simultaneously. 12/8 = “0” will enable the MSBs or LSBs as determined by the AO line. TABLE I. ADC774 Control Line Functions. CE 0 X 1 1 1 1 1 1 1 CS R/C 12/8 AO OPERATION X 1 0 0 X X 0 0 0 0 X X X X X X X X 1 0 0 X X 0 1 0 1 0 1 X 0 1 None None Initiate 12-bit conversion Initiate 8-bit conversion Initiate 12-bit conversion Initiate 8-bit conversion Initiate 12-bit conversion Initiate 8-bit conversion Enable 12-bit output Enable 8 MSBs only Enable 4 LSBs plus 4 trailing zeros 0 0 0 0 0 1 1 1 SYMBOL PARAMETER tHRL tDS tHDR tHS tHRH tDDR Low R/C Pulse Width STS Delay from R/C Data Valid After R/C Low STS Delay After Data Valid High R/C Pulse Width Data Access Time MIN TYP MAX 50 200 25 150 375 150 150 UNITS ns ns ns ns ns ns TABLE III. Stand-Alone Mode Timing. TABLE II. Control Input Truth Table. ® 5 ADC774 FULLY CONTROLLED OPERATION Conversion Length Conversion length (8-bit or 12-bit) is determined by the state of the AO input, which is latched upon receipt of a conversion start transition (described below). If AO is latched high, the conversion continues for 8 bits. The full 12-bit conversion will occur if AO is low. If all 12 bits are read following an 8-bit conversion, the 3 LSBs (DB0–DB2) will be low (logic 0) and DB3 will be high (logic 1). AO is latched because it is also involved in enabling the output buffers. No other control inputs are latched. Figure 1 illustrates timing when conversion is initiated by an R/C pulse which goes low and returns to the high state during the conversion. In this case, the three-state outputs go to the high-impedance state in response to the falling edge of R/C and are enabled for external access of the data after completion of the conversion. Figure 2 illustrates the timing when conversion is initiated by a positive R/C pulse. In this mode the output data from the previous conversion is enabled during the positive portion of R/C. A new conversion is started on the falling edge of R/C, and the three-state outputs return to the high-impedance state until the next occurrence of a high R/C pulse. Timing specifications for stand-alone operation are listed in Table III. CE CE tHEC tSSR tSSC tHSR CS CS tSRC tHSC tHRR R/C R/C tSRR tHRC AO AO tHAR tSAR tSAC tHAC STS STS tDSC tHS tC High-Z DB11– DB0 High Impedance DB11– DB0 Data Valid tDD FIGURE 3. Conversion Cycle Timing. SYMBOL MIN STS Delay from CE CE Pulse Width CS to CE Setup time CS low during CE high R/C to CE setup R/C low during CE high AO to CE setup AO valid during CE high Conversion time 12-bit cycle at 25°C 0 to +75°C –55°C to +125°C 8-bit cycle at 25°C 0 to +75°C –55° to +125°C Read Mode tDD tHD tHL tSSR tSAR tHSR tHRR tHAR tHS 50 50 50 50 50 0 50 TYP MAX UNITS 60 30 20 20 0 20 200 ns ns ns ns ns ns ns ns 8.5 9.0 9.5 5.3 5.6 6 µs µs µs µs µs µs 75 35 100 0 150 150 375 ns ns ns ns ns ns ns ns ns 20 7.5 5 Access time from CE Data valid after CE low Output float delay CS to CE setup R/C to CE setup CS valid after CE low R/C high after CE low AO valid after CE low STS delay after data valid 25 50 0 0 0 50 TABLE IV. Timing Specifications. ® ADC774 tHL FIGURE 4. Read Cycle Timing. PARAMETER tDSC tHEC tSSC tHSC tSRC tHRC tSAC tHAC tC tHD 6 150 CONVERSION START The converter is commanded to initiate a conversion by a transition occurring on any of three logic inputs (CE, CS, and R/C) as shown in Table II. Conversion is initiated by the last of the three to reach the required state and thus all three may be dynamically controlled. If necessary, all three may change state simultaneously, and the nominal delay time is the same regardless of which input actually starts conversion. If it is desired that a particular input establish the actual start of conversion, the other two should be stable a minimum of 50ns prior to the transition of that input. Timing relationships for start of conversion timing are illustrated in Figure 3. The specifications for timing are contained in Table IV. of the three digital inputs which control conversion will be ignored, so that conversion cannot be prematurely terminated or restarted. However, if AO changes state after the beginning of conversion, any additional start conversion transition will latch the new state of AO, possibly resulting in an incorrect conversion length (8 bits vs 12 bits) for that conversion. READING OUTPUT DATA After conversion is initiated, the output data buffers remain in a high-impedance state until the following four logic conditions are simultaneously met: R/C high, STATUS low, CE high, and CS low. Upon satisfaction of these conditions the data lines are enabled according to the state of inputs 12/8 and AO. See Figure 4 and Table IV for timing relation- The STATUS output indicates the current state of the converter by being in a high state only during conversion. During this time the three-state output buffers remain in a high-impedance state, and therefore data cannot be read during conversion. During this period additional transitions ® 7 ADC774 This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.