TPS28225-Q1 TPS28226-Q1 www.ti.com SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 High-Frequency 4-A Sink Synchronous MOSFET Drivers Check for Samples: TPS28225-Q1, TPS28226-Q1 FEATURES APPLICATIONS • • • 1 • • • • • • • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature Range – Device HBM ESD Classification Level H2 – Device CDM ESD Classification Level C3B Drives Two N-Channel MOSFETs with 14-ns Adaptive Dead Time Wide Gate Drive Voltage: 4.5 V Up to 8.8 V With Best Efficiency at 7 V to 8 V Wide Power System Train Input Voltage: 3 V Up to 27 V Wide Input PWM Signals: 2.0 V up to 13.2-V Amplitude Capable Drive MOSFETs with ≥40-A Current per Phase High Frequency Operation: 14-ns Propagation Delay and 10-ns Rise/Fall Time Allow FSW - 2 MHz Capable Propagate <30-ns Input PWM Pulses Low-Side Driver Sink On-Resistance (0.4 Ω) Prevents dV/dT Related Shoot-Through Current 3-State PWM Input for Power Stage Shutdown Space Saving Enable (input) and Power Good (output) Signals on Same Pin Thermal Shutdown UVLO Protection Internal Bootstrap Diode Economical SOIC-8 and Thermally Enhanced 3-mm x 3-mm DFN-8 Packages High Performance Replacement for Popular 3State Input Drivers • • • Multi-Phase DC-to-DC Converters with Analog or Digital Control Desktop and Server VRMs and EVRDs Portable/Notebook Regulators Synchronous Rectification for Isolated Power Supplies DESCRIPTION The TPS28225-Q1 and TPS28226-Q1 are highspeed drivers for N-channel complimentary driven power MOSFETs with adaptive dead-time control. These drivers are optimized for use in variety of highcurrent one and multi-phase dc-to-dc converters. The TPS28225-Q1 is a solution that provides highly efficient, small size low EMI emissions. The performance is achieved by up to 8.8-V gate drive voltage, 14-ns adaptive dead-time control, 14-ns propagation delays and high-current 2-A source and 4-A sink drive capability. The 0.4-Ω impedance for the lower gate driver holds the gate of power MOSFET below its threshold and ensures no shootthrough current at high dV/dt phase node transitions. The bootstrap capacitor charged by an internal diode allows use of N-channel MOSFETs in half-bridge configuration. The TPS28225-Q1 features a 3-state PWM input compatible with all multi-phase controllers employing 3-state output feature. As long as the input stays within 3-state window for the 250-ns hold-off time, the driver switches both outputs low. This shutdown mode prevents a load from the reversed- outputvoltage. The other features include under voltage lockout, thermal shutdown and two-way enable/power good signal. Systems without 3-state featured controllers can use enable/power good input/output to hold both outputs low during shutting down. The TPS28225-Q1 is offered in an economical SOIC8 and thermally enhanced low-size Dual Flat No-Lead (DFN-8) packages. The driver is specified in the extended temperature range of –40°C to 105°C with the absolute maximum junction temperature 150°C. The TPS28226-Q1 operates in the same manner as the TPS28225-Q1 other than the input under voltage lock out. Unless otherwise stated all references to the TPS28225-Q1 apply to the TPS28226-Q1 also. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2012, Texas Instruments Incorporated TPS28225-Q1 TPS28226-Q1 SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM VDD 6 2 BOOT 1 UGATE 8 PHASE 5 LGATE 4 GND UVLO EN/PG 7 THERMAL SD SHOOTTHROUGH PROTECTION VDD HLD-OFF TIME 27K 3-STATE INPUT CIRCUIT PWM 3 13K TYPICAL APPLICATIONS Figure 1. One-Phase POL Regulator VDD (4.5 V to 8 V) VIN (3 V to 32 V − V DD) 6 VDD BOOT 2 TPS28225 UGATE 1 TPS40200 3 PWM PHASE 8 VCC 3 VOUT OUT 3 7 ENBL FB 3 GND 3 2 LGATE 5 GND 4 Copyright © 2011–2012, Texas Instruments Incorporated TPS28225-Q1 TPS28226-Q1 www.ti.com SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 TYPICAL APPLICATIONS (continued) Figure 2. Driver for Synchronous Rectification with Complementary Driven MOSFETs 12 V 35 V to 75V VOUT = 3.3 V Primary High Side VDD High Voltage Driver HB PWM CONTROLLER LI DRIVE HI C O N TR OL HI HO LINEAR REG. HS DRIVE LO LO TPS28255 BOOT 2 6 VDD VSS ISOLATION AND FEEDBACK VDD (4.5 V to 8 V) UGATE 1 7 EN/PG PHASE 8 3 PWM LGATE 5 GND 4 Copyright © 2011–2012, Texas Instruments Incorporated 3 TPS28225-Q1 TPS28226-Q1 SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 www.ti.com TYPICAL APPLICATIONS (continued) Figure 3. Multi-Phase Synchronous Buck Converter VDD (4.5 V to 8 V) VIN (3 V to 32 V − VDD) 6 VDD BOOT 2 TPS28225 3 PWM UGATE 1 PHASE 8 LGATE 5 GND 4 BOOT 2 7 EN/PG PWM1 2 CS 1 To Controller To Driver TPS4009x or any other analog or digital controller PWM2 1 VIN 8 To Driver PWM3 8 6 VDD PWM 4 5 GND GNDS VOUT 7 3 To Controller TPS28225 UGATE 1 PHASE 8 CS 4 CSCN 4 3 PWM VOUT 7 EN/PG Enable LGATE 5 GND 4 ORDERING INFORMATION TA PACKAGE SOIC (D) Reel of 2500 -40°C to 105°C DFN (DRB) (1) (2) 4 Reel of 3000 (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING TPS28225TDRQ1 PREVIEW TPS28226TDRQ1 PREVIEW TPS28225TDRBRQ1 PXND TPS28226TDRBRQ1 PREVIEW The SOIC-8 (D) and DFN-8 (DRB) package uses in Pb-Free lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to 260°C peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations. In the DFN package, the pad underneath the center of the device is a thermal substrate. The PCB “thermal land” design for this exposed die pad should include thermal vias that drop down and connect to one or more buried copper plane(s). This combination of vias for vertical heat escape and buried planes for heat spreading allows the DFN to achieve its full thermal potential. This pad should be either grounded for best noise immunity, and it should not be connected to other nodes. Copyright © 2011–2012, Texas Instruments Incorporated TPS28225-Q1 TPS28226-Q1 www.ti.com SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) VALUE Input supply voltage range, VDD UNIT (3) Boot voltage, VBOOT Phase voltage, VPHASE DC –0.3 to 8.8 V –0.3 to 33 V –2 to 32 or VBOOT + 0.3 – VDD whichever is less Pulse < 400 ns, E = 20 μJ Input voltage range, VPWM, VEN/PG –0.3 to 13.2 V VPHASE – 0.3 to VBOOT + 0.3, (VBOOT – VPHASE < 8.8) Output voltage range, VUGATE Pulse < 100 ns, E = 2 μJ Output voltage range, VLGATE Pulse < 100 ns, E = 2 μJ V VPHASE – 2 to VBOOT + 0.3, (VBOOT – VPHASE < 8.8) –0.3 to VDD + 0.3 V –2 to VDD + 0.3 (HBM) AEC-Q100 Classification Level H2 ESD rating V –7 to 33.1 or VBOOT + 0.3 – VDD whichever is less 2 (CDM) AEC-Q100 Classification Level C3B kV 750 V Operating virtual junction temperature range, TJ –40 to 150 °C Operating ambient temperature range, TA –40 to 105 °C Storage temperature, Tstg –65 to 150 °C 300 °C Lead temperature (soldering, 10 sec.) (1) (2) (3) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. These devices are sensitive to electrostatic discharge; follow proper device handling procedures. All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Data book for thermal limitations and considerations of packages. THERMAL INFORMATION THERMAL METRIC (1) TPS28225TDRBRQ1 θJA Junction-to-ambient thermal resistance 50.2 θJCtop Junction-to-case (top) thermal resistance 57.5 θJB Junction-to-board thermal resistance 25.9 ψJT Junction-to-top characterization parameter 1.5 ψJB Junction-to-board characterization parameter 26.0 θJCbot Junction-to-case (bottom) thermal resistance 9.5 (1) UNITS DRB (8 PINS) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VDD MIN TYP MAX Input supply voltage (TPS28225-Q1) 4.5 7.2 8 Input supply voltage (TPS28226-Q1) 6.8 7.2 VIN Power input voltage for the TPS28225-Q1 TJ Operating junction temperature range Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 8 3 32 V–VDD –40 125 Submit Documentation Feedback UNIT V °C 5 TPS28225-Q1 TPS28226-Q1 SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (1) VDD = 7.2 V, EN/PG pulled up to VDD by 100-kΩ resistor, TA = –40°C to 105°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT UNDER VOLTAGE LOCKOUT Rising threshold (TPS28225-Q1) 3.2 Rising threshold (TPS28226-Q1) VPWM = 0 V Falling threshold (TPS28225-Q1) Falling threshold (TPS28226-Q1) 3.5 3.8 6.35 6.70 2.7 3.0 4.7 5.0 1.00 1.35 Hysteresis (TPS28225-Q1) V 0.5 Hysteresis (TPS28226-Q1) BIAS CURRENTS IDD(off) Bias supply current VEN/PG = low, PWM pin floating 350 IDD Bias supply current VEN/PG = high, PWM pin floating 500 μA INPUT (PWM) IPWM Input current VPWM = 5 V 185 VPWM = 0 V –200 PWM 3-state rising threshold (2) μA 1.0 PWM 3-state falling threshold VPWM PEAK = 5 V tHLD_R 3-state shutdown Hold-off time TMIN PWM minimum pulse to force UGATE pulse 3.4 3.8 4.0 250 CL = 3 nF at UGATE , VPWM = 5 V V ns 30 ENABLE/POWER GOOD (EN/PG) Enable high rising threshold PG FET OFF Enable low falling threshold PG FET OFF 1.7 Hysteresis Power good output 0.8 1.0 0.35 0.70 VDD = 2.5 V 2.1 V 0.2 UPPER GATE DRIVER OUTPUT (UGATE) Source resistance Source current tRU (2) Rise time Sink resistance Sink current tFU (1) (2) 6 (2) Fall time 2.0 Ω 500 mA source current 1.0 VUGATE-PHASE = 2.5 V 2.0 A CL = 3 nF 10 ns 500 mA sink current 1.0 VUGATE-PHASE = 2.5 V 2.0 A CL = 3 nF 10 ns 2.0 Ω Typical values for TA = 25°C Not tested in production Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 TPS28225-Q1 TPS28226-Q1 www.ti.com SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 ELECTRICAL CHARACTERISTICS(1) (continued) VDD = 7.2 V, EN/PG pulled up to VDD by 100-kΩ resistor, TA = –40°C to 105°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOWER GATE DRIVER OUTPUT (LGATE) tRL 2.0 Ω Source resistance 500 mA source current 1.0 Source current (3) VLGATE = 2.5 V 2.0 A Rise time (3) CL = 3 nF 10 ns Sink resistance 500 mA sink current 0.4 Sink current (3) VLGATE = 2.5 V 4.0 A Fall time (3) CL = 3 nF 5 ns 1.0 Ω SWITCHING TIME tDLU UGATE turn-off propagation Delay CL = 3 nF 14 tDLL LGATE turn-off propagation Delay CL = 3 nF 14 tDTU Dead time LGATE turn-off to UGATE turn-on CL = 3 nF 14 tDTL Dead time UGATE turn-off to LGATE turn-on CL = 3 nF 14 Forward bias current 100 mA 1.0 ns BOOTSTRAP DIODE VF Forward voltage V THERMAL SHUTDOWN Rising threshold (3) 150 160 170 Falling threshold (3) 130 140 150 Hysteresis (3) °C 20 Not tested in production Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 Submit Documentation Feedback 7 TPS28225-Q1 TPS28226-Q1 SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 www.ti.com DEVICE INFORMATION SOIC-8 Package (top view) UGATE 1 8 PHASE BOOT 2 7 EN/PG PWM 3 6 VDD GND 4 5 LGATE DRB-8 Package (top view) U G ATE 1 BOOT 2 PWM 3 GND 4 Exposed Thermal Die Pad 8 PHASE 7 EN/PG 6 VDD 5 LG A T E BLOCK DIAGRAM VDD 6 2 BOOT 1 UGATE 8 PHASE 5 LGATE 4 GND UVLO EN/PG 7 THERMAL SD HLD-OFF TIME 27K SHOOTTHROUGH PROTECTION VDD 3-STATE INPUT CIRCUIT PWM 3 13K A. 8 For the TPS28225-Q1DRB device the thermal PAD on the bottom side of package must be soldered and connected to the GND pin and to the GND plane of the PCB in the shortest possible way. See Recommended Land Pattern in the Application section. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 TPS28225-Q1 TPS28226-Q1 www.ti.com SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION SOIC-8 DRB-8 NAME 1 1 UGATE O Upper gate drive sink/source output. Connect to gate of high-side power N-Channel MOSFET. 2 2 BOOT I/O Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. 3 3 PWM I 4 The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see the 3-state PWM Input section under DETAILED DESCRIPTION for further details. Connect this pin to the PWM output of the controller. 4 GND — Ground pin. All signals are referenced to this node. Exposed die pad Thermal pad — Connect directly to the GND for better thermal performance and EMI 5 5 LGATE O Lower gate drive sink/source output. Connect to the gate of the low-side power N-Channel MOSFET. 6 6 VDD I Connect this pin to a 5-V bias supply. Place a high quality bypass capacitor from this pin to GND. 7 7 EN/PG I/O Enable/Power Good input/output pin with 1MΩ impedance. Connect this pin to HIGH to enable and LOW to disable the device. When disabled, the device draws less than 350μA bias current. If the VDD is below UVLO threshold or over temperature shutdown occurs, this pin is internally pulled low. 8 8 PHASE I Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin provides a return path for the upper gate driver. TRUTH TABLE VDD FALLING > 3 V AND TJ < 150°C PIN VDD RISING < 3.5 V OR TJ > 160°C EN/PG FALLING > 1.0 V EN/PG RISING < 1.7 V PWM < 1 V PWM > 1.5 V AND TRISE/TFALL < 200 ns PWM SIGNAL SOURCE IMPEDANCE >40 kΩ FOR > 250ns (3-State) (1) LGATE Low Low High Low Low UGATE Low Low Low High Low EN/PG Low (1) To exit the 3-state condition, the PWM signal should go low. One Low PWM input signal followed by one High PWM input signal is required before re-entering the 3-state condition. Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 Submit Documentation Feedback 9 TPS28225-Q1 TPS28226-Q1 SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 www.ti.com TPS28225-Q1 TIMING DIAGRAM Enter into 3-State at PWM rise Normal switching Exit 3-State Enter into 3-State at PWM fall 90% PWM tPWM_MIN tRU 10% 10% LGATE tDLL tHLD_F tHLD_R 90% 90% t DLU UGATE 90% 3-State window 50% 50% tFU tDTU 90% 10% tRL 10% UGATE exits 3-State after PWM goes Low and then High 90% 90% tDTL 10% tFL TPS28226-Q1 TIMING DIAGRAM Enter into 3-State at PWM rise Normal switching Exit 3-State Enter into 3-State at PWM fall 90% PWM 50% 50% tPWM_MIN tRU 10% 90% t DLU UGATE 10% 90% LGATE tDLL 3-State window tDTU 10% tFL tHLD_F tHLD_R 90% tFU 90% 10% tRL 90% tDTL 90% 10% LGATE exits 3-State after PWM goes High and then Low 10 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 TPS28225-Q1 TPS28226-Q1 www.ti.com SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 TYPICAL CHARACTERISTICS BIAS SUPPLY CURRENT vs TEMPERATURE (VEN/PG = Low, PWM Input Floating, VDD = 7.2V) UNDER VOLTAGE LOCKOUT THRESHOLD vs TEMPERATURE 500 480 IDD(off) − Bias Supply − µA 460 440 420 400 380 360 340 320 300 −40 125 25 TJ − Temperature − °C Figure 4. Figure 5. ENABLE/POWER GOOD THRESHOLD vs TEMPERATURE (VDD = 7.2 V) PWM 3-STATE THRESHOLDS, (5-V Input Pulses) vs TEMPERATURE, (VDD = 7.2 V) 2.00 5.0 PWM − PWM 3−State Threshold − V EN/PG − Enable/Power Good − V 4.5 Rising 1.75 1.50 1.25 1.00 Falling 0.75 0.50 0.25 2.5 3.0 2.5 2.0 1.5 Rising 1.0 0.5 0.00 −40 Falling 4.0 0.0 25 125 −40 TJ − Temperature − °C Figure 6. 25 125 TJ − Temperature − °C Figure 7. Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 Submit Documentation Feedback 11 TPS28225-Q1 TPS28226-Q1 SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) LGATE DC OUTPUT IMPEDANCE vs TEMPERATURE (VDD = 7.2 V) 2.00 2.00 1.75 1.75 ROUT − Output Impedance − Ω ROUT − Output Impedance − Ω UGATE DC OUTPUT IMPEDANCE vs TEMPERATURE, (VDD = 7.2 V) 1.50 RSOURCE 1.25 1.00 0.75 RSINK 0.50 1.50 1.25 1.00 RSOURCE 0.75 0.50 RSINK 0.25 0.25 0 0 −40 25 −40 125 25 TJ − Temperature − °C Figure 8. Figure 9. UGATE RISE AND FALL TIME vs TEMPERATURE (VDD = 7.2 V, CLOAD = 3 nF) LGATE RISE AND FALL TIME vs TEMPERATURE (VDD = 7.2 V, CLOAD = 3 nF) 15 14 14 13 tRL/tFL − Rise and Fall Time − ns tRU/tFU − Rise and Fall Time − ns TJ − Temperature − °C Rising 13 12 11 10 9 Falling 8 Rising 12 11 10 9 8 Falling 7 6 7 5 4 6 −40 25 125 −40 25 Figure 10. Submit Documentation Feedback 125 TJ − Temperature − °C TJ − Temperature − °C 12 125 Figure 11. Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 TPS28225-Q1 TPS28226-Q1 www.ti.com SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 TYPICAL CHARACTERISTICS (continued) UGATE AND LGATE (Turning OFF Propagation Delays) vs TEMPERTURE (VDD = 7.2 V, CLOAD = 3 nF) UGATE AND LGATE (Dead Time) vs TEMPERTURE (VDD = 7.2 V, CLOAD = 3 nF) 30 20.0 UGATE UGATE tDTU/tDTL − UGATE and LGATE − ns tDLU/tDLL − UGATE and LGATE − ns 17.5 25 20 15 LGATE 10 5 15.0 12.5 10.0 7.5 LGATE 5.0 2.5 0 0.0 −40 25 125 −40 25 125 TJ − Temperature − °C TJ − Temperature − °C Figure 12. Figure 13. UGATE MINIMUM SHORT PULSE vs TEMPERATURE (VDD = 7.2 V, CLOAD = 3 nF) BOOTSTRAP DIODE FORWARD VOLTAGE vs TEMPERATURE (VDD = 7.2 V, IF = 100 mA) 30 1.3 1.2 VF − Forward Voltage − V TMIN − Minimum Short Pulse − ns 25 20 15 10 1.1 1.0 0.9 0.8 0.7 5 0.6 0 0.5 −40 25 125 −40 TJ − Temperature − °C Figure 14. 25 125 TJ − Temperature − °C Figure 15. Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 Submit Documentation Feedback 13 TPS28225-Q1 TPS28226-Q1 SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) BIAS SUPPLY CURRENT vs SWITCHING FREQUENCY (VDD = 7.2 V, No Load, TJ = 25°C) DRIVER DISSIPATED POWER vs SWITCHING FREQUENCY (Different Load Charge, VDD = 7.2 V, TJ = 25°C) 15 1200 PDISS − Dissipated Power − mW IDD − Bias Supply Current − mA UG = 50 nC LG = 50 nC 10 5 1000 UG = 25 nC LG = 100 nC 800 UG = 25 nC LG = 50 nC 600 400 200 0 0 100 300 500 700 900 1100 1300 1500 1700 1900 100 300 500 700 900 1100 1300 1500 1700 1900 FSW − Switching Frequency − kHz FSW − Switching Frequency − kHz Figure 16. Figure 17. PWM INPUT RISING SWITCHING WAVEFORMS PWM INPUT FALLING SWITCHING WAVEFORMS VDD = 7.2 V, CL = 3 nF, TJ = 25°C Voltage − 5 V/div. Voltage − 5 V/div. PWM LGATE UGATE 14 VDD = 7.2 V, CL = 3 nF, TJ = 25°C PWM LGATE UGATE t − Time − 10 ns/div. t − Time − 10 ns/div. Figure 18. Figure 19. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 TPS28225-Q1 TPS28226-Q1 www.ti.com SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 TYPICAL CHARACTERISTICS (continued) NORMAL AND 3-STATE OPERATION ENTER/EXIT CONDITIONS MINIMUM UGATE PULSE SWITCHING WAVEFORMS VDD = 7.2 V, CL = 3 nF, TJ = 25°C PWM − 2 V/div. Voltage Voltage − 5 V/div. PWM 30ns LGATE 3−St Trigger, High = 3−St UGATE − 10 V/div. UGATE LGATE − 10 V/div. t − Time − 20 ns/div. t − Time − 5 µs/div. Figure 20. Figure 21. Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 Submit Documentation Feedback 15 TPS28225-Q1 TPS28226-Q1 SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 www.ti.com DETAILED DESCRIPTION Under Voltage Lockout (UVLO) The TPS2822x-Q1 incorporates an under voltage lockout circuit that keeps the driver disabled and external power FETs in an OFF state when the input supply voltage VDD is insufficient to drive external power FETs reliably. During power up, both gate drive outputs remain low until voltage VDD reaches UVLO threshold, typically 3.5 V for the TPS2822x-Q1 and and 6.35 V for the TPS28226-Q1. Once the UVLO threshold is reached, the condition of gate drive outputs is defined by the input PWM and EN/PG signals. During power down the UVLO threshold is set lower, typically 3.0 V for the TPS2822x-Q1 and 5.0 V for the TPS28226-Q1. The 0.5-V for the TPS2822x-Q1 and 1.35 V for the TPS28226-Q1 hysteresis is selected to prevent the driver from turning ON and OFF while the input voltage crosses UVLO thresholds, especially with low slew rate. The TPS2822x-Q1 has the ability to send a signal back to the system controller that the input supply voltage VDD is insufficient by internally pulling down the EN/PG pin. The TPS2822x-Q1 releases EN/PG pin immediately after the VDD has risen above the UVLO threshold. Output Active Low The output active low circuit effectively keeps the gate outputs low even if the driver is not powered up. This prevents open gate conditions on the external power FETs and accidental turn ON when the main power stage supply voltage is applied before the driver is powered up. For the simplicity, the output active low circuit is shown in a block diagram as the resistor connected between LGATE and GND pins with another one connected between UGATE and PHASE pins. 16 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 TPS28225-Q1 TPS28226-Q1 www.ti.com SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 Enable/Power Good The Enable/Power Good circuit allows the TPS2822x-Q1 to follow the PWM input signal when the voltage at EN/PG pin is above 2.1 V maximum. This circuit has a unique two-way communication capability. This is illustrated by Figure 22. VDD = 4.5 V to 8 V for the TPS28225 or 6.8 V to 8.0 V for the TPS28226 VCC Driver TPS28225 6 System . 20 kΩ Controller 1 kΩ EN/PG 2 V Rise 1 V Fall 7 RDS(on) = 1 kΩ UVLO 1M Thermal SD Figure 22. Enable/Power Good Circuit The EN/PG pin has approximately 1-kΩ internal series resistor. Pulling EN/PG high by an external ≥ 20-kΩ resistor allows two-way communication between controller and driver. If the input voltage VDD is below UVLO threshold or thermal shut down occurs, the internal MOSFET pulls EN/PG pin to GND through 1-kΩ resistor. The voltage across the EN/PG pin is now defined by the resistor divider comprised by the external pull up resistor, 1kΩ internal resistor and the internal FET having 1-kΩ RDS(on). Even if the system controller allows the driver to start by setting its own enable output transistor OFF, the driver keeps the voltage at EN/PG low. Low EN/PG signal indicates that the driver is not ready yet because the supply voltage VDD is low or that the driver is in thermal shutdown mode. The system controller can arrange the delay of PWM input signals coming to the driver until the driver releases EN/PG pin. If the input voltage VDD is back to normal, or the driver is cooled down below its lower thermal shutdown threshold, then the internal MOSFET releases the EN/PG pin and normal operation resumes under the external Enable signal applied to EN/PG input. Another feature includes an internal 1-MΩ resistor that pulls EN/PG pin low and disables the driver in case the system controller accidentally loses connection with the driver. This could happen if, for example, the system controller is located on a separate PCB daughter board. The EN/PG pin can serve as the second pulse input of the driver additionally to PWM input. The delay between EN/PG and the UGATE going high, provided that PWM input is also high, is only about 30ns. If the PWM input pulses are synchronized with EN/PG input, then when PWM and EN/PG are high, the UGATE is high and LGATE is low. If both PWM and EN/PG are low, then UGATE and LGATE are both low as well. This means the driver allows operation of a synchronous buck regulator as a convertional buck regulator using the body diode of the low side power MOSFET as the freewheeling diode. This feature can be useful in some specific applications to allow startup with a pre-biased output or, to improve the efficiency of buck regulator when in power saving mode with low output current. Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 Submit Documentation Feedback 17 TPS28225-Q1 TPS28226-Q1 SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 www.ti.com 3-State Input As soon as the EN/PG pin is set high and input PWM pulses are initiated (see Note below). The dead-time control circuit ensures that there is no overlapping between UGATE and LGATE drive outputs to eliminate shoot through current through the external power FETs. Additionally to operate under periodical pulse sequencing, the TPS2822x-Q1 has a self-adjustable PWM 3-state input circuit. The 3-state circuit sets both gate drive outputs low, and thus turns the external power FETs OFF if the input signal is in a high impedance state for at least 250 ns typical. At this condition, the PWM input voltage level is defined by the internal 27kΩ to 13kΩ resistor divider shown in the block diagram. This resistor divider forces the input voltage to move into the 3-state window. Initially the 3-state window is set between 1.0-V and 2.0-V thresholds. The lower threshold of the 3-state window is always fixed at about 1.0 V. The higher threshold is adjusted to about 75% of the input signal amplitude. The self-adjustable upper threshold allows shorter delay if the input signal enters the 3-state window while the input signal was high, thus keeping the high-side power FET in ON state just slightly longer than 250 ns time constant set by an internal 3-state timer. Both modes of operation, PWM input pulse sequencing and the 3-state condition, are illustrated in the timing diagrams shown in Figure 21. The self-adjustable upper threshold allows operation in wide range amplitude of input PWM pulse signals. The waveforms in Figure 23 and Figure 24 illustrates the TPS28225-Q1 operation at normal and 3-state mode with the input pulse amplitudes 6 V and 2.5 V accordingly. After entering into the 3-state window and staying within the window for the hold-off time, the PWM input signal level is defined by the internal resistor divider and, depending on the input pulse amplitude, can be pulled up above the normal PWM pulse amplitude (Figure 24) or down below the normal input PWM pulse (Figure 23). TPS28225-Q1 3-State Exit Mode: • To exit the 3-state operation mode, the PWM signal should go low and then high at least once. TPS28226-Q1 3-State Exit Mode: • To exit the 3-state operation mode, the PWM signal should go high and then low at least once. This is necessary to restore the voltage across the bootstrap capacitor that could be discharged during the 3state mode if the 3-state condition lasts long enough. Figure 23. 6-V Amplitude PWM Pulse (TPS28225Q1) Figure 24. 2.5-V Amplitude PWM Pulse (TPS28225Q1) NOTE The driver sets UGATE low and LGATE high when PWM is low. When the PWM goes high, UGATE goes high and LGATE goes low. 18 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 TPS28225-Q1 TPS28226-Q1 www.ti.com SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 IMPORTANT NOTE: Any external resistor between PWM input and GND with the value lower than 40kΩ can interfere with the 3-state thresholds. If the driver is intended to operate in the 3-state mode, any resistor below 40kΩ at the PWM and GND should be avoided. A resistor lower than 3.5kΩ connected between the PWM and GND completely disables the 3-state function. In such case, the 3-state window shrinks to zero and the lower 3state threshold becomes the boundary between the UGATE staying low and LGATE being high and vice versa depending on the PWM input signal applied. It is not necessary to use a resistor <3.5kΩ to avoid the 3-state condition while using a controller that is 3-state capable. If the rise and fall time of the input PWM signal is shorter than 250ns, then the driver never enter into the 3-state mode. In the case where the low-side MOSFET of a buck converter stays on during shutdown, the 3-state feature can be fused to avoid negative resonent voltage across the output capacitor. This feature also can be used during start up with a pre-biased output in the case where pulling the output low during the startup is not allowed due to system requirements. If the system controller does not have the 3-state feature and never goes into the highimpedance state, then setting the EN/PG signal low will keep both gate drive outputs low and turn both low- and high-side MOSFETs OFF during the shut down and start up with the pre-biased output. The self-adjustable input circuit accepts wide range of input pulse amplitudes (2V up to 13.2V) allowing use of a variety of controllers with different outputs including logic level. The wide PWM input voltage allows some flexibility if the driver is used in secondary side synchronous rectifier circuit. The operation of the TPS2822x-Q1 with a 12-V input PWM pulse amplitude, and with VDD = 7.2V and VDD = 5V respectively is shown in Figure 25 and Figure 26. Figure 25. 12-V PWM Pulse at VDD = 7.2 V Figure 26. 12-V PWM Pulse at VDD = 5 V Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 Submit Documentation Feedback 19 TPS28225-Q1 TPS28226-Q1 SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 www.ti.com Bootstrap Diode The bootstrap diode provides the supply voltage for the UGATE driver by charging the bootstrap capacitor connected between BOOT and PHASE pins from the input voltage VDD when the low-side FET is in ON state. At the very initial stage when both power FETs are OFF, the bootstrap capacitor is pre-charged through this path including the PHASE pin, output inductor and large output capacitor down to GND. The forward voltage drop across the diode is only 1.0V at bias current 100 mA. This allows quick charge restore of the bootstrap capacitor during the high-frequency operation. Upper And Lower Gate Drivers The upper and lower gate drivers charge and discharge the input capacitance of the power MOSFETs to allow operation at switching frequencies up to 2 MHz. The output stage consists of a P-channel MOSFET providing source output current and an N-channel MOSFET providing sink current through the output stage. The ON state resistances of these MOSFETs are optimized for the synchronous buck converter configuration working with low duty cycle at the nominal steady state condition. The UGATE output driver is capable of propagating PWM input puses of less than 30-ns while still maintaining proper dead time to avoid any shoot through current conditions. The waveforms related to the narrow input PWM pulse operation are shown in Figure 20. Dead-Time Control The dead-time control circuit is critical for highest efficiency and no shoot through current operation througout the whole duty cycle range with the different power MOSFETs. By sensing the output of driver going low, this circuit does not allow the gate drive output of another driver to go high until the first driver output falls below the specified threshold. This approach to control the dead time is called adaptive. The overall dead time also includes the fixed portion to ensure that overlapping never exists. The typical dead time is around 14 ns, although it varies over the driver internal tolerances, layout and external MOSFET parasitic inductances. The proper dead time is maintained whenever the current through the output inductor of the power stage flows in the forward or reverse direction. Reverse current could happen in a buck configuration during the transients or while dynamically changing the output voltage on the fly, as some microprocessors require. Because the dead time does not depend on inductor current direction, this driver can be used both in buck and boost regulators or in any bridge configuration where the power MOSFETs are switching in a complementary manner. Keeping the dead time at short optimal level boosts efficiency by 1% to 2% depending on the switching frequency. Measured switching waveforms in one of the practical designs show 10-ns dead time for the rising edge of PHASE node and 22 ns for the falling edge (Figure 32 and Figure 33 in the Application Section of the data sheet). Large non-optimal dead time can cause duty cycle modulation of the dc-to-dc converter during the operation point where the output inductor current changes its direction right before the turn ON of the high-side MOSFET. This modulation can interfere with the controller operation and it impacts the power stage frequency response transfer function. As the result, some output ripple increase can be observed. The TPS2822x-Q1 driver is designed with the short adaptive dead time having fixed delay portion that eliminates risk of the effective duty cycle modulation at the described boundary condition. Thermal Shutdown If the junction temperature exceeds 160°C, the thermal shutdown circuit will pull both gate driver outputs low and thus turning both, low-side and high-side power FETs OFF. When the driver cools down below 140°C after a thermal shutdown, then it resumes its normal operation and follows the PWM input and EN/PG signals from the external control circuit. While in thermal shutdown state, the internal MOSFET pulls the EN/PG pin low, thus setting a flag indicating the driver is not ready to continue normal operation. Normally the driver is located close to the MOSFETs, and this is usually the hottest spots on the PCB. Thus, the thermal shutdown feature of TPS2822x-Q1 can be used as an additional protection for the whole system from overheating. 20 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 TPS28225-Q1 TPS28226-Q1 www.ti.com SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 APPLICATION INFORMATION Switching The MOSFETs Driving the MOSFETs efficiently at high switching frequencies requires special attention to layout and the reduction of parasitic inductances. Efforts need to be done both at the driver’s die and package level and at the PCB layout level to keep the parasitic inductances as low as possible. Figure 27 shows the main parasitic inductances and current flow during turning ON and OFF of the MOSFET by charging its CGS gate capacitance. L bond wire L pin 6 L trace VDD I source Rsource Driver Output L bond wire L pin 5 Stage Rsink Cvdd L trace Rg LGATE I sink L pin L bond wire 4 L trace L trace Cgs GND Figure 27. MOSFET Drive Paths and Main Circuit Parasitics Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 Submit Documentation Feedback 21 TPS28225-Q1 TPS28226-Q1 SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 www.ti.com Voltage LGATE Falling, V or A LGATE Falling, V or A The ISOURCE current charges the gate capacitor and the ISINK current discharges it. The rise and fall time of voltage across the gate defines how quickly the MOSFET can be switched. The timing parameters specified in datasheet for both upper and lower driver are shown in Figure 18 and Figure 19 where 3-nF load capacitor has been used for the characterization data. Based on these actual measurements, the analytical curves in Figure 28 and Figure 29 show the output voltage and current of upper and low side drivers during the discharging of load capacitor. The left waveforms show the voltage and current as a function of time, while the right waveforms show the relation between the voltage and current during fast switching. These waveforms show the actual switching process and its limitations because of parasitic inductances. The static VOUT/ IOUT curves shown in many datasheets and specifications for the MOSFET drivers do not replicate actual switching condition and provide limited information for the user. Current t − Time − ns LGATE Current, A Figure 28. LGATE Turning Off Voltage and Sink Current vs Time (Related Switching Diagram (right)) UGATE Falling, V UGATE Falling, V Voltage Current t − Time − ns UGATE Current, A Figure 29. UGATE Turning Off Voltage and Sink Current vs Time (Related Switching Diagram (right)) 22 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 TPS28225-Q1 TPS28226-Q1 www.ti.com SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 Turning Off of the MOSFET needs to be done as fast as possible to reduce switching losses. For this reason the TPS2822x-Q1 driver has very low output impedance specified as 0.4Ω typ for lower driver and 1Ω typ for upper driver at dc current. Assuming 8-V drive voltage and no parasitic inductances, one can expect an initial sink current amplitude of 20A and 8A respectively for the lower and upper drivers. With pure R-C discharge circuit for the gate capacitor, the voltage and current waveforms are expected to be exponential. However, because of parasitic inductances, the actual waveforms have some ringing and the peak current for the lower driver is about 4A and about 2.5A for the upper driver (Figure 28 and Figure 29). The overall parasitic inductance for the lower drive path is estimated as 4nH and for the upper drive path as 6nH. The internal parasitic inductance of the driver, which includes inductances of bonded wires and package leads, can be estimated for SOIC-8 package as 2nH for lower gate and 4nH for the upper gate. Use of DFN-8 package reduces the internal parasitic inductances by approximately 50%. Layout Recommendations To • • • • • • • improve the switching characteristicsand efficiency of a design, the following layout rules need to be followed. Locate the driver as close as possible to the MOSFETs. Locate the VDD and bootstrap capacitors as close as possible to the driver. Pay special attention to the GND trace. Use the thermal pad of the DFN-8 package as the GND by connecting it to the GND pin. The GND trace or pad from the driver goes directly to the source of the MOSFET but should not include the high current path of the main current flowing through the drain and source of the MOSFET. Use a similar rule for the PHASE node as for the GND. Use wide traces for UGATE and LGATE closely following the related PHASE and GND traces. Eighty to 100 mils width is preferable where possible. Use at least 2 or more vias if the MOSFET driving trace needs to be routed from one layer to another. For the GND the number of vias are determined not only by the parasitic inductance but also by the requirements for the thermal pad. Avoid PWM and enable traces going close to the PHASE node and pad where high dV/dT voltage can induce significant noise into the relatively high impedance leads. It should be taken into account that poor layout can cause 3% to 5% less efficiency versus a good layout design and can even decrease the reliability of the whole system. Figure 30. One of Four Phases Driven by TPS2822x-Q1 Driver in 4-phase VRM Reference Design Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 Submit Documentation Feedback 23 TPS28225-Q1 TPS28226-Q1 SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 www.ti.com The schematic of one of the phases in a multi-phase synchronous buck regulator and the related layout are shown in Figure 30 and Figure 31. These help to illustrate good design practices. The power stage includes one high-side MOSFET Q10 and two low-side MOSFETS (Q8 and Q9). The driver (U7) is located on bottom side of PCB close to the power MOSFETs. The related switching waveforms during turning ON and OFF of upper FET are shown in Figure 32 and Figure 33. The dead time during turning ON is only 10ns (Figure 32) and 22ns during turning OFF (Figure 33). Figure 31. Component Placement Based on Schematic in Figure 30 Figure 32. Phase Rising Edge Switching Waveforms (20ns/div) of the Power Stage in Figure 30 24 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 TPS28225-Q1 TPS28226-Q1 www.ti.com SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 Figure 33. Phase Falling Edge Switching Waveforms (10ns/div) of the Power State in Figure 30 List of Materials The list of materials for this specific example is provided in the table. The component vendors are not limited to those shown in the table below. It should be notd that, in this example, the power MOSFET packages were chosen with drains on top. The decoupling capacitors C47, C48, C65, and C66 were chosen to have low profiles. This allows the designer to meet good layout rules and place a heatsink on top of the FETs using an electrically isolated and thermally conductive pad. Table 1. List of Materials MANUFACTURE PART NUMBER C47, C48, C65, C66 REF DES COUNT 4 Capacitor, ceramic, 4.7 μF, 16 V, X5R 10%, low profile 0.95 mm, 1206 DESCRIPTION TDK C3216X5R1C475K C41, C42 2 Capacitor, ceramic, 10 μF, 16 V, X7R 10%, 1206 TDK C3216X7R1C106K C50, C51 2 Capacitor, ceramic, 1000 pF, 50 V, X7R, 10%, 0603 Std Std C23 1 Capacitor, ceramic, 0.22 μF, 16 V, X7R, 10%, 0603 Std Std C25, C49, C71 3 Capacitor, ceramic, 1 μF, 16 V, X7R, 10%, '0603 Std Std L3 1 Inductor, SMT, 0.12 μH, 31 A, 0.36 mΩ, 0.400 x 0.276 Pulse PA0511-101 Q8, Q9 2 Mosfet, N-channel, VDS 30 V, RDS 2.4 mΩ, ID 45 A, LFPAK-i Renesas RJK0301DPB-I Q10 1 Mosfet, N-channel, VDS 30 V, RDS 6.2 mΩ, ID 30 A, LFPAK-i Renesas RJK0305DPB-I R32 1 Resistor, chip, 0 Ω, 1/10 W, 1%, '0805 Std Std R51, R52 2 Resistor, chip, 2.2 Ω, 1/10 W, 1%, '0805 Std Std U7 1 Device, High Frequency 4-A Sink Synchronous Buck MOSFET Driver, DFN-8 Texas Instruments TPS28225-Q1DRB Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 Submit Documentation Feedback 25 TPS28225-Q1 TPS28226-Q1 SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 www.ti.com Efficiency of Power Stage vs Load Current at Different Switching Frequencies Efficiency achieved using TPS2822x-Q1 driver with 8-V drive at different switching frequencies a similar industry 5-V driver using the power stage in Figure 30 is shown in Figure 36, Figure 38, Figure 37, Figure 34 and Figure 35. EFFICIENCY vs LOAD CURRENT EFFICIENCY vs LOAD CURRENT 85 85 Efficiency − % 90 Efficiency − % 90 80 80 TI: 400kHz TI: 500kHz Ind: 400kHz Ind: 500kHz 75 75 5 10 15 25 20 30 35 5 10 15 CL − Load Currnt − A 20 25 30 35 CL − Load Currnt − A Figure 34. Figure 35. EFFICIENCY vs LOAD CURRENT 90 TI: 600kHz Ind: 600kHz Efficiency − % 85 80 75 5 10 15 20 25 30 35 CL − Load Currnt − A Figure 36. 26 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 TPS28225-Q1 TPS28226-Q1 www.ti.com SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 EFFICIENCY vs LOAD CURRENT EFFICIENCY vs LOAD CURRENT 90 90 TI: 700kHz Ind: 700kHz TI: 800kHz Ind: 800kHz Efficiency − % 85 Efficiency − % 85 80 80 75 75 5 10 15 20 25 30 35 5 10 15 CL − Load Currnt − A 20 25 30 35 CL − Load Currnt − A Figure 37. Figure 38. When using the same power stage, the driver with the optimal drive voltage and optimal dead time can boost efficiency up to 5%. The optimal 8-V drive voltage versus 5-V drive contributes 2% to 3% efficiency increase and the remaining 1% to 2% can be attributed to the reduced dead time. The 7-V to 8-V drive voltage is optimal for operation at switching frequency range above 400kHz and can be illustrated by observing typical RDS(on) curves of modern FETs as a function of their gate drive voltage. This is shown in Figure 39. DRIVE LOSS vs SWITCHING FREQUENCY 2.0 12−V Estimation Rdson Vg = 5V @ Rdson @ Vg = 7V DL − Drive Loss − W 1.5 SOIC−8 Package Limit at 45°C 1.0 8−V TPS28225 5−V Ind. Std. 0.5 0.0 400 500 600 700 800 FSW − Switching Frequency − kHz Figure 39. RDS(on) of MOSFET as Function of VGS Figure 40. Drive Power as Function of VGS and FSW Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 Submit Documentation Feedback 27 TPS28225-Q1 TPS28226-Q1 SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 www.ti.com The plots show that the RDS(on) at 5-V drive is substantially larger than at 7 V and above that the RDS(on) curve is almost flat. This means that moving from 5-V drive to an 8-V drive boosts the efficiency because of lower RDS(on) of the MOSFETs at 8 V. Further increase of drive voltage from 8 V to 12 V only slightly decreases the conduction losses but the power dissipated inside the driver increases dramatically (by 125%). The power dissipated by the driver with 5V, 8V and 12V drive as a function of switching frequency from 400 kHz to 800 kHz. It should be noted that the 12-V driver exceeds the maximum dissipated power allowed for an SOIC-8 package even at 400kHz switching frequency. RELATED PRODUCTS • • 28 TPS40090, 2/3/4-Phase Multi-Phase Controller TPS40091, 2/3/4-Phase Multi-Phase Controller Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 TPS28225-Q1 TPS28226-Q1 www.ti.com SLUSAR9A – DECEMBER 2011 – REVISED MAY 2012 REVISION HISTORY Changes from Original (December, 2011) to Revision A Page • Added AEC-Q100 info to Features. ...................................................................................................................................... 1 • Added AEC-Q100 info to ESD rating in Abs Max table and changed the CDM from 500 to 750 V. ................................... 5 Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS28225-Q1 TPS28226-Q1 Submit Documentation Feedback 29 PACKAGE OPTION ADDENDUM www.ti.com 5-Apr-2012 PACKAGING INFORMATION Orderable Device TPS28225TDRBRQ1 Status (1) Package Type Package Drawing ACTIVE SON DRB Pins Package Qty 8 3000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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