OPA694 SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004 Wideband, Low-Power, Current Feedback Operational Amplifier FEATURES DESCRIPTION D D D D D D The OPA694 is an ultra-wideband, low-power, current feedback operational amplifier featuring high slew rate and low differential gain/phase errors. An improved output stage provides ±80mA output drive with < 1.5V output voltage headroom. Low supply current with > 500MHz bandwidth meets the requirements of high density video routers. Being a current feedback design, the OPA694 holds its bandwidth to very high gains—at a gain of 10, the OPA694 will still provide 200MHz bandwidth. D UNITY GAIN STABLE BANDWIDTH: 1.5GHz HIGH GAIN OF 2V/V BANDWIDTH: 690MHz LOW SUPPLY CURRENT: 5.8mA HIGH SLEW RATE: 1700V/µsec HIGH FULL-POWER BANDWIDTH: 675MHz LOW DIFFERENTIAL GAIN/PHASE: 0.03%/0.0155 Pb-FREE AND GREEN SOT23-5 PACKAGE RF applications can use the OPA694 as a low-power SAW pre-amplifier. Extremely high 3rd-order intercept is provided through 70MHz at much lower quiescent power than many typical RF amplifiers. APPLICATIONS D D D D D WIDEBAND VIDEO LINE DRIVER MATRIX SWITCH BUFFER The OPA694 is available in an industry-standard pinout in both SO-8 and SOT23-5 packages. DIFFERENTIAL RECEIVER ADC DRIVER IMPROVED REPLACEMENT FOR OPA658 +5V VIN 75Ω 75Ω RELATED PRODUCTS VLOAD RG− 59 OPA694 75Ω SINGLES DUALS TRIPLES QUADS 402Ω FEATURES — OPA2694 — — Dual Version OPA683 OPA2683 — — Low-Power, CFBplus OPA684 OPA2684 OPA3684 OPA4684 Low-Power, CFBplus OPA691 OPA2691 OPA3691 — High Output OPA695 OPA2695 OPA3695 — High Intercept 402Ω −5V Gain 2V/V Video Line Driver Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright 2004, Texas Instruments Incorporated ! ! www.ti.com "#$ www.ti.com SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004 ABSOLUTE MAXIMUM RATINGS(1) Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6.5VDC Internal Power Dissipation . . . . . . . . . See Thermal Characteristics Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.2V Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS Storage Temperature Range: D, DBV . . . . . . . . . −40°C to +125°C Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C ESD Rating: Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . 1500V Charge Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . . 1000V Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR OPA694 SO-8 D −40°C to +85°C OPA694 OPA694 SOT23-5 DBV −40°C to +85°C BIA ORDERING NUMBER TRANSPORT MEDIA, QUANTITY OPA694ID Rails, 100 OPA694IDR Tape and Reel, 2500 OPA694IDBVT Tape and Reel, 250 OPA694IDBVR Tape and Reel, 3000 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or refer to our website at www.ti.com. PIN CONFIGURATIONS Top View Top View NC 1 8 NC Inverting Input 2 7 +VS Noninverting Input 3 6 Output −VS 4 5 NC Output 1 −VS 2 Noninverting Input 3 5 +VS 4 Inverting Input 4 5 SOT23−5 3 1 2 BIA SO−8 NC = No Connection Pin Orientation/Package Marking 2 "#$ www.ti.com SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004 ELECTRICAL CHARACTERISTICS: VS = ±5V Boldface limits are tested at +25°C. At RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted. OPA694ID, IDBV TYP PARAMETER MIN/MAX OVER TEMPERATURE +25°C(1) 0°C to 70°C(2) −40°C to +85°C(2) 690 350 340 330 250 200 180 200 150 130 CONDITIONS +25°C G = +1, VO = 0.5VPP, RF = 430Ω 1500 G = +2, VO = 0.5VPP, RF = 402Ω G = +5, VO = 0.5VPP, RF = 318Ω G = +10, VO = 0.5VPP, RF = 178Ω G = +1, VO = 0.5VPP, RF = 430Ω MIN/ MAX TEST LEVEL(3) MHz typ C MHz min B 160 MHz min B 120 MHz min B MHz typ C UNITS AC PERFORMANCE (see Figure 1) Small-Signal Bandwidth Bandwidth for 0.1dB Gain Flatness 90 VO ≤ 0.2VPP, RF = 430Ω G = +2, VO = 2VPP 2 dB typ C 675 MHz typ C G = +2, 2V Step 1700 V/µs min B G = +2, VO = 0.2V Step 0.8 ns typ C G = +2, VO = 2V Step 20 ns typ C G = +2, VO = 2V Step 13 ns typ C 2nd-Harmonic G = +2, f = 5MHz, VO = 2VPP RL = 100Ω −68 −63 −62 −61 dBc max B −92 −87 −85 −83 dBc max B 3rd-Harmonic RL ≥ 500Ω RL = 100Ω −72 −69 −67 −66 dBc max B RL ≥ 500Ω f > 1MHz −93 −88 −86 −84 dBc max B 2.1 2.4 2.8 3.0 nV/√Hz max B Inverting Input Current Noise Density f > 1MHz 22 24 26 28 pA/√Hz max B Noninverting Input Current Noise Density f > 1MHz 24 26 28 30 pA/√Hz max B VO = 1.4VPP, RL = 150Ω VO = 1.4VPP, RL = 37.5Ω 0.03 % typ C 0.05 % typ C G = +2, VO = 1.4VPP, RL = 150Ω 0.015 ° typ C VO = 1.4VPP, RL = 37.5Ω 0.16 ° typ C VO = 0V, RL = 100Ω VCM = 0V 145 90 65 60 kΩ min A ±0.5 ±3.0 ±3.7 ±4.1 mV max A 12 15 µV/°C max B ±26 ±31 µA max A ±100 ±150 nA/°C max B ±26 ±38 µA max A ±150 ±200 nA/°C max B A Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise Time and Fall Time Settling Time to 0.01% to 0.1% Harmonic Distortion Input Voltage Noise Density NTSC Differential Gain NTSC Differential Phase 1300 1275 1250 DC PERFORMANCE(4) Open-Loop Transimpedance Input Offset Voltage Average Input Offset Voltage Drift Non-inverting Input Bias Current Average Input Bias Current Drift VCM = 0V VCM = 0V Inverting Input Bias Current VCM = 0V VCM = 0V Average Input Bias Current Drift VCM = 0V ±5 ±2 ±20 ±18 INPUT Common-mode Input Voltage(5) (CMIR) Common-Mode Rejection Ratio (CMRR) VCM = 0V Noninverting Input Impedance Inverting Input Resistance Open-Loop ±2.5 ±2.3 ±2.2 ±2.1 V min 60 55 53 51 dB min A 280 1.2 kΩ pF typ C 30 Ω typ C OUTPUT Voltage Output Voltage Output Current Short-Circuit Output Current Closed-Loop Output Impedance No Load ±4 ±3.8 ±3.7 ±3.6 V min A RL = 100Ω VO = 0V ±3.4 ±3.1 ±3.1 ±3.0 V min A ±80 ±60 ±58 ±50 mA min A VO = 0V G = +2, f =100kHz ±200 mA typ C 0.02 Ω typ C (1) Junction temperature = ambient for +25°C specifications. (2) Junction temperature = ambient at low temperature limits; junction temperature = ambient +9°C at high temperature limit for over temperature specifications. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out of node. V CM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMRR at ±CMIR limits. 3 "#$ www.ti.com SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004 ELECTRICAL CHARACTERISTICS: VS = ±5V (continued) Boldface limits are tested at +25°C. At RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted. OPA694ID, IDBV TYP MIN/MAX OVER TEMPERATURE +25°C(1) 0°C to 70°C(2) −40°C to +85°C(2) Maximum Operating Voltage Range ±6.3 ±6.3 ±6.3 Minimum Operating Voltage Range ±3.5 ±3.5 PARAMETER CONDITIONS +25°C MIN/ MAX TEST LEVEL(3) V typ C V max A ±3.5 V max B UNITS POWER SUPPLY ±5 Specified Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Power-Supply Rejection Ratio (−PSRR) VS = ±5V VS = ±5V 5.8 6.0 6.2 6.3 mA max A 5.8 5.6 5.3 5.0 mA min A Input-Referred 58 54 52 50 dB min A −40 to +85 °C typ C THERMAL CHARACTERISTICS Specification: ID, IDBV Thermal Resistance qJA Junction-to-Ambient D SO-8 125 °C/W typ C DBV SOT-23 150 °C/W typ C (1) Junction temperature = ambient for +25°C specifications. (2) Junction temperature = ambient at low temperature limits; junction temperature = ambient +9°C at high temperature limit for over temperature specifications. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out of node. V CM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMRR at ±CMIR limits. 4 "#$ www.ti.com SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS: VS = ±5V At RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted. NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE INVERTING SMALL−SIGNAL FREQUENCY RESPONSE 3 3 −3 −6 G = +10V/V RF = 178Ω −9 G = −5V/V RF = 318Ω 0 Normalized Gain (dB) G = +2V/V R F = 402Ω 0 G = +5V/V RF = 318Ω G = −1V/V RF = 430Ω −3 −6 G = −10V/V RF = 500Ω −9 −12 G = −2V/V RF = 402Ω −15 See Figure 1 See Figure 2 −18 −12 0 700 400 600 800 1000 0 INVERTING LARGE−SIGNAL FREQUENCY RESPONSE 1000 9 G = +2V/V RF = 402Ω 6 VO = 4VPP V = 2V O PP 3 Gain (dB) 3 Gain (dB) 800 600 NONINVERTING LARGE−SIGNAL FREQUENCY RESPONSE 6 0 VO = 2VPP −3 0 VO = 1VPP −3 VO = 7VPP −6 −6 VO = 7VPP −9 VO = 4VPP See Figure 1 200 −12 400 600 800 0 1000 200 400 600 Frequency (MHz) Frequency (MHz) NONINVERTING PULSE RESPONSE INVERTING PULSE RESPONSE 3 Small Signal, 0.5VPP Right Scale 0 0.4 0.2 0 −1 −0.2 −2 −0.4 −3 −0.6 Time (5ns/div) 1000 0.6 G = −2V/V 2 Output Voltage (1V/div) Large Signal, 5VPP Left Scale 800 3 0.6 See Figure 1 G = +2V/V Output Voltage (200mV/div) 0 G = −2V/V R F = 402Ω See Figure 2 −9 −12 Output Voltage (1V/div) 400 Frequency (MHz) VO = 1VPP 1 200 Frequency (MHz) 9 2 VO = 0.5VPP RL = 100Ω 1 See Figure 2 Large Signal, 5VPP Left Scale Small Signal, 0.5VPP Right Scale 0 0.4 0.2 0 −1 −0.2 −2 −0.4 −3 Output Voltage (200mV/div) Normalized Gain (dB) VO = 0.5VPP RL = 100Ω −0.6 Time (5ns/div) 5 "#$ www.ti.com SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted. HARMONIC DISTORTION vs LOAD RESISTANCE HARMONIC DISTORTION vs SUPPLY VOLTAGE −65 −75 Harmonic Distortion (dBc) −70 Harmonic Distortion (dBc) −60 G = +2V/V f = 5MHz VO = 2VPP 2nd Harmonic −80 −85 3rd Harmonic −90 −95 See Figure 1 −100 100 G = +2V/V f = 5MHz RL = 100Ω VO = 2VPP −65 2nd Harmonic −70 3rd Harmonic −75 See Figure 1 −80 1000 3.5 4.0 Load Resistance (Ω ) Harmonic Distortion (dBc) Harmonic Distortion (dBc) G = +2V/V R L = 100Ω VO = 2VPP 2nd Harmonic −70 −80 3rd Harmonic −90 G = +2V/V RL = 100Ω f = 5MHz −70 6.0 2nd Harmonic −75 3rd Harmonic −80 See Figure 1 See Figure 1 −85 −100 0.1 1 10 0.1 20 1 Frequency (MHz) Output Voltage Swing (VPP) HARMONIC DISTORTION vs NONINVERTING GAIN HARMONIC DISTORTION vs INVERTING GAIN −60 10 −60 RL = 100Ω f = 5MHz VO = 2VPP Harmonic Distortion (dBc) Harmonic Distortion (dBc) 5.5 −65 −50 −65 2nd Harmonic −70 3rd Harmonic RL = 100Ω f = 5MHz VO = 2VPP −65 2nd Harmonic −70 3rd Harmonic See Figure 2 See Figure 1 −75 −75 1 10 Gain (V/V) 6 5.0 HARMONIC DISTORTION vs OUTPUT VOLTAGE HARMONIC DISTORTION vs FREQUENCY −60 4.5 Supply Voltage (±VS) 1 10 Gain (|V/V|) "#$ www.ti.com SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted. INPUT VOLTAGE AND CURRENT NOISE 2−TONE, 3rd−ORDER INTERMODULATION INTERCEPT 1k 55 50Ω PI Intercept Point (+dBm) Current Noise (pA/√Hz) Voltage Noise (nV/√Hz) 50 Noninverting Current Noise (24pA/√Hz) 100 Inverting Current Noise (22pA/√Hz) 10 Voltage Noise (2.1nV/√Hz) 50Ω 402Ω 45 402Ω 40 35 30 25 20 1 10 100 1k 10k 100k 1M 10M 100M 10 0 20 30 40 60 50 70 Frequency (Hz) Frequency (MHz) RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 60 80 90 100 3 CL = 10pF 0dB Peaking Targeted 0 Normalized Gain (dB) 50 40 RS (Ω) PO OPA694 50Ω 30 20 CL = 47pF −6 RS VI −9 −15 0 −18 VO OPA694 50Ω 1kΩ(1) CL 402Ω −12 10 CL = 22pF CL = 100pF −3 402Ω NOTE: (1) 1kΩ load is optional 10 100 10M 1M 100M Capacitive Load (pF) Frequency (Hz) COMMON−MODE REJECTION RATIO AND POWER−SUPPLY REJECTION RATIO vs FREQUENCY OPEN−LOOP ZOL GAIN AND PHASE 70 1G 120 30 110 0 100 −30 +PSRR PSRR (dB) CMRR (dB) 50 40 −PSRR 30 20 10 0 100 1K 10K 100K Frequency (Hz) 1M 10M 100M −60 90 < ZOL 80 −120 70 20 log |ZOL| 60 −150 −180 50 40 100 −90 Open−Loop ZOL Phase (_ ) 60 Open−Loop ZOL Gain (dBΩ) CMRR −210 1K 10K 100K 1M 10M 100M 1G Frequency (Hz) 7 "#$ www.ti.com SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted. VIDEO DIFFERENTIAL GAIN/DIFFERNTIAL PHASE (No Pulldown) TYPICAL DC DRIFT OVER TEMPERATURE 0.08 0.04 dG Negative Video 0.04 0.02 dP Negative Video 2 4 Noninverting Input Bias Current (IBN) Right Scale +75 +100 10 90 RL = 50Ω Output Current Limit 1 RL = 25Ω 0 Output Current Limit 9 Left Scale 80 8 Sinking Output Current Left Scale 70 7 Supply Current 60 6 Right Scale 50 1W Internal Power Limit −100 −10 +125 Sourcing Output Current Output Current (mA) Output Voltage (V) +50 100 0 100 40 −50 200 5 −25 0 +25 +50 +75 Output Current (mA) Ambient Temperature (_ C) NONINVERTING OVERDRIVE RECOVERY INVERTING OVERDRIVE RECOVERY 4 4 8 0 −2 −4 Input Voltage (V) Output Left Scale 0 4 +125 RL = 100Ω G = −1V/V 2 4 +100 4 RL = 100Ω G = +2V/V Output Voltage (V) Input Right Scale Output Voltage (V) +25 SUPPLY AND OUTPUT CURRENT vs TEMPERATURE −3 2 2 Input Right Scale 0 0 Output Left Scale −2 −2 See Figure 2 See Figure 1 −4 −8 Time (10ns/div) 8 0 OUTPUT VOLTAGE AND CURRENT LIMITATIONS RL = 100Ω −4 −200 −25 Ambient Temperature (_ C) 2 −2 −5 −0.5 Video Loads 1W Internal Power Limit 5 0 0 3 −1 Inverting Input Bias Current (I BI) Right Scale Supply Current (mA) 4 3 0.5 −4 −4 Time (10ns/div) Input Voltage (V) 1 Input Offset Voltage (VOS) Left Scale −1.0 −50 0 0 Input Offset Voltage (mV) dG Positive Video Differential Phase (_ ) Differential Gain (%) 0.12 0.06 10 1.0 dP Positive Video Input Bias and Offset Current (µA) 0.16 0.08 "#$ www.ti.com SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At RF = 402Ω, RL = 100Ω, and GD = 2V/V, unless otherwise noted. Differential Performance Test Circuit DIFFERENTIAL SMALL−SIGNAL FREQUENCY RESPONSE +5V 3 VO = 2VPP RL = 400Ω RG RF RG RF VI RT RL 400Ω OPA694 VO VI = RF RG VO Normalized Gain (dB) 0 OPA694 GD = 1 GD = 2 RF = 430Ω R = 402Ω F −3 −6 GD = 5 RF = 330Ω −9 GD = 10 RF = 250Ω −12 = GD 0 50 100 150 200 250 −5V DIFFERENTIAL LARGE−SIGNAL FREQUENCY RESPONSE −60 6 Gain (dB) VO = 12VPP 3 VO = 5VPP VO = 16VPP Harmonic Distortion (dBc) GD = 2 R L = 400Ω −3 VO = 8VPP 400 450 500 VO = 4VPP f = 5MHz GD = 2 −65 3rd Harmonic −70 −75 −80 −85 2nd Harmonic −6 −90 0 50 100 150 200 250 300 350 400 450 500 10 1000 Resistance (Ω) DIFFERENTIAL DISTORTION vs FREQUENCY DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE GD = 2 VO = 4VPP RL = 400Ω −65 3rd Harmonic Harmonic Distortion (dBc) −65 100 Frequency (MHz) −55 Harmonic Distortion (dBc) 350 DIFFERENTIAL DISTORTION vs LOAD RESISTANCE 9 0 300 Frequency (MHz) −75 2nd Harmonic −85 −95 GD = 2 f = 5MHz RL = 400Ω −70 −75 3rd Harmonic −80 −85 −90 2nd Harmonic −95 −105 1 10 Frequency (MHz) 20 0.1 1 10 100 Output Voltage Swing (VPP ) 9 "#$ www.ti.com SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004 WIDEBAND CURRENT FEEDBACK OPERATION The OPA694 provides exceptional AC performance for a wideband, low-power, current-feedback operational amplifier. Requiring only 5.8mA quiescent current, the OPA694 offers a 690MHz bandwidth at a gain of +2, along with a 1700V/µs slew rate. An improved output stage provides ±80mA output drive, along with < 1.5V output voltage headroom. This combination of low power and high bandwidth can benefit high-resolution video applications. Figure 1 shows the DC-coupled, gain of +2, dual powersupply circuit configuration used as the basis of the ±5V Electrical Characteristic tables and Typical Characteristic curves. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 50Ω with a series output resistor. Voltage swings reported in the Electrical Charateristics are taken directly at the input and output pins, while load powers (dBm) are defined at a matched 50Ω load. For the circuit of Figure 1, the total effective load will be 100Ω || 804Ω = 89Ω. One optional component is included in Figure 1. In addition to the usual power-supply decoupling capacitors to ground, a 0.1µF capacitor is included between the two power-supply pins. In practical PC board layouts, this optional added capacitor will typically improve the 2nd-harmonic distortion performance by 3dB to 6dB. Figure 2 shows the DC-coupled, gain of −2V/V, dual power-supply circuit used as the basis of the inverting Typical Characteristic curves. Inverting operation offers several performance benefits. Since there is no common-mode signal across the input stage, the slew rate for inverting operation is higher and the distortion performance is slightly improved. An additional input resistor, RT, is included in Figure 2 to set the input impedance equal to 50Ω. The parallel combination of RT and RG sets the input impedance. Both the noninverting and inverting applications of Figure 1 and Figure 2 will benefit from optimizing the feedback resistor (RF) value for bandwidth (see the discussion in Setting Resistor Values to Optimize Bandwidth). The typical design sequence is to select the RF value for best bandwidth, set RG for the gain, then set RT for the desired input impedance. As the gain increases for the inverting configuration, a point will be reached where RG will equal 50Ω, where RT is removed and the input match is set by RG only. With RG fixed to achieve an input match to 50Ω, RF is simply increased, to increase gain. This will, however, quickly reduce the achievable bandwidth, as shown by the inverting gain of –10 frequency response in the Typical Characteristic curves. For gains > 10V/V (14dB at the matched load), noninverting operation is recommended to maintain broader bandwidth. +5V +VS 0.1µF 0.1µF +5V +VS + APPLICATION INFORMATION 20Ω 6.8µF + 6.8µF 50ΩLoad VO 50Ω OPA694 50ΩSource 50Ω Load VI 50Ω VO 50Ω Optional 0.01µF OPA694 50Ω Source 0.1µF VI RT 66.5Ω + −VS −5V 6.8µF 0.1µF 0.1µF Figure 1. DC-Coupled, G = +2, Bipolar-Supply Specification and Test Circuit 10 RF 402Ω 6.8µF + RG 402Ω RF 402Ω RG 200Ω −VS −5V Figure 2. DC-Coupled, G = −2V/V, Bipolar-Supply Specification and Test Circuit "#$ www.ti.com SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004 ADC DRIVER gain), wideband inverting summing stages may be implemented using the OPA694. The circuit in Figure 4 shows an example inverting summing amplifier, where the resistor values have been adjusted to maintain both maximum bandwidth and input impedance matching. If each RF signal is assumed to be driven from a 50Ω source, the NG for this circuit will be (1 + 100Ω/(100Ω/5)) = 6. The total feedback impedance (from VO to the inverting error current) is the sum of RF + (RI • NG). where RI is the impedance looking into the inverting input from the summing junction (see the Setting Resistor Values to Optimize Performance section). Using 100Ω feedback (to get a signal gain of –2 from each input to the output pin) requires an additional 30Ω in series with the inverting input to increase the feedback impedance. With this resistor added to the typical internal RI = 30Ω, the total feedback impedance is 100Ω + (60Ω • 6) = 460Ω, which is equal to the required value to get a maximum bandwidth flat frequency response for NG = 6. Most modern, high-performance analog-to-digital converters (ADCs), such as Texas Instruments ADS522x series, require a low-noise, low-distortion driver. The OPA694 combines low-voltage noise (2.1nV/√Hz) with low harmonic distortion. Figure 3 shows an example of a wideband, AC-coupled, 12-bit ADC driver. Two OPA694s are used in the circuit of Figure 3 to form a differential driver for the ADS5220. The two OPA694s offer > 250MHz bandwidth at a differential gain of 5V/V, with a 2VPP output swing. A 2nd-order RLC filter is used in order to limit the noise from the amplifier and provide some attenuation for higher-frequency harmonic distortion. WIDEBAND INVERTING SUMMING AMPLIFIER Since the signal bandwidth for a current-feedback op amp can be controlled independently of the noise gain (NG, which is normally the same as the noninverting signal +5V Power−supply decoupling not shown. C1 25Ω 100Ω 1:2 R1 L OPA694 V+ 500Ω C R2 VI 50Ω 12−Bit 40MSPS ADS5220 VCM 100Ω 500Ω 0.1µF R2 C1 Single−to−Differential Gain of 10 R1 L V− OPA694 25Ω −5V Figure 3. Wideband, AC-Coupled, Low-Power ADC Driver +5V DIS 50Ω V1 VO = −(V1 + V2 + V3 + V4 + V5) 50Ω 50Ω OPA694 RG−58 V2 50Ω 50Ω 30Ω V3 100Ω 50Ω 100MHz, −1dB Compression = 15dBm V4 50Ω −5V V5 Figure 4. 200MHz RF Summing Amplifier 11 "#$ www.ti.com SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004 SAW FILTER BUFFER One common requirement in an IF strip is to buffer the output of a mixer with enough gain to recover the insertion loss of a narrowband SAW filter. Figure 5 shows one possible configuration driving a SAW filter. The 2-Tone, 3rd-Order Intermodulation Intercept plot is shown in the Typical Characteritics curves. Operating in the inverting mode at a voltage gain of –8V/V, this circuit provides a 50Ω input match using the gain set resistor, has the feedback optimized for maximum bandwidth (250MHz in this case), and drives through a 50Ω output resistor into the matching network at the input of the SAW filter. If the SAW filter gives a 12dB insertion loss, a net gain of 0dB to the 50Ω load at the output of the SAW (which could be the input impedance of the next IF amplifier or mixer) will be delivered in the passband of the SAW filter. Using the OPA694 in this application will isolate the first mixer from the impedance of the SAW filter and provide very low two-tone, 3rd-order spurious levels in the SAW filter bandwidth. This circuit removes the peaking by bootstrapping out any parasitic effects on RG. The input impedance is still set by RM as the apparent impedance looking into RG is very high. RM may be increased to show a higher input impedance, but larger values will start to impact DC output offset voltage. This circuit creates an additional input offset voltage as the difference in the two input bias currents times the impedance to ground at VI. Figure 7 shows a comparison of small-signal frequency response for the unity gain buffer of Figure 1 compared to the improved approach shown in Figure 6. Either approach gives a low-power unity-gain buffer with > 1.56GHz bandwidth. +5V DIS OPA694 RG 430Ω RO VO 50Ω RF 430Ω VI RM 50Ω +12V −5V 5kΩ 50Ω 1000pF 0.1µF 5kΩ OPA694 PO Matching Network Figure 6. IF Amplifier Driving SAW Filter 50Ω 50Ω Source 1000pF PI SAW Filter 50Ω 400Ω PO = 12dB − (SAW Loss) PI 3 G = +1, Figure 1 WIDEBAND UNITY GAIN BUFFER WITH IMPROVED FLATNESS The unity gain buffer configuration of Figure 1 shows a peaking in the frequency response exceeding 2dB. This gives the slight amount of overshoot and ringing apparent in the gain of +1V/V pulse response curves. A similar circuit that holds a flatter frequency response, giving improved pulse fidelity, is shown in Figure 6. Normalized Gain (dB) 0 Figure 5. IF Amplifier Driving SAW Filter −3 G = +1, Figure 6 −6 −9 −12 10M 100M 1G Frequency (MHz) Figure 7. IF Amplifier Driving SAW Filter 12 3G "#$ www.ti.com SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004 DESIGN-IN TOOLS VI DEMONSTRATION BOARDS α Two PC boards are available to assist in the initial evaluation of circuit performance using the OPA694 in its two package styles. Both are available free, as unpopulated PC boards delivered with descriptive documentation. The summary information for these boards is shown in Table 1. VO RI Z(S) iERR iERR RF RG Table 1. Demo Board Listing LITERATURE REQUEST NUMBER PRODUCT PACKAGE BOARD PART NUMBER OPA694ID SO-8 DEM-OPA84xD SBOU026 OPA694IDBV SOT23-5 DEM-OPA84xDBV SBOU027 To request either of these boards, use the Texas Instruments web site (www.ti.com). MACROMODELS AND APPLICATIONS SUPPORT Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA694 is available through the TI web site (www.ti.com). These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion or dG/dφ characteristics. These models do not attempt to distinguish between package types in their small-signal AC performance. OPERATING SUGGESTIONS SETTING RESISTOR VALUES TO OPTIMIZE BANDWIDTH A current-feedback op amp like the OPA694 can hold an almost constant bandwidth over signal gain settings with the proper adjustment of the external resistor values. This is shown in the Typical Characteristic curves; the small-signal bandwidth decreases only slightly with increasing gain. Those curves also show that the feedback resistor has been changed for each gain setting. The resistor values on the inverting side of the circuit for a current-feedback op amp can be treated as frequency response compensation elements while their ratios set the signal gain. Figure 8 shows the small-signal frequency response analysis circuit for the OPA694. Figure 8. Recommended Feedback Resistor Versus Noise Gain The key elements of this current-feedback op amp model are: α → Buffer gain from the noninverting input to the inverting input RI → Buffer output impedance iERR → Feedback error current signal Z(s) → Frequency dependent open-loop transimpedance gain from iERR to VO The buffer gain is typically very close to 1.00 and is normally neglected from signal gain considerations. It will, however, set the CMRR for a single op amp differential amplifier configuration. For a buffer gain α < 1.0, the CMRR = –20 × log (1– α) dB. RI, the buffer output impedance, is a critical portion of the bandwidth control equation. RI for the OPA694 is typically about 30Ω. A current-feedback op amp senses an error current in the inverting node (as opposed to a differential input error voltage for a voltage-feedback op amp) and passes this on to the output through an internal frequency dependent transimpedance gain. The Typical Characteristics show this open-loop transimpedance response. This is analogous to the open-loop voltage gain curve for a voltage-feedback op amp. Developing the transfer function for the circuit of Figure 8 gives Equation (1): ǒ Ǔ RF RG a 1) VO + VI 1) ǒ Ǔ R R F)RI 1) F RG Z (S) + aNG R )R I NG 1) F Z (S) (1) where: ǒ NG + 1 ) Ǔ RF RG 13 "#$ www.ti.com SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004 Z (S) + Loop Gain R F ) R I NG (2) If 20 × log(RF + NG × RI) were drawn on top of the open-loop transimpedance plot, the difference between the two would be the loop gain at a given frequency. Eventually, Z(S) rolls off to equal the denominator of Equation (2), at which point the loop gain reduces to 1 (and the curves intersect). This point of equality is where the amplifier closed-loop frequency response given by Equation (1) starts to roll off, and is exactly analogous to the frequency at which the noise gain equals the open-loop voltage gain for a voltage-feedback op amp. The difference here is that the total impedance in the denominator of Equation (2) may be controlled somewhat separately from the desired signal gain (or NG). The OPA694 is internally compensated to give a maximally flat frequency response for RF = 402Ω at NG = 2 on ±5V supplies. Evaluating the denominator of Equation (2) (which is the feedback transimpedance) gives an optimal target of 462Ω. As the signal gain changes, the contribution of the NG × RI term in the feedback transimpedance will change, but the total can be held constant by adjusting RF. Equation (3) gives an approximate equation for optimum RF over signal gain: R F + 462W * NG @ RI (3) As the desired signal gain increases, this equation will eventually predict a negative RF. A somewhat subjective limit to this adjustment can also be set by holding RG to a minimum value of 20Ω. Lower values will load both the buffer stage at the input and the output stage, if RF gets too low, actually decreasing the bandwidth. Figure 9 shows the recommended RF versus NG for ±5V operation. The values for RF versus gain shown here are approximately equal to the values used to generate the Typical Characteristics. They differ in that the optimized values used in the Typical Characteristics are also correcting for board parasitics not considered in the simplified analysis leading to Equation (2). The values shown in Figure 9 give a good starting point for design where bandwidth optimization is desired. 14 450 400 Feedback Resistor (Ω ) This is written in a loop-gain analysis format, where the errors arising from a noninfinite open-loop gain are shown in the denominator. If Z(S) were infinite over all frequencies, the denominator of Equation (1) would reduce to 1 and the ideal desired signal gain shown in the numerator would be achieved. The fraction in the denominator of Equation (1) determines the frequency response. Equation (2) shows this as the loop-gain equation: 350 300 250 200 150 0 5 10 15 20 Noise Gain Figure 9. Feedback Resistor vs Noise Gain The total impedance going into the inverting input may be used to adjust the closed-loop signal bandwidth. Inserting a series resistor between the inverting input and the summing junction will increase the feedback impedance (denominator of Equation (1)), decreasing the bandwidth. This approach to bandwidth control is used for the inverting summing circuit on the front page. The internal buffer output impedance for the OPA694 is slightly influenced by the source impedance looking out of the noninverting input terminal. High source resistors will have the effect of increasing RI, decreasing the bandwidth. OUTPUT CURRENT AND VOLTAGE The OPA694 provides output voltage and current capabilities that are not usually found in wideband amplifiers. Under no-load conditions at 25°C, the output voltage typically swings closer than 1.2V to either supply rail; the +25°C swing limit is within 1.2V of either rail. Into a 15Ω load (the minimum tested load), it is tested to deliver more than ±60mA. The specifications described above, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the voltage × current, or V−I product, which is more relevant to circuit operation. Refer to the Output Voltage and Current Limitations plot in the Typical Characteristics. The X and Y axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the OPA694 output drive capabilities, noting that the graph is bounded by a Safe Operating Area of 1W maximum internal power "#$ www.ti.com SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004 dissipation. Superimposing resistor load lines onto the plot shows that the OPA694 can drive ±2.5V into 25Ω or ±3.5V into 50Ω without exceeding the output capabilities or the 1W dissipation limit. A 100Ω load line (the standard test circuit load) shows the full ±3.4V output swing capability, as shown in the Electrical Charateristics. The minimum specified output voltage and current over-temperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup will the output current and voltage decrease to the numbers shown in the Electrical Characteristic tables. As the output transistors deliver power, the junction temperatures will increase, decreasing both VBE (increasing the available output voltage swing) and increasing the current gains (increasing the available output current). In steady-state operation, the available output voltage and current will always be greater than that shown in the over-temperature specifications, since the output stage junction temperatures will be higher than the minimum specified operating ambient. DRIVING CAPACITIVE LOADS One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADC—including additional external capacitance that may be recommended to improve ADC linearity. A high-speed, high open-loop gain amplifier like the OPA694 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier open−loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the recommended RS vs Capacitive Load and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA694. Long PC-board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA694 output pin (see the Board Layout Guidelines section). DISTORTION PERFORMANCE The OPA694 provides good distortion performance into a 100Ω load on ±5V supplies. Generally, until the fundamental signal reaches very high frequency or power levels, the 2nd-harmonic will dominate the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network—in the noninverting configuration (see Figure 1), this is the sum of RF + RG, while in the inverting configuration it is just RF. Also, providing an additional supply decoupling capacitor (0.1µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB). In most op amps, increasing the output voltage swing increases harmonic distortion directly. The Typical Characteristics show the 2nd-harmonic increasing at a little less than the expected 2x rate, while the 3rd-harmonic increases at a little less than the expected 3x rate. Where the test power doubles, the 2nd-harmonic increases by less than the expected 6dB, while the 3rd-harmonic increases by less than the expected 12dB. This also shows up in the 2-tone, 3rd-order intermodulation spurious (IM3) response curves. The 3rd-order spurious levels are extremely low at low output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Characteristics show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. 15 "#$ www.ti.com SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004 NOISE PERFORMANCE Wideband, current-feedback op amps generally have a higher output noise than comparable voltage-feedback op amps. The OPA694 offers an excellent balance between voltage and current noise terms to achieve low output noise. The inverting current noise (24pA/√Hz) is significantly lower than earlier solutions, while the input voltage noise (2.1nV/√Hz) is lower than most unity-gain stable, wideband, voltage-feedback op amps. This low input voltage noise was achieved at the price of higher noninverting input current noise (22pA/√Hz). As long as the AC source impedance looking out of the noninverting node is less than 100Ω, this current noise will not contribute significantly to the total output noise. The op amp input voltage noise and the two input current noise terms combine to give low output noise under a wide variety of operating conditions. Figure 10 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. ENI EO OPA694 RS IBN ERS RF √4kTRS 4kT RG √4kTRF IBI RG 4kT = 1.6 × 10−20 J at 290K 2 ENI ) ǒI BNRSǓ ) 4kTRS 2 Ǔ = ± (2 × 3mV) ± (20µA × 25Ω × 2) ± (402Ω × 18µA) 2 NG2 ) ǒI BIRFǓ ) 4kTRFNG (4) Dividing this expression by the noise gain (NG = (1 + RF/RG)) will give the equivalent input-referred spot noise voltage at the noninverting input, as shown in Equation 6. EN + 16 Ǹ ENI ) ǒI BNR SǓ ) 4kTR S ) 2 2 ǒ Ǔ I BIR F NG 2 ) 4kTR F NG A current-feedback op amp like the OPA694 provides exceptional bandwidth in high gains, giving fast pulse settling, but only moderate DC accuracy. The Electrical Characteristics show an input offset voltage comparable to high-speed, voltage-feedback amplifiers. However, the two input bias currents are somewhat higher and are unmatched. Whereas bias current cancellation techniques are very effective with most voltage-feedback op amps, they do not generally reduce the output DC offset for wideband, current-feedback op amps. Since the two input bias currents are unrelated in both magnitude and polarity, matching the source impedance looking out of each input to reduce their error contribution to the output is ineffective. Evaluating the configuration of Figure 1, using worst-case +25°C input offset voltage and the two input bias currents, gives a worst-case output offset range equal to: where NG = noninverting signal gain The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation (4) shows the general form for the output noise voltage using the terms shown in Figure 10. Ǹǒ DC ACCURACY AND OFFSET CONTROL ± (NG × VOS) ± (IBN × RS/2 × NG) ± (IBI × RF) Figure 10. Op Amp Noise Analysis Model EO + Evaluating these two equations for the OPA694 circuit and component values (see Figure 1) gives a total output spot noise voltage of 11.2nV/√Hz and a total equivalent input spot noise voltage of 5.6nV/√Hz. This total input-referred spot noise voltage is higher than the 2.1nV/√Hz specification for the op amp voltage noise alone. This reflects the noise added to the output by the inverting current noise times the feedback resistor. If the feedback resistor is reduced in high-gain configurations (as suggested previously), the total input-referred voltage noise given by Equation (5) will approach just the 2.1nV/√Hz of the op amp itself. For example, going to a gain of +10 using RF = 178Ω will give a total input-referred noise of 2.36nV/√Hz. (5) = ±6mV + 1mV ± 7.24mV = ±14.24mV A fine-scale, output offset null, or DC operating point adjustment, is sometimes required. Numerous techniques are available for introducing DC offset control into an op amp circuit. Most simple adjustment techniques do not correct for temperature drift. It is possible to combine a lower speed, precision op amp with the OPA694 to get the DC accuracy of the precision op amp along with the signal bandwidth of the OPA694. Figure 11 shows a noninverting G = +10 circuit that holds an output offset voltage less than ±7.5mV over-temperature with > 150MHz signal bandwidth. "#$ www.ti.com SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004 THERMAL ANALYSIS Power−supply decoupling not shown. +5V DIS VI OPA694 VO 1.8kΩ +5V 2.86kΩ −5V 180Ω OPA237 20Ω −5V 18kΩ 2kΩ Figure 11. Wideband, DC-Connected Composite Circuit This DC-coupled circuit provides very high signal bandwidth using the OPA694. At lower frequencies, the output voltage is attenuated by the signal gain and compared to the original input voltage at the inputs of the OPA237 (this is a low-cost, precision voltage-feedback op amp with 1.5MHz gain bandwidth product). If these two do not agree (due to DC offsets introduced by the OPA694), the OPA237 sums in a correction current through the 2.86kΩ inverting summing path. Several design considerations will allow this circuit to be optimized. First, the feedback to the OPA237 noninverting input must be precisely matched to the high-speed signal gain. Making the 2kΩ resistor to ground an adjustable resistor would allow the low- and high-frequency gains to be precisely matched. Second, the crossover frequency region where the OPA237 passes control to the OPA694 must occur with exceptional phase linearity. These two issues reduce to designing for pole/zero cancellation in the overall transfer function. Using the 2.86kΩ resistor will nominally satisfy this requirement for the circuit in Figure 11. Perfect cancellation over process and temperature is not possible. However, this initial resistor setting and precise gain matching will minimize long-term pulse settling tails. Due to the high output power capability of the OPA694, heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature will set the maximum allowed internal power dissipation, as described below. In no case should the maximum junction temperature be allowed to exceed 150°C. Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). Under this condition PDL = VS2/(4 × RL) where RL includes feedback network loading. Note that it is the power in the output stage and not in the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA694IDBV (SOT23-5 package) in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C and driving a grounded 20Ω load to +2.5V DC: PD = 10V × 6.0mA + 52/(4 × (20Ω || 804Ω)) = 380mΩ Maximum TJ = +85°C + (0.38W × (150°C/W) = 142°C Although this is still below the specified maximum junction temperature, system reliability considerations may require lower junction temperatures. Remember, this is a worst-case internal power dissipation—use your actual signal and load to compute PDL. The highest possible internal dissipation will occur if the load requires current to be forced into the output for positive output voltages or sourced from the output for negative output voltages. This puts a high current through a large internal voltage drop in the output transistors. The Output Voltage and Current Limitations plot shown in the Typical Characteristics includes a boundary for 1W maximum internal power dissipation under these conditions. 17 "#$ www.ti.com SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004 BOARD LAYOUT GUIDELINES Achieving optimum performance with a high-frequency amplifier like the OPA694 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25”) from the power-supply pins to high-frequency 0.1µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections (on pins 4 and 7) should always be decoupled with these capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) will improve 2nd-harmonic distortion performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequencies, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high-frequency performance of the OPA694. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high-frequency performance. Again, keep their leads and PC-board trace length as short as possible. Never use wirewound type resistors in a high-frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. The frequency response is primarily determined by the feedback resistor value, as described previously. Increasing its value will reduce the bandwidth, while decreasing it will give a more peaked frequency response. The 402Ω feedback resistor used in the Electrical 18 Characteristic tables at a gain of +2 on ±5V supplies is a good starting point for design. Note that a 430Ω feedback resistor, rather than a direct short, is recommended for the unity-gain follower application. A current-feedback op amp requires a feedback resistor even in the unity-gain follower configuration to control stability. d) Connections to other wideband devices on the board may be made with short, direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of Recommended RS vs Capacitive Load. Low parasitic capacitive loads (< 5pF) may not need an RS, since the OPA694 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary onboard, and in fact, a higher impedance environment will improve distortion, as shown in the Distortion versus Load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA694 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the OPA694 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of Recommended RS vs Capacitive Load. This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high-speed part like the OPA694 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA694 onto the board. "#$ www.ti.com SBOS319C − SEPTEMBER 2004 − REVISED NOVEMBER 2004 INPUT AND ESD PROTECTION The OPA694 is built using a very high speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins have limited ESD protection using internal diodes to the power supplies, as shown in Figure 12. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (for example, in systems with ±15V supply parts driving into the OPA694), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible, since high values degrade both noise performance and frequency response. +VCC External Pin Internal Circuitry −VCC Figure 12. Internal ESD Protection 19 PACKAGE OPTION ADDENDUM www.ti.com 21−Sep−2004 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY ECO−STATUS(2) OPA694ID OPA694IDR OPA694DBVR ACTIVE SO−8 D 8 100 N/A OPA694DBVT ACTIVE SO−8 D 8 2500 N/A ACTIVE SOT23 DBV 5 250 ACTIVE SOT23 DBV 5 3000 Pb−Free, Green Pb−Free, Green (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime−buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco−Status information Additional details including specific material content can be accessed at www.ti.com/leadfree GREEN: Ti defines Green to mean Lead (Pb)−Free and in addition, uses less package materials that do not contain halogens, including bromine (Br), or antimony (Sb) above 0.1% of total product weight. N/A: Not yet available Lead (Pb)−Free; for estimated conversion dates, go to www.ti.com/leadfree. Pb−FREE: Ti defines Lead (Pb)−Free to mean RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and, if designed to be soldered, suitable for use in specified lead−free soldering processes. PACKAGE OPTION ADDENDUM www.ti.com 18-Jan-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty None Lead/Ball Finish MSL Peak Temp (3) OPA694ID ACTIVE SOIC D 8 100 CU SNPB Level-3-260C-168 HR OPA694IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA694IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OPA694IDR ACTIVE SOIC D 8 2500 None CU SNPB Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated