TPS73534 SBVS164 – JUNE 2011 www.ti.com 500mA, Low-Dropout Voltage Regulator for C2000™ Check for Samples: TPS73534 FEATURES The device also has superior noise and PSRR performance to supply noise sensitive circuit blocks. 1 • • • • • • • • • • 23 Optimal Output Voltage for I/O Rail of C2000 Good Line/Load Transient Response for MCUs 500mA LDO Voltage Regulator with Enable Low IQ: 46μA Low Shutdown Current: 1μA Stable with 2μF Ceramic Capacitor Good PSRR: 60dB at 1kHz Low Noise: 28μVRMS 2% Overall Accuracy (Load/Line/Temp) 8-Pin 3x3mm SON In combination with a voltage supervisor such as the TPS3808G01, the TPS73534 can deliver tight VIO voltages and generate accurate power-good signals that meet or exceed power requirements for the C2000. The TPS73534 is fully specified from TJ = –40°C to +125°C and is offered in a 3mm x 3mm SON package. DRB PACKAGE 3mm x 3mm SON (TOP VIEW) APPLICATIONS • OUT 1 C2000 I/O Power Rail Supply space N/C 2 NR/FB 3 8 IN 7 N/C GND 6 N/C 5 EN GND 4 DESCRIPTION The TPS73534 low-dropout (LDO) voltage regulator is optimized for use with TI's C2000 controller family to meet the I/O power rail tolerance requirement. The device offers very good line and load transient response, even with very low quiescent current of 46μA. 1.8 V 3.3 V 10 kW TPS3808G01 or TPS3808G19 TPS73219 or TPS73619 OUT EN LDO 1.8 V SENSE 51 kW 15 kW RESET SVS 1.8 V 10 kW C2000 TPS73534 or TPS73734 TPS3808G01 OUT EN LDO 3.3 V SENSE 91 kW RESET XRS SVS 3.3 V 13 kW Figure 1. Typical Application 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. C2000 is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated TPS73534 SBVS164 – JUNE 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT TPS735xx yyy z (1) (2) VOUT (2) XX is nominal output voltage (for example, 28 = 2.8V, 285 = 2.85V, 01 = Adjustable). YYY is package designator. Z is package quantity. For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Output voltages from 1.0V to 3.6V in 50mV increments are available through the use of innovative factory EEPROM programming; minimum order quantities may apply. Contact factory for details and availability. ABSOLUTE MAXIMUM RATINGS Over operating temperature range (unless otherwise noted). (1) PARAMETER TPS73534 UNIT VIN range –0.3 to +7.0 V VEN range –0.3 to VIN +0.3 V VOUT range –0.3 to VIN +0.3 V –0.3 to VFB (TYP) +0.3 V VFB range Peak output current Continuous total power dissipation Internally limited See Thermal Information table Junction temperature range, TJ –55 to +150 Storage temperature range , TSTG °C –55 to +150 °C ESD rating, HBM 2 kV ESD rating, CDM 500 V (1) 2 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Copyright © 2011, Texas Instruments Incorporated TPS73534 SBVS164 – JUNE 2011 www.ti.com THERMAL INFORMATION TPS73534 (2) THERMAL METRIC (1) DRB UNITS 8 PINS Junction-to-ambient thermal resistance (3) θJA (4) 47.8 θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (5) N/A ψJT Junction-to-top characterization parameter (6) 2.1 ψJB Junction-to-board characterization parameter (7) 17.8 θJCbot Junction-to-case (bottom) thermal resistance (8) 12.1 (1) (2) (3) (4) (5) (6) (7) (8) 83 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A. Thermal data for the DRB package is derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array. (b) The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage. (c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature sections of this data sheet. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Copyright © 2011, Texas Instruments Incorporated 3 TPS73534 SBVS164 – JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS Over operating temperature range (TJ = –40°C to +125°C), VIN = 3.9V; IOUT = 1mA, VEN = VIN, COUT = 2.2μF, CNR = 0.01μF, unless otherwise noted. Typical values are at TJ = +25°C. PARAMETER VIN VOUT VOUT % –2.0 Dropout voltage (VIN = VOUT(NOM) – 0.1V) IOUT = 500mA ICL Output current limit VOUT = 0.9 × VOUT(NOM) VIN = VOUT(NOM) + 0.9V, VIN ≥ 2.7V IGND Ground pin current 500μA ≤ IOUT ≤ 500mA ISHDN Shutdown current (IGND) VEN ≤ 0.4V Power-supply rejection ratio VIN = 3.85V, VOUT = 2.85V, CNR = 0.01μF, IOUT = 100mA Output noise voltage BW = 10Hz to 100kHz, VOUT = 2.8V Startup time, VOUT= 0% to 90% VOUT = 2.85V, RL = 14Ω, COUT = 2.2μF VEN(HI) Enable high (enabled) VEN(LO) Enable low (shutdown) Enable pin current, enabled TSD Thermal shutdown temperature TJ Operating junction temperature UVLO +2.0 VOUT + 0.3V ≤ VIN ≤ VOUT > 6.5V 1mA ≤ IOUT ≤ 500mA, VOUT > 2.2V VDO IEN(HI) % Output accuracy 500μA ≤ IOUT ≤ 500mA TSTR +1.0 –1.0 VOUT(NOM) + 0.3V ≤ VIN ≤ 6.5V UNIT V TJ = +25°C Load regulation MAX 6.5 DRB package over VIN, IOUT, Temp Line regulation TYP 3.9 Nominal ΔVOUT%/ ΔVIN VN MIN Output accuracy ΔVOUT%/ ΔIOUT PSRR 4 TEST CONDITIONS Input voltage range 800 ±1.0 0.02 %/V 0.005 %/mA 280 500 mV 1170 1720 mA 45 65 μA 0.15 1.0 μA f = 100Hz 60 dB f = 1kHz 56 dB f = 10kHz 41 dB f = 100kHz 28 dB CNR = 0.01μF 11 x VOUT μVRMS CNR = none 95 x VOUT μVRMS CNR = none 45 μs CNR = 0.001μF 45 μs CNR = 0.01μF 50 μs CNR = 0.047μF 50 1.2 0 VEN = VIN = 6.5V 0.03 Shutdown, temperature increasing 165 Reset, temperature decreasing VIN rising Hysteresis VIN falling 1.90 2.20 70 V 0.4 V 1.0 μA °C °C 145 –40 Under-voltage lock-out μs VIN +125 °C 2.65 V mV Copyright © 2011, Texas Instruments Incorporated TPS73534 SBVS164 – JUNE 2011 www.ti.com DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAM IN OUT 400W 2mA Current Limit Thermal Shutdown EN Overshoot Detect UVLO Quickstart 1.208V (1) Bandgap NR 500kW GND NOTE (1): Fixed voltage versions between 1.0V to 1.2V have a 1.0V bandgap circuit instead of a 1.208V bandgap circuit. Figure 2. Fixed Voltage Version PIN CONFIGURATION DRB PACKAGE 3mm × 3mm SON-6 (TOP VIEW) OUT 1 N/C 2 NR/FB 3 GND 4 8 IN 7 N/C GND 6 N/C 5 EN PIN DESCRIPTIONS TPS73534 NAME DRB DESCRIPTION IN 8 Input supply. GND 4 Ground. The pad must be tied to GND. EN 5 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. EN can be connected to IN if not used. NR 3 Fixed voltage versions only; connecting an external capacitor to this pin bypasses noise generated by the internal bandgap. This allows output noise to be reduced to very low levels. FB 3 Adjustable version only; this is the input to the control loop error amplifier, and is used to set the output voltage of the device. OUT 1 Output of the regulator. A small capacitor (total typical capacitance ≥ 2.0μF ceramic) is needed from this pin to ground to assure stability. N/C 2, 6, 7 Not internally connected. This pin must either be left open, or tied to GND. Copyright © 2011, Texas Instruments Incorporated 5 TPS73534 SBVS164 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS Over operating temperature range (TJ= –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater; IOUT = 1mA, VEN = VIN,COUT = 2.2μF, CNR = 0.01μF, unless otherwise noted. Typical values are at TJ = +25°C. TPS73501 LINE REGULATION 0.5 IOUT = 100mA 0.3 TJ = -40°C 0.2 TJ = 0°C 0.1 0 -0.1 TJ = +25°C -0.2 TJ = +85°C -0.3 0.3 0.1 0 -0.1 -0.2 TJ = +85°C -0.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 3.0 6.5 3.5 4.0 4.5 2.86 5.5 6.0 Figure 3. Figure 4. TPS73501 LOAD REGULATION TPS73525 LOAD REGULATION 2.55 Y-axis range is ±2% of 2.8V 2.85 5.0 6.5 VIN (V) VIN (V) Y-axis range is ±2% of 2.5V 2.54 2.84 2.53 2.83 TJ = -40°C 2.81 2.80 2.79 VOUT (V) 2.52 2.82 VOUT (V) TJ = +25°C TJ = +125°C -0.4 -0.5 TJ = +85°C 2.78 2.77 2.51 2.47 2.46 2.74 2.45 50 TJ = -40°C 2.49 2.75 0 TJ = 0°C 2.50 2.48 TJ = +125°C 2.76 TJ = +25°C TJ = +125°C 0 100 150 200 250 300 350 400 450 500 50 TJ = +85°C 100 150 200 250 300 350 400 450 500 Load (mA) Load (mA) Figure 5. Figure 6. TPS73525 GROUND PIN CURRENT vs OUTPUT CURRENT TPS73525 GROUND PIN CURRENT (DISABLE) vs TEMPERATURE 60 TJ = +25°C 50 500 TJ = +125°C VEN = 0.4V 450 TJ = +85°C 400 350 TJ = -40°C 30 TJ = 0°C 20 IGND (na) 40 IGND (mA) TJ = 0°C TJ = -40°C 0.2 -0.3 TJ = +125°C -0.4 IOUT = 100mA 0.4 Change in VOUT (%) 0.4 Change in VOUT (%) TPS73525 LINE REGULATION 0.5 300 250 VIN = 3.3V 200 VIN = 5.0V 150 VIN = 6.5V 100 10 50 0 0 0 50 100 150 200 250 300 350 400 450 500 IOUT (mA) Figure 7. 6 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ (°C) Figure 8. Copyright © 2011, Texas Instruments Incorporated TPS73534 SBVS164 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ= –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater; IOUT = 1mA, VEN = VIN,COUT = 2.2μF, CNR = 0.01μF, unless otherwise noted. Typical values are at TJ = +25°C. TPS73501 DROPOUT VOLTAGE vs OUTPUT CURRENT POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (VIN – VOUT = 1.0V) 90 400 TJ = +125°C 350 200 TJ = 0°C 150 PSRR (dB) TJ = +25°C 250 IOUT = 100mA 50 40 IOUT = 500mA 20 50 10 0 0 0 50 COUT = 2.2mF CNR = 0.01mF 10 100 150 200 250 300 350 400 450 500 100 IOUT = 200mA 10k 1k 100k 10M 1M IOUT (mA) Frequency (Hz) Figure 9. Figure 10. POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (VIN – VOUT = 0.5V) POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (VIN – VOUT = 0.3V) 90 90 80 80 IOUT = 1mA 70 60 IOUT = 100mA 50 40 0 IOUT = 200mA 60 IOUT = 100mA 50 40 30 20 10 IOUT = 1mA 70 IOUT = 200mA 30 20 COUT = 2.2mF CNR = 0.01mF 10 100 IOUT = 500mA IOUT = 250mA 10k 1k 10 0 100k 1M 10M COUT = 10mF CNR = 0.01mF 10 100 IOUT = 200mA IOUT = 500mA 10k 1k 100k Frequency (Hz) Frequency (Hz) Figure 11. Figure 12. TPS73525 TOTAL NOISE vs CNR TPS73525 TOTAL NOISE vs COUT 140 Total Noise (mVRMS) 80 60 40 20 15 10 5 20 IOUT = 1mA CNR = 0.01mF 0 0 0.1 1 10 0 5 10 15 CNR (nF) COUT (mF) Figure 13. Figure 14. Copyright © 2011, Texas Instruments Incorporated 10M 25 100 0.01 1M 30 IOUT = 1mA COUT = 2.2mF 120 Total Noise (mVRMS) IOUT = 250mA 60 30 TJ = -40°C 100 IOUT = 1mA 70 PSRR (dB) VDO (mV) 300 PSRR (dB) 80 TJ = +85°C 20 25 7 TPS73534 SBVS164 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ= –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater; IOUT = 1mA, VEN = VIN,COUT = 2.2μF, CNR = 0.01μF, unless otherwise noted. Typical values are at TJ = +25°C. TPS73525 TURN-ON RESPONSE (VIN = VEN) TPS73525 EN RESPONSE OVER STABLE VIN 3.5 3.5 3.0 COUT = 2.2mF 3.0 VOUT 2.5 2.0 1.5 COUT = 10mF 1.0 VOUT 2.0 1.5 1.0 0.5 0.5 0 0 -0.5 COUT = 10mF -0.5 10ms/div 10ms/div Figure 15. Figure 16. TPS73525 POWER-UP/POWER-DOWN (VIN = VEN) TPS73525 LOAD TRANSIENT RESPONSE 7.0 RL = 5W 6.0 VIN = 3.0V COUT = 470mF OSCON 200mV/div COUT = 10mF VIN = EN VOUT 200mV/div 5.0 Volts (V) VEN COUT = 2.2mF Voltage (V) Voltage (V) 2.5 VEN VOUT 4.0 COUT = 2.2mF 200mV/div 3.0 2.0 VOUT 1.0 500mA 0 500mA/div IOUT 1mA -1.0 10ms/div 10ms/div Figure 17. Figure 18. TPS73525 LINE TRANSIENT RESPONSE COUT = 470mF OSCON 50mV/div COUT =V10 mF OUT 50mV/div COUT = 2.2mF 50mV/div VOUT VOUT VOUT 4V 0.5V/div 3V VIN 10ms/div Figure 19. 8 Copyright © 2011, Texas Instruments Incorporated TPS73534 SBVS164 – JUNE 2011 www.ti.com APPLICATION INFORMATION The TPS73534 LDO regulators combines the high performance required of many RF and precision analog applications with ultra-low current consumption. High PSRR is provided by a high gain, high bandwidth error loop with good supply rejection at very low headroom (VIN – VOUT). Fixed voltage versions provide a noise reduction pin to bypass noise generated by the bandgap reference and to improve PSRR while a quick-start circuit fast-charges this capacitor at startup. The combination of high performance and low ground current also make the TPS73534 an excellent choice for portable applications. All versions have thermal and over-current protection and are fully specified from –40°C to +125°C. Figure 20 shows the basic circuit connections for fixed voltage models. R1 and R2 can be calculated for any output voltage using the formula in . Optional input capacitor. May improve source impedance, noise, or PSRR. VIN IN EN VEN VOUT OUT TPS735xx GND NR 2.2mF Ceramic Optional bypass capacitor to reduce output noise and increase PSRR. Figure 20. Typical Application Circuit for Fixed Voltage Versions Input and Output Capacitor Requirements Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1μF to 1μF low equivalent series resistance (ESR) capacitor across the input supply near the regulator. The ground of this capacitor should be connected as close as the ground of output capacitor; a capacitor value of 0.1μF is enough in this condition. When it is difficult to place these two ground points close together, a 1μF capacitor is recommended. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is located several inches from the power source. If source impedance is not sufficiently low, a 0.1μF input capacitor may be necessary to ensure stability. The TPS73534 is designed to be stable with standard ceramic output capacitors of values 2.2μF or larger. Copyright © 2011, Texas Instruments Incorporated X5R and X7R type capacitors are best because they have minimal variation in value and ESR over temperature. Maximum ESR of the output capacitor should be < 1.0Ω, so output capacitor type should be either ceramic or conductive polymer electrolytic. Output Noise In most LDOs, the bandgap is the dominant noise source. If a noise reduction capacitor (CNR) is used with the TPS73534, the bandgap does not contribute significantly to noise. Instead, noise is dominated by the output resistor divider and the error amplifier input. To minimize noise in a given application, use a 0.01μF noise reduction capacitor; for the adjustable version, smaller value resistors in the output resistor divider reduce noise. A parallel combination that gives 2μA of divider current has the same noise performance as a fixed voltage version. To further optimize noise, equivalent series resistance of the output capacitor can be set to approximately 0.2Ω. This configuration maximizes phase margin in the control loop, reducing total output noise by up to 10%. Noise can be referred to the feedback point (FB pin) such that with CNR = 0.01μF, total noise is given approximately by Equation 1: 11mVRMS VN = x VOUT V (1) Board Layout Recommendations to Improve PSRR and Noise Performance To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of the device. Internal Current Limit The TPS73534 internal current limit helps protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, the device should not be operated in current limit for extended periods of time. The PMOS pass element in the TPS73534 has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting may be appropriate. 9 TPS73534 SBVS164 – JUNE 2011 www.ti.com Shutdown Transient Response The enable pin (EN) is active high and is compatible with standard and low voltage TTL-CMOS levels. When shutdown capability is not required, EN can be connected to IN. As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but increases duration of the transient response. In the adjustable version, adding CFB between OUT and FB improves stability and transient response. The transient response of the TPS73534 is enhanced by an active pull-down that engages when the output overshoots by approximately 5% or more when the device is enabled. When enabled, the pull-down device behaves like a 400Ω resistor to ground. Dropout Voltage The TPS73534 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in its linear region of operation and the input-to-output resistance is the RDS, ON of the PMOS pass element. Because the PMOS device behaves like a resistor in dropout, VDO approximately scales with output current. As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in the Typical Characteristics section. Startup and Noise Reduction Capacitor The TPS73534 uses a quick-start circuit to fast-charge the noise reduction capacitor, CNR, if present (see the Functional Block Diagrams). This architecture allows the combination of very low output noise and fast start-up times. The NR pin is high impedance so a low leakage CNR capacitor must be used; most ceramic capacitors are appropriate in this configuration. Note that for fastest startup, VIN should be applied first, then the enable pin (EN) driven high. If EN is tied to IN, startup is somewhat slower. Refer to the Typical Characteristics section. The quick-start switch is closed for approximately 135μs. To ensure that CNR is fully charged during the quick-start time, a 0.01μF or smaller capacitor should be used. 10 Undervoltage Lock-Out (UVLO) The TPS73534 utilizes an undervoltage lock-out circuit to keep the output shut off until internal circuitry is operating properly. The UVLO circuit has a de-glitch feature so that it typically ignores undershoot transients on the input if they are less than 50μs duration. Minimum Load The TPS73534 is stable and well-behaved with no output load. To meet the specified accuracy, a minimum load of 500μA is required. Below 500μA at junction temperatures near +125°C, the output can drift up enough to cause the output pull-down to turn on. The output pull-down limits voltage drift to 5% typically but ground current could increase by approximately 50μA. In typical applications, the junction cannot reach high temperatures at light loads because there is no appreciable dissipated power. The specified ground current would then be valid at no load in most applications. Copyright © 2011, Texas Instruments Incorporated TPS73534 SBVS164 – JUNE 2011 www.ti.com Thermal Information Thermal Protection Thermal protection disables the output when the junction temperature rises to approximately +165°C, allowing the device to cool. When the junction temperature cools to approximately +145°C the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +35°C above the maximum expected ambient condition of your particular application. This configuration produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS73534 has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS73534 into thermal shutdown degrades device reliability. Note: When the device is used in a condition of higher input and lower output voltages with the DRV and DRB packages, PD exceeds the package rating at room temperature. This equation shows an example of the DRB package: PD = (6.5V – 1.0V) × 500mA = 2.75W, which is greater than 2.5W at +25°C. Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation. On both SON (DRB) and SON (DRV) packages, the primary conduction path for heat is through the exposed pad to the printed circuit board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be calculated using Equation 3: ()125OC * T A) R qJA + PD (3) Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking can be estimated using Figure 21. 160 DRV DRB 140 Package Mounting Power Dissipation The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the Thermal Information table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation is equal to the product of the output current time the voltage drop across the output pass element, as shown in Equation 2: P D + ǒVIN*V OUTǓ @ I OUT (2) Copyright © 2011, Texas Instruments Incorporated qJA (°C/W) Solder pad footprint recommendations for the TPS73534 are available from the Texas Instruments web site at www.ti.com. 120 100 80 60 40 20 0 0 Note: 1 2 4 5 7 3 6 Board Copper Area (in2) 8 9 10 θJA value at board size of 9in2 (that is, 3in × 3in) is a JEDEC standard. Figure 21. θJA vs Board Size Figure 21 shows the variation of θJA as a function of ground plane copper area in the board. It is intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate actual thermal performance in real application environments. 11 TPS73534 SBVS164 – JUNE 2011 www.ti.com NOTE: When the device is mounted on an application PCB, it is strongly recommended to use ΨJT and ΨJB, as explained in the Estimating Junction Temperature section. By looking at Figure 22, the new thermal metrics (ΨJT and ΨJB) have very little dependency on board size. That is, using ΨJT or ΨJB with Equation 4 is a good way to estimate TJ by simply measuring TT or TB, regardless of the application board size. ESTIMATING JUNCTION TEMPERATURE YJB: TJ = TB + YJB · PD (4) 35 30 YJT and YJB (°C/W) Using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 4). For backwards compatibility, an older θJC,Top parameter is listed as well. YJT: TJ = TT + YJT · PD 25 DRV Y JB DRB 20 15 10 DRV Y JT DRB Where PD is the power dissipation shown by Equation 2, TT is the temperature at the center-top of the IC package, and TB is the PCB temperature measured 1mm away from the IC package on the PCB surface (as Figure 23 shows). 5 NOTE: Both TT and TB can be measured on actual application boards using a thermo-gun (an infrared thermometer). Figure 22. ΨJT and ΨJB vs Board Size For more information about measuring TT and TB, see the application note SBVA025, Using New Thermal Metrics, available for download at www.ti.com. 0 0 1 3 2 5 6 7 8 9 10 For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics, refer to application report SBVA025, Using New Thermal Metrics, available for download at www.ti.com. For further information, refer to application report SPRA953, IC Package Thermal Metrics, also available on the TI website. TT on top of IC TB on PCB surface 4 Board Copper Area (in2) TT on top of IC TB on PCB surface 1mm 1mm See note (1) (a) Example DRB (SON) Package Measurement (1) (b) Example DRV (SON) Package Measurement Power dissipation may limit operating range. Check Thermal Information table. Figure 23. Measuring Points for TT and TB 12 Copyright © 2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 7-Apr-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS73534DRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS73534DRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS73534DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS73534DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS73534DRBR SON DRB 8 3000 367.0 367.0 35.0 TPS73534DRBT SON DRB 8 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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