CADEKA SPT574BCN

SPT574
FAST, COMPLETE 12-BIT µP COMPATIBLE
A/D CONVERTER WITH SAMPLE/HOLD
FEATURES
APPLICATIONS
• Improved Version of the HADC574Z
• Complete 12-Bit A/D Converter with Sample/Hold,
Reference and Clock
• Low Power Dissipation (100 mW Max)
• 12-Bit Linearity (Over Temp)
• 25 µs Max Conversion Time
• Single +5 V Supply
• Full Bipolar and Unipolar Input Range
•
•
•
•
•
GENERAL DESCRIPTION
The SPT574 has standard bipolar and unipolar input ranges
of 10 V and 20 V that are controlled by a bipolar offset pin and
laser trimmed for specified linearity, gain and offset accuracy.
The SPT574 is a complete, 12-bit successive approximation
A/D converter manufactured in CMOS technology. The device is an improved version of the HADC574Z. Included on
chip are an internal reference, clock, and a sample-and-hold.
The S/H is an additional feature not available on similar
devices.
Data Acquisition Systems
8 or 12-Bit µP Input Functions
Process Control Systems
Test and Scientific Instruments
Personal Computer Interface
The power supply is +5 V. The device also has an optional
mode control voltage which may be used depending on the
application. With a maximum dissipation of 100 mW at the
specified voltages, power consumption is about five times
lower than that of currently available devices.
The SPT574 features 25 µs (max) conversion time of 10 or
20 V input signals. Also, a three-state output buffer is added
for direct interface to an 8, 12, or 16-bit µP bus.
The SPT574 is available in 28-lead ceramic sidebrazed DIP,
PDIP and SOIC packages in the commercial temperature
range.
Output
BLOCK DIAGRAM
Nibble A
Nibble B
Nibble C
Three-State Buffers And Control
STS
12-Bit SAR
12-Bit
Capacitance
DAC
+
Comp
-
Clock
Offset/Gain
Trim
Control Logic
Ref
20 V In
10 V In
12/8
CS
Ao
BIP Off
R/C
CE
Ref Out
AGND
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 1 25 °C
Supply Voltages
Mode Control Voltage (VEE to DGND) .................... 0 to +7 V
Logic Supply Voltage (VDD to DGND) ...................0 to +7 V
Analog to Digital Ground (AGND to DGND) ................. ±1 V
Input Voltages
Control Input Voltages (to DGND)
(CE, CS, Ao, 12/8, R/C) ......................... -0.5 to VDD +0.5 V
Analog Input Voltage (to AGND)
(REF IN, BIP OFF, 10 VIN) ...................................... ±16.5 V
20 V VIN Input Voltage (to AGND) .............................. ±24 V
Note:
Output
Reference Output Voltage .............. Indefinite Short to GND
Momentary Short to VDD
Temperature
Operating Temperature, Ambient .................... 0 to +70 °C
Junction ......................... +165 °C
Lead Temperature, (Soldering 10 Seconds) ........... +300 °C
Storage Temperature .................................... -65 to +150 °C
Operation at any Absolute Maximum Rating is not implied. See Operating Conditions for proper nominal applied
conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA = TMIN to TMAX, VEE = 0 to +5 V, VDD = +5 V, fS = 40 kHz, fIN = 10 kHz, unless otherwise specified.
PARAMETER
TEST
CONDITIONS
TEST
LEVEL
MIN
SPT574C
TYP
MAX
MIN
SPT574B
TYP
MAX
UNITS
DC ELECTRICAL CHARACTERISTICS
Resolution
VI
12
12
Bits
±1
±0.5
LSB
Linearity Error
TA= 0 to +70 °C
VI
Differential Linearity
No Missing Codes
VI
Unipolar Offset; 10 V, 20 V
+25 °C Adjustable to Zero
VI
±2
±2
LSB
Bipolar Offset; ±5 V, ±10 V
+25 °C Adjustable to Zero
VI
±10
±4
LSB
Full Scale Calibration Error1
+25 °C Adjustable to Zero
VI
0.3
0.3
% of FS
Full Scale Calibration Error1
No Adjustment to Zero
TA = 0 to +70 °C
V
0.47
0.37
% of FS
V
V
V
±1.0
±2.0
±12
±1.0
±2.0
±12
ppm/°C
ppm/°C
ppm/°C
Temperature Coefficients
Unipolar Offset
Bipolar Offset
Full Scale Calibration
Using Internal Reference
Power Supply Rejection
+4.75 V<VDD<+5.25 V
Max Change in Full
Scale Calibration
Analog Input Ranges
Bipolar
Unipolar
Input Impedance
10 Volt Span
20 Volt Span
12
12
Bits
±0.5
VI
VI
VI
VI
VI
-5
-10
0
0
VI
VI
15
60
+5
+10
+10
+20
21
84
-5
-10
0
0
15
60
21
84
±0.5
LSB
+5
+10
+10
+20
Volts
Volts
Volts
Volts
kΩ
kΩ
SPT574
2
8/1/00
ELECTRICAL SPECIFICATIONS
TA = TMIN to TMAX, VEE = 0 to +5 V, VDD = +5 V, fS = 40 kHz, fIN = 10 kHz, unless otherwise specified.
PARAMETER
TEST
CONDITIONS
TEST
LEVEL
MIN
SPT574C
TYP
MAX
MIN
SPT574B
TYP
MAX
UNITS
DC ELECTRICAL CHARACTERISTICS
Power Supplies Operating
Voltage Range
VDD
VEE2
Operating Current
IDD
IEE2
IV
IV
+4.5
+5.5
VDD
+4.5
+5.5
VDD
Volts
Volts
IV
IV
13
167
20
13
167
20
mA
µA
Power Dissipation
VI
65
100
65
100
mW
Internal Reference
Voltage
Output Current3
VI
VI
2.4
0.5
2.5
2.6
2.4
0.5
2.5
2.6
Volts
mA
Logic 0
Logic1
VI
VI
-0.5
2.0
+0.8
5.5
-0.5
2.0
+0.8
5.5
Volts
Volts
Current
VI
-5.0
5.0
-5.0
VEE = +5 V
DIGITAL CHARACTERISTICS
Logic Inputs
(CE, CS , R/C , Ao, 12/8 )
Capacitance
Logic Outputs
(DB11-DB0, STS)
Logic 0
Logic 1
Leakage
V
(ISink = 1.6 mA)
(ISOURCE = 500 µA)
(High Z State,
DB11-DB0 Only)
Capacitance
AC Accuracy
Spurious Free Dyn. Range
Total Harmonic Distortion
Signal-to-Noise Ratio
Signal-to-Noise & Distortion
(SINAD)
Intermodulation Distortion
0. 1
5
VI
VI
VI
0. 1
+0.4
+2.4
-5
0.1
5.0
5
+5
+0.4
+2.4
-5
0.1
µA
pF
+5
Volts
Volts
µA
V
5
5
pF
V
V
V
V
78
-77
72
71
78
-77
72
71
dB
dB
dB
dB
fS=40 kHz, fIN=10 kHz
V
-75
-75
dB
fIN=10 kHz;
fIN2=11.5 kHz
Note 1: Fixed 50 Ω resistor from REF OUT to REF IN and REF OUT to BIP OFF.
Note 2: VEE is optional and is only used to set the mode for the internal sample/hold. When not using VEE, the pin should be treated
as a no connect. If VEE is connected to 0 to -15 V, aperture delay (tAP) will increase from 20 ns (typ) to 4000 ns (typ).
Note 3: Available for external loads; external load should not change during conversion.
SPT574
3
8/1/00
ELECTRICAL SPECIFICATIONS
TA = TMIN to TMAX, VEE = 0 to +5 V, VDD = +5 V, fS = 40 kHz, fIN = 10 kHz, unless otherwise specified.
TEST
CONDITIONS
PARAMETER
TEST
LEVEL
MIN
SPT574C
TYP
MAX
MIN
SPT574B
TYP
MAX
UNITS
AC ELECTRICAL CHARACTERISTICS4
Convert Mode Timing
tDSC STS Delay from CE
tHEC CE Pulse Width
tSSC CS to CE Setup
VI
VI
VI
50
50
60
30
20
200
50
50
60
30
20
200
ns
ns
ns
tHSC CS Low during CE High
VI
50
20
50
20
ns
tSRC R/C to CE Setup
VI
50
0
50
0
ns
tHRC R/C Low During CE High
tSAC Ao to CE Setup
tHAC Ao Valid During CE High
tC Conversion Time5
12-Bit Cycle
8-Bit Cycle
VI
VI
VI
50
0
50
20
50
0
50
20
ns
ns
ns
VI
VI
20
22
16
25
18
75
35
100
0
150
Read Mode Timing
tDD Access Time from CE
tHD Data Valid After CE Low
tHL Output Float Delay
tSSR CS to CE Setup
VI
VI
VI
VI
50
tSRR R/C to CE Setup
tSAR Ao to CE Setup
tHSR CS Valid After CE Low
VI
VI
VI
0
50
0
25
tHRR R/C High After CE Low
tHS STS Delay After Data Valid
tHAR Ao Valid after CE Low
VI
VI
VI
0
300
50
400
25
25
150
50
1000
20
22
16
25
18
µs
µs
75
35
100
0
150
ns
ns
ns
ns
0
50
0
25
0
300
50
400
150
ns
ns
ns
ns
ns
ns
1000
Note 4: Time is measured from 50% level of digital transitions.
Note 5: Includes acquisition time.
Figure 1 - Convert Mode Timing Diagram
Figure 2 - Read Mode Timing Diagram
CE
CE
CS
t HEC
t SSC
CS
t SSR
t HSR
t HRR
t HSC
t SRC
R/C
R/C
t SRR
t HRC
Ao
Ao
t SAR
t SAC
t HAR
t HAC
STS
STS
t DSC
tC
t HD
t HS
HIGH
DB11-DB0
IMPEDANCE
DB11-DB0
DATA
VALID
High Impedance
t DD
t HL
SPT574
4
8/1/00
ELECTRICAL SPECIFICATIONS
TA = TMIN to TMAX, VEE = 0 to +5 V, VDD = +5 V, fS = 40 kHz, fIN = 10 kHz, unless otherwise specified.
TEST
CONDITIONS
PARAMETER
TEST
LEVEL
MIN
SPT574C
TYP
MAX
MIN
SPT574B
TYP
MAX
UNITS
AC ELECTRICAL CHARACTERISTICS4
Stand-Alone Mode Timing
tHRL Low R/C Pulse Width
VI
tDS STS Delay from R/C
VI
tHDR Data Valid After R/C Low
tHS STS Delay After Data Valid
tHRH High R/C Pulse Width
tDDR Data Access Time
Sample-and-Hold
Aperture Delay
Aperture Uncertainty Time
VI
VI
VI
VI
VEE = +5 V
VEE = +5 V
25
300
100
All parameters having min/max specifications
are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
ns
400
200
25
300
100
1000
400
1000
150
IV
V
All electrical characteristics are subject to the
following conditions:
25
200
150
20
300
TEST LEVEL
TEST LEVEL CODES
20
300
ns
ns
ns
ns
ns
ns
ps, RMS
TEST PROCEDURE
I
100% production tested at the specified temperature.
II
100% production tested at TA=25 °C, and sample
tested at the specified temperatures.
III
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
IV
V
Parameter is a typical value for information purposes
only.
VI
100% production tested at TA = 25 °C. Parameter is
guaranteed over specified temperature range.
Figure 3 - Low Pulse for R/C - Outputs Enabled
After Conversion
t
25
Figure 4 - High Pulse for R/C - Outputs Enabled While
R/C is High, Otherwise High Impedance
HRL
R/C
R/C
t
t
t
HRH
DS
DS
STS
STS
t
t
HDR
t
t
C
t HS
DDR
t
C
HDR
HIGH-Z
HIGH-Z
DATA VALID
DB11-DB0
DB11-DB0
DATA VALID
DATA VALID
SPT574
5
8/1/00
CIRCUIT OPERATION
The SPT574 is a complete 12-bit analog-to-digital converter
that consists of a single chip version of the industry standard
574. This single chip contains a precision 12-bit capacitor
digital-to-analog converter (CDAC) with voltage reference,
comparator, successive approximation register (SAR), sampleand-hold, clock, output buffers and control circuitry to make it
possible to use the SPT574 with few external components.
When the control section of the SPT574 initiates a conversion
command, the clock is enabled and the successive-approximation register is reset to all zeros. Once the conversion
cycle begins, it cannot be stopped or restarted and data is not
available from the output buffers.
The SAR, timed by the clock, sequences through the conversion cycle and returns an end-of-convert flag to the control
section of the ADC. The clock is then disabled by the control
section, the output status goes low, and the control section is
enabled to allow the data to be read by external command.
The internal SPT574 12-bit CDAC is sequenced by the SAR
starting from the MSB to the LSB at the beginning of the
conversion cycle to provide an output voltage from the CDAC
that is equal to the input signal voltage (which is divided by the
input voltage divider network). The comparator determines
whether the addition of each successively-weighted bit voltage causes the CDAC output voltage summation to be
greater or less than the input voltage; if the sum is less, the
bit is left on; if more, the bit is turned off. After testing all the
bits, the SAR contains a 12-bit binary code which accurately
represents the input signal to within ±1/2 LSB.
The internal reference provides the voltage reference to the
CDAC with excellent stability over temperature and time. The
reference is trimmed to 2.5 volts and can supply at least
0.5 mA to an external load. Any external load on the SPT574
reference must remain constant during conversion.
The sample-and-hold feature is a bonus of the CDAC architecture. Therefore the majority of the S/H specifications are
included within the A/D specifications.
Although the sample-and-hold circuit is not implemented in
the classical sense, the sampling nature of the capacitive
DAC makes the SPT574 appear to have a built-in sampleand-hold. This sample-and-hold action substantially increases the signal bandwidth of the SPT574 over that of
similar competing devices.
Note that even though the user may use an external sampleand-hold for very high frequency inputs, the internal sampleand-hold still provides a very useful isolation function. Once
the internal sample is taken by the CDAC capacitance, the
input of the SPT574 is disconnected from the user’s sampleand-hold. This prevents transients occurring during conversion from affecting the attached sample-and-hold buffer. All
other 574 circuits will cause a transient load current on the
sample-and-hold which will upset the buffer output and may
add error to the conversion itself.
Furthermore, the isolation of the input after the acquisition
time in the SPT574 allows the user an opportunity to release
the hold on an external sample-and-hold and start it tracking
the next sample. This increases system throughput with the
user’s existing components.
TYPICAL INTERFACE CIRCUIT
The SPT574 is a complete A/D converter that is fully operational when powered up and issued a Start Convert Signal.
Only a few external components are necessary as shown in
figures 5 and 6. The two typical interface circuits are for
operating the SPT574 in either an unipolar or bipolar input
mode. Information on these connections and on conditions
concerning board layout to achieve the best operation are
discussed below.
For each application of this device, strict attention must be
given to power supply decoupling, board layout (to reduce
pickup between analog and digital sections), and grounding.
Digital timing, calibration and the analog signal source must
be considered for correct operation.
POWER SUPPLIES
The supply voltage for the SPT574 must be kept as quiet as
possible from noise pickup and also regulated from transients
or drops. Because the part has 12-bit accuracy, voltage
spikes on the supply lines can cause several LSB deviations
on the output. Switching power supply noise can be a
problem. Careful filtering and shielding should be employed
to prevent the noise from being picked up by the converter.
VDD should be bypassed with a 10 µF tantalum capacitor
located close to the converter to filter noise and counter the
problems caused by the variations in supply current. VEE is
only used as a logic input and is immune to typical supply
variation.
GROUNDING CONSIDERATIONS
Resistance of any path between the analog and digital
grounds should be as low as possible to accommodate the
ground currents present with this device.
To achieve specified accuracy, a double-sided printed circuit
board with a copper ground plane on the component side is
recommended. Keep analog signal traces away from digital
lines. It is best to lay the PC board out such that there is an
analog section and a digital section with a single point ground
connection between the two through an RF bead located as
close to the device as possible. If possible, run analog signals
between ground traces and cross digital lines at right angles
only.
SPT574
6
8/1/00
The analog and digital common pins should be tied together
as close to the package as possible to guarantee best
performance. The code dependent currents flow through the
VDD terminal and not through the analog and digital common
pins.
RANGE CONSIDERATIONS
The SPT574 may be operated by a microprocessor or in the
stand-alone mode. The part has four standard input ranges:
0 V to +10 V, 0 V to +20 V, ±5 V and ±10 V. The maximum
errors that are listed in the specifications for gain and offset
may be adjusted externally to zero as explained in the next
two sections.
The gain adjustment should be done at positive full scale. The
ideal input corresponding to the last code change is applied.
This is 1 and 1/2 LSB below the nominal full scale which is
+9.9963 V for the 10 V range and +19.9927 V for the 20 V
range. Adjust the gain potentiometer R2 for flicker between
codes 1111 1111 1110 and 1111 1111 1111. If calibration is
not necessary for the intended application, replace R2 with a
50 Ω, 1% metal film resistor and remove the network from the
BIP OFF pin. Connect the BIP OFF pin to AGND. Connect the
analog input to the 10 V IN pin for the 0 to 10 V range or to the
20 V IN pin for the 0 to 20 V range.
BIPOLAR
The gain and offset errors listed in the specification may be
adjusted to zero using the potentiometers R1 and R2. (See
figure 6.) If adjustment is not needed, either or both pots may
be replaced by a 50 Ω, 1% metal film resistor.
CALIBRATION & CONNECTION PROCEDURES
UNIPOLAR
The calibration procedure consists of adjusting the
converter’s most negative output to its ideal value for offset
adjustment and then adjusting the most positive output to its
ideal value for gain adjustment.
Starting with offset adjustment and referring to figure 5, the
midpoint of the first LSB increment should be positioned at
the origin to get an output code of all 0s. To do this, an input
of +1/2 LSB or +1.22 mV for the 10 V range and +2.44 mV for
the 20 V range should be applied to the SPT574. Adjust the
offset potentiometer R1 for code transition flickers between
0000 0000 0000 and 0000 0000 0001.
Figure 5 - Unipolar Input Connections
To calibrate, connect the analog input signal to the 10 V IN pin
for a ±5 V range or to the 20 V IN pin for a ±10 V range. First
apply a DC input voltage 1/2 LSB above negative full scale
which is -4.9988 V for the ±5 V range or -9.9976 V for the ±10
V range. Adjust the offset potentiometer R1 for flicker between output codes 0000 0000 0000 and 0000 0000 0001.
Next, apply a DC input voltage 1 and 1/2 LSB below positive
full scale which is +4.9963 V for the ±5 V range or +9.9927 V
for the ±10 V range. Adjust the gain potentiometer R2 for
flicker between codes 1111 1111 1110 and 1111 1111 1111.
Figure 6 - Bipolar Input Connections
Output Bits
Output Bits
R/C
R/C
Nibble A
CS
Ao
Control
Logic
Nibble B
Nibble C
Ao
Control
Logic
CE
12-Bits
STS
VDD
+5 V
.1 µF
Strobe
+15 V
12-Bits
12-Bit SAR
Oscillator
VDD
R1
100 kΩ
Strobe
12-Bits
100 kΩ
Analog
Inputs
0 to 20 V
Sample/Hold
10 V In
20 V In
DGND
Comp
CDAC
±5 V
LSB
MSB
Sample/Hold
10 V In
Analog
Inputs
BIP Off
MSB
Comp
CDAC
LSB
20 V In
±10 V
100 Ω
BIP Off
100 Ω
R1
VRef Out
100 Ω
(Calibration)
+5 V
.1 µF
12-Bits
DGND
0 to 10 V
Nibble C
STS
12-Bit SAR
Oscillator
Nibble B
Three-State Buffers And Control
12/8
CE
-15 V
Nibble A
CS
Three-State Buffers And Control
12/8
Ref
Ref
Amp
Offset/Gain
Trim Network
VRef Out
Ref
Ref
Amp
Offset/Gain
Trim Network
R2
100 Ω
R1
VRef In
VEE
VRef In
VEE
SPT574
7
8/1/00
ALTERNATIVE
Figure 7 - Interfacing the SPT574 to an 8-Bit Data Bus
In some applications, a full scale of 10.24 V (for an LSB of
2.5 mV) or 20.48 V (for an LSB of 5.0 mV) is more convenient.
In the unipolar mode of operation, replace R2 with a 200 Ω
potentiometer and add 150 Ω in series with the 10 V IN pin for
10.24 V input range or 500 Ω in series with the 20 V IN pin for
20.48 V input range. In bipolar mode of operation, replace R1
with a 500 Ω potentiometer (in addition to the previous
changes). The calibration will remain similar to the standard
calibration procedure.
Ao
Address Bus
~
STS
12/8
MSB
Ao
Data
Bus
CONTROLLING THE SPT574
The SPT574 can be operated by most microprocessor systems due to the control input pins and on-chip logic. It may
also be operated in the stand-alone mode and enabled by the
R/C input pin. Full µP control consists of selecting an 8 or
12-bit conversion cycle, initiating the conversion, and reading
the output data when ready. The output read has the options
of choosing either 12-bits at once or 8 bits followed by
4-bits in a left-justified format. All five control inputs are TTL/
CMOS compatible and include 12/8 , CS , Ao, R/C and CE.
The use of these inputs in controlling the converter’s operations is shown in table I, and the internal control logic is shown
in a simplified schematic in figure 10.
STAND-ALONE OPERATION
The simplest interface is a control line connected to R/C . The
output controls must be tied to known states as follows: CE
and 12/8 are wired high, Ao and CS are wired low. The output
data arrives in words of 12-bits each. The limits on R/C duty
cycle are shown in figures 3 and 4. It may have a duty cycle
within and including the extremes shown in the specifications. In general, data may be read when R/C is high unless
STS is also high, indicating a conversion is in progress.
Table I - Truth Table for the SPT574 Control Inputs
Operation
CE
CS
R/C
12/8
Ao
0
X
X
X
X
None
X
1
X
X
X
None
0
0
X
0
Initiate 12 bit conversion
0
0
X
1
Initiate 8 bit conversion
0
X
0
Initiate 12 bit conversion
0
1
1
X
1
Initiate 8 bit conversion
1
0
X
0
Initiate 12 bit conversion
1
0
X
1
Initiate 8 bit conversion
1
0
1
1
X
Enable 12 bit Output
1
0
1
0
0
Enable 8 MSB's Only
1
0
1
0
1
Enable 4 LSB's Plus 4
LSB
DIG
COM
CONTROLLED OPERATION
CONVERSION LENGTH
A conversion start transition latches the state of Ao as shown
in figure 7 and table I. The latched state determines if the
conversion stops with 8 bits (Ao high) or continues for 12 bits
(Ao low). If all 12 bits are read following an 8-bit conversion, the
three LSBs will be a logic 0 and DB3 will be a logic 1. Ao is latched
because it is also involved in enabling the output buffers as
will be explained later. No other control inputs are latched.
CONVERSION START
A conversion may be initiated by a logic transition on any of
the three inputs: CE, CS , R/C , as shown in table I. The last
of the three to reach the correct state starts the conversions,
so one, two or all three may be dynamically controlled. The
nominal delay from each is the same and all three may
change state simultaneously. In order to assure that a particular input controls the start of conversion, the other two
should be set up at least 50 ns earlier. Refer to the convert
mode timing specifications. The Convert Start timing diagram
is illustrated in figure 1.
The output signal STS is the status flag and goes high only
when a conversion is in progress. While STS is high, the
output buffers remain in a high impedance state so that data
can not be read. Also, when STS is high, an additional Start
Convert will not reset the converter or reinitiate a conversion.
Note, if Ao changes state after a conversion begins, an
additional Start Convert command will latch the new start of
Ao and possibly cause a wrong cycle length for that conversion (8 versus 12 bits).
Trailing Zeroes
SPT574
8
8/1/00
READING THE OUTPUT DATA
SAMPLE-AND-HOLD (S/H) CONTROL MODE
The output data buffers remain in a high impedance state until
the following four conditions are met: R/C is high, STS is low,
CE is high, and CS is low. The data lines become active in
response to the four conditions and output data according to
the conditions of 12/8 and Ao. The timing diagram for this
process is shown in figure 2. When 12/8 is high, all 12 data
outputs become active simultaneously and the Ao input is
ignored. This is for easy interface to a 12 or 16-bit data bus.
The 12/8 input is usually tied high or low, although it is
TTL/CMOS compatible. When 12/8 is low, the output is
separated into two 8-bit bytes as shown below.
This control mode is provided to allow full use of the internal
S/H, eliminating the need for an external S/H in most applications. The SPT574 in the control mode also eliminates the
need for one of the control signals, usually the convert
command. The command that puts the internal S/H in the
hold state also initiates a conversion, reducing time constraints in many systems. As soon as the conversion is
completed the internal S/H immediately begins slewing to
track the input signal. See figure 9.
Figure 8 - Output When 12/8 Is Low
BYTE 1
X X X X
BYTE 2
X X X X
MSB
X X X X
O O O O
LSB
This configuration makes it easy to connect to an 8-bit data
bus as shown in figure 7. The Ao control can be connected to
the least significant bit of the address bus in order to store the
output data into two consecutive memory locations. When Ao
is pulled low, the 8 MSBs are enabled only. When Ao is high,
the 4 MSBs are disabled, bits 4 through 7 are forced to a zero
and the four LSBs are enabled. The two byte format is left
justified data as shown above and can be considered to have
a decimal point or binary to the left of byte 1.
Ao may be toggled without damage to the converter at any
time. Break-before-make action is guaranteed between the
two data bytes. This assures that the outputs in figure 7 will
never be enabled at the same time.
In figure 2, it can be seen that a read operation usually begins
after the conversion is completed and STS is low. If earlier
access is needed, the read can begin no later than the
addition of time tDD and tHS before STS goes low.
In the control mode it is assumed that during the required 4
µs acquisition time the signal is not slewing faster than the
slew rate of the SPT574. No assumption is made about the
input level after the convert command arrives since the input
signal is sampled and conversion begins immediately after
the convert command. This means that the convert command can be used to switch an input multiplexer or change
gains on a programmable gain amplifier, allowing the input
signal to settle before the next acquisition at the end of the
conversion. Because aperture jitter is minimized by the
internal S/H, a high input frequency can be converted without
an external S/H. See table II.
Table II - Conversion Timing (VEE = +5 V)
Parameter
Throughput Time (tAQ+tC)
12-Bit Conversions
8-Bit Conversions
Conversion Time (tC)
12-Bit Conversions
8-Bit Conversions
Acquisition Time(tAC)
Aperture Delay (tAP)
Aperture Uncertainty (tJ)
S/H Control Mode
Min
Typ Max
Units
22
16
µs
µs
18
12
4
20
0.3
25
18
µs
µs
µs
ns
ns
Figure 9 - S/H Control Mode Timing (VEE = +5 V)
R/C
tC
tAP
Signal Acquisition
Conversion
Signal Acquisition
tAQ
SPT574
9
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Figure 10 - Control Logic
Nibble B Zero
Override
Nibble A,B
Input Buffers
12/8
Nibble C
CS
Read Control
A
R/C
H
D
Q
CK
CE
R
EOC8
CK
Delay
Q
STS
D
Q
AO Latch
EOC12
PACKAGE OUTLINES
28-Lead PDIP
INCHES
SYMBOL
A
B
C
D
E
F
G
H
I
J
K
K
28
I
1
MIN
0.115
0.014
0.030
0.008
0.125
0.600
0.485
1.380
0.005
MILLIMETERS
MAX
0.250
0.200
0.022
0.100
0.070
0.015
0.195
0.625
0.580
1.565
0.040
MIN
2.92
0.36
0.76
0.20
3.18
15.24
12.32
35.05
0.13
MAX
6.35
5.08
0.56
2.54
1.78
0.38
4.95
15.88
14.73
39.75
1.02
J
H
G
A
B
F
C
D
E
SPT574
10
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PACKAGE OUTLINES
28-Lead Sidebrazed
28
H
INCHES
SYMBOL
I
1
J
G
A
E
F
MIN
MILLIMETERS
MAX
MIN
MAX
A
0.077
0.093
1.96
2.36
B
C
0.016
0.095
0.020
0.105
0.41
2.41
0.51
2.67
D
E
F
0.040
0.215
.050 typ
0.060
0.235
1.02
5.46
1.27 typ
1.52
5.97
G
H
I
J
1.388
0.585
0.009
0.600
1.412
0.605
0.012
0.620
35.26
14.86
0.23
15.24
35.86
15.37
0.30
15.75
C
B
D
28-Lead SOIC
INCHES
SYMBOL
28
MIN
1
A
MIN
A
0.696
0.712
17.68
B
0.004
0.012
0.10
C
I H
MILLIMETERS
MAX
.050 typ
MAX
18.08
0.30
1.27 typ
D
0.014
0.019
0.36
0.48
E
0.009
0.012
0.23
0.30
2.64
F
0.080
0.104
2.03
G
0.016
0.050
0.41
1.27
H
0.394
0.419
10.01
10.64
I
0.291
0.299
7.39
7.59
H
F
B
C
D
G
E
SPT574
11
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PIN ASSIGNMENTS
PIN FUNCTIONS
NAME
FUNCTION
1 VDD
STS
28
2 12/8
DB11
27
VDD
Logic Supply Voltage, Nominally +5 V
3 CS
DB10
26
12/8
Data Mode Selection
4 Ao
DB9
25
CS
Chip Selection
5 R/C
DB8
24
Ao
Byte Address/Short Cycle
6 CE
DB7
23
R/C
Read/Convert
7 N/C
DB6
22
CE
Chip Enable
8 REF OUT
DB5
21
VEE
Mode Control Voltage, Nominally +5 V
9 AGND
DB4
20
REF OUT
Reference Output, Nominally +2.5 V
10 REF IN
DB3
19
AGND
Analog Ground
11 VEE
DB2
18
REF IN
Reference Input
N/C
Pin Not Connected to Device
12 BIP OFF
DB1
17
13 10 V IN
BIP OFF
Bipolar Offset
DB0
16
10 V IN
10 Volt Analog Input
14 20 V IN
DGND
15
20 V IN
20 Volt Analog Input
DGND
Digital Ground
DB0 - DB11
Digital Data Output
DB11 - MSB
DB0 - LSB
STS
Status
28-LEAD DIP/SOIC
ORDERING INFORMATION
TEMPERATURE RANGE
0 to +70 °C
LINEARITY ERROR
MAX
±1/2 LSB
SPT574BCJ
0 to +70 °C
±1/2 LSB
28L Sidebrazed DIP
SPT574BCS
0 to +70 °C
±1/2 LSB
28L SOIC
SPT574CCN
0 to +70 °C
±1 LSB
28L Plastic DIP
SPT574CCJ
0 to +70 °C
±1 LSB
28L Sidebrazed DIP
SPT574CCS
0 to +70 °C
±1 LSB
28L SOIC
PART NUMBER
SPT574BCN
PACKAGE
TYPE
28L Plastic DIP
SPT574
12
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