SPT7760 8-BIT, 1 GSPS, FLASH A/D CONVERTER OCTOBER 2002 FEATURES APPLICATIONS • • • • • • • • • • 1:2 Demuxed ECL compatible outputs Wide input bandwidth – 900 MHz Low input capacitance – 15 pF Metastable errors reduced to 1 LSB Monolithic for low cost Gray code output GENERAL DESCRIPTION The SPT7760 is a full parallel (flash) analog-to-digital converter capable of digitizing full scale (0 to –2 V) inputs into eight-bit digital words at an update rate of 1 GSPS. The ECL-compatible outputs are demultiplexed into two separate output banks, each with differential data ready outputs to ease the task of data capture. The SPT7760’s wide input bandwidth and low capacitance eliminate the need for ex- BLOCK DIAGRAM ternal track-and-hold amplifiers for most applications. A proprietary decoding scheme reduces metastable errors to the 1 LSB level. The SPT7760 operates from a single –5.2 V supply, with a nominal power dissipation of 5.5 W. The SPT7760 is available in an 80-lead surface-mount MQuad package over the industrial temperature range (–25 °C to +85 °C). CLK CLK CLOCK BUFFER Analog VRT Input Preamp Digital oscilloscopes Transient capture Radar, EW, ECM Direct RF down-conversion DEMUX CLOCK BUFFER Comparator 256 127 64 63 2 1 VRB D7B D8B (OVR) D6B D7B (MSB) D5B D6B D4B D5B D3B D2B D5 D4 D3 D2 D1 D0 (LSB) D1B D0B D8A D7A D6A D5A D4B BANK B D6 D8B DRB (DATA READY) D3B D2B D1B D0B (LSB) DRA (DATA READY) DRA (DATA READY) D8A (OVR) D7A (MSB) D6A D4A D5A D3A D4A D2A D3A D1A D2A D0A D1A D0A (LSB) BANK A VRM D7 (MSB) 1:2 DEMULTIPLEXER 128 256 TO 8 Bit Decoder With Metastable Error Correction 152 151 DRB (DATA READY) D8 (OVR) ECL Output Buffers And Latches 255 ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C Supply Voltages Negative Supply Voltage (VEE TO GND) –7.0 to +0.5 V Ground Voltage Differential .................... –0.5 to +0.5 V Output Digital Output Current ............................... 0 to –28 mA Temperature Operating Temperature, ambient ............ –25 to +85 °C case .......................... +125 °C junction ...................... +150 °C Lead Temperature, (soldering 10 seconds) ...... +300 °C Storage Temperature ............................ –65 to +150 °C Input Voltage Analog Input Voltage ............................... +0.5 V to VEE Reference Input Voltage .......................... +0.5 V to VEE Digital Input Voltage ................................ +0.5 V to VEE Reference Current VRT to VRB ........................... 35 mA Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS TJ = TC = TA = +25 °C , VEE=–5.2 V, VRB=–2.0 V, VRM=–1.0 V, VRT=0.00 V, ƒCLK=1 GHz, Duty Cycle=50%, unless otherwise specified. PARAMETERS TEST CONDITIONS TEST LEVEL MIN Resolution DC Accuracy Integral Linearity Error (ILE) Differential Linearity Error (DLE) No Missing Codes Analog Input Input Voltage Range Input Bias Current Input Resistance Input Capacitance Input Bandwidth Small Signal Large Signal Offset Error VRT Offset Error VRB Input Slew Rate Clock Synchronous Input Currents SPT7760A TYP MAX MIN 8 ƒCLK = 100 kHz I –1.0 ƒCLK = 100 kHz I –0.85 8 +1.0 –1.5 +0.95 –0.95 Guaranteed VIN=0 V Over Full Input Range I I V V VRB .75 15 15 V V IV IV V Bits +1.5 LSB +1.5 LSB VRT 2.0 V mA kΩ pF Guaranteed VRT 2.0 VRB .75 15 15 900 500 5 5 MHz MHz mV mV V/ns 2 2 µA 80 30 Ω MHz 2 250 1.4 1.75 GHz ps ps ns ns –30 –30 V SPT7760B TYP MAX UNITS 900 500 +30 +30 –30 –30 +30 +30 Reference Input Ladder Resistance Reference Bandwidth I V 60 Timing Characteristics Maximum Sample Rate Aperture Jitter Acquisition Time Clock to Data Delay CLK to Data Ready Delay I V V IV IV 1 0.9 1.25 I I 45 43 43 41 dB dB I I –44 –36 –42 –34 dBc dBc I I 42 35 40 33 dB dB Dynamic Performance Signal-To-Noise Ratio (without Harmonics) ƒIN = 50 MHz ƒIN = 250 MHz Total Harmonic Distortion ƒIN = 50 MHz ƒIN = 250 MHz Signal-to-Noise and Distortion ƒIN = 50 MHz ƒIN = 250 MHz 2 80 30 60 1 2 250 1.4 1.75 1.9 2.25 0.9 1.25 1.9 2.25 SPT7760 October 2002 ELECTRICAL SPECIFICATIONS TJ = TC = TA = +25 °C , VEE=–5.2 V, VRB=–2.0 V, VRM=–1.0 V, VRT=0.00 V, ƒCLK=1 GHz, Duty Cycle=50%, unless otherwise specified. PARAMETERS TEST CONDITIONS Dynamic Performance Spurious Free Dynamic Range ƒIN = 50 MHz ƒIN = 250 MHz Digital Inputs Input High Voltage (CLK, CLK) Input Low Voltage (CLK, CLK) Clock Pulse Width High (tPWH) Clock Pulse Width Low (tPWL) Digital Outputs Logic 1 Voltage Logic 0 Voltage Rise Time Fall Time 20% to 80% 20% to 80% Power Supply Requirements Voltage VEE Current IEE Power Dissipation TEST LEVEL MIN I I 47 39 I –1.1 –0.7 I I I 0.5 0.5 –1.8 0.4 0.4 I I V V –1.1 IV I I –4.95 SPT7760A TYP MAX MIN SPT7760B TYP MAX UNITS 43 35 –0.9 –1.8 450 450 –5.2 1.05 5.5 –1.1 –0.7 0.5 0.5 –1.8 0.4 0.4 –1.5 –1.1 –1.5 –5.45 1.2 6.25 dB dB –4.95 –0.9 –1.8 450 450 –5.2 1.05 5.5 V –1.5 –1.5 V ns ns V V ps ps –5.45 V 1.2 A 6.25 W Typical Thermal Impedance: θJC = +4 °C/W. TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. LEVEL I II III IV V VI TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. Unless otherwise noted, all test are pulsed tests; therefore, TJ = TC = TA. 3 SPT7760 October 2002 GENERAL DESCRIPTION makes the part easier to drive than previous flash converters. The preamplifiers also add a gain of two to the input signal so that each comparator has a wider overdrive or threshold range to “trip” into or out of the active state. This gain reduces metastable states that can cause errors at the output. The SPT7760 is one of the fastest monolithic 8-bit parallel flash A/D converters available today. The nominal conversion rate is 1 GSPS and the analog bandwidth is in excess of 900 MHz. A major advance over previous flash converters is the inclusion of 256 input preamplifiers between the reference ladder and input comparators (see block diagram). This not only reduces clock transient kickback to the input and reference ladder due to a low AC beta, but also reduces the effect of the dynamic state of the input signal on the latching characteristics of the input comparators. The preamplifiers act as buffers and stabilize the input capacitance so that it remains constant over different input voltage and frequency ranges and therefore The SPT7760 has true differential analog and digital data paths from the preamplifiers to the output buffers (Current Mode Logic) for reducing potential missing codes while rejecting common mode noise. Signature errors are also reduced by careful layout of the analog circuitry. The output drive capability of the device can provide full ECL swings into 50 Ω loads. Figure 1 – SPT7760 Typical Interface Circuit DRB 50 W DRA VIN DRA DRB (DATA READY) DRA (DATA READY) U3 DRA (DATA READY) 50 W VIN 50 W VIN** DRB (DATA READY) U3 DRB 2.0 V Pulldown (Digital) VRTF D8B (OVR) D7B (MSB) D6B D5B D4B D3B D2B D1B D0B (LSB) VRTS R 22 W + U1 * VRM R * CLK U2 50 W 5.2 V CLK 50 W 2 V Pulldown (Analog) .1 µF * DGND 50 W AGND Convert VRBF 50 W 5.2 V VRBS VEE 2.0 V Reference 22 W 2N2907 +U1 D8A (OVR) D7A (MSB) D6A D5A D4A D3A D2A D1A D0A (LSB) 2.0 V Pulldown (Digital) FB = Ferrite bead U1 = OP291 or equivalent with low offset/noise. R = 1 kW; 0.1% matched. FB = AGND 5.2 V = DGND U2 = ON Semiconductor ECLinPS LITE, MC10EL16, differential receiver with 250 ps (typ) propagation delay. U3 = MC10EL16 or MC100EL16. * = 10 µF Tantalum Capacitor and 0.1 µF Chip Capacitor ** = Care must be taken to avoid exceeding the maximum rating for the input, especially during power up sequencing of the analog input driver. 4 SPT7760 October 2002 TYPICAL INTERFACE CIRCUIT VRBF, VRBS, VRTF, VRTS, VRM (REFERENCE INPUTS) The circuit in figure 1 is intended to show the most elaborate method of achieving the least error by correcting for integral linearity, input induced distortion, and power supply/ground noise. This is achieved by the use of external reference ladder tap connections, input buffer, and supply decoupling. Please contact the factory for the SPT7760 evaluation board application note that contains more details on interfacing the SPT7760. The function of each pin and external connections to other components is as follows: There are two reference inputs and one external reference voltage tap. These are –2 V (VRB force and sense), midtap (VRM) and AGND (VRT force and sense). The reference pins and tap can be driven by op amps as shown in figure 1 or VRM may be bypassed for limited temperature operation. These voltage inputs can be bypassed to AGND for further noise suppression if so desired. Table I – Output Coding VIN >–0.5 LSB –0.5 LSB VEE, AGND, DGND VEE is the supply pin with AGND as ground for the device. The power supply pins should be bypassed as close to the device as possible with at least a .01 µF ceramic capacitor. A 10 µF tantalum can also be used for low frequency suppression. DGND is the ground for the ECL outputs and is to be referenced to the output pulldown voltage and appropriately bypassed as shown in figure 1. –1.5 LSB • • • –1.0 V • • • –2.0 V +0.5 LSB VIN (ANALOG INPUT) There are two analog input pins that are tied to the same point internally. Either one may be used as an analog input sense and the other for input force. This is convenient for testing the source signal to see if there is sufficient drive capability. The pins can also be tied together and driven by the same source. The SPT7760 is superior to similar devices due to a preamplifier stage before the comparators. This makes the device easier to drive because it has constant capacitance and induces less slew rate distortion. <(–2.0 V +0.5 LSB) D8 1 1 0 0 0 • • • 0 0 • • • 0 0 0 D7 10 10 10 10 10 . 0 0 0 0 0 110 010 000 000 000 . . 000 000 000 000 000 • • • 000 000 • • • 000 000 000 D8 00 00 00 00 01 00 00 01 00 00 Indicates the transition between the two codes THERMAL MANAGEMENT The typical thermal impedance is as follows: ΘCA = +17 °C/W in still air with no heat sink CLK, CLK (CLOCK INPUTS) The clock inputs are designed to be driven differentially with ECL levels. The duty cycle of the clock should be kept at 50% to avoid causing larger second harmonics. If this is not important to the intended application, then duty cycles other than 50% may be used. D0 TO D8, DR, DR, (A AND B) The digital outputs can drive 50 Ω to ECL levels when pulled down to –2 V. When pulled down to –5.2 V, the outputs can drive 130 Ω to 1 kΩ loads. All digital outputs are grey code with the coding as shown in table I. CADEKA recommends using differential receivers on the outputs of the data ready lines to ensure the proper output rise and fall times. 5 We highly recommend that a heat sink be used for this device with adequate air flow to ensure rated performance of the device. We have found that a Thermalloy 17846 heat sink with a minimum air flow of 1 meter/second (200 linear feet per minute) provides adequate thermal performance under laboratory tests. Application specific conditions should be taken into account to ensure that the device is properly heat sinked. SPT7760 October 2002 OPERATION prior to the clock transition and output logic codes in sequence from the top comparators, closest to VRT (0 V), down to the point where the magnitude of the input signal changes sign (thermometer code). The output of each comparator is then registered into four 64-to-6 bit decoders when the CLK is changed from high to low. At the output of the decoders is a set of four 7-bit latches which are enabled (“track”) when the clock changes from high to low. From here, the output of the latches are coded into 6 LSBs from 4 columns and 4 columns are coded into 2 MSBs. Finally, 8 ECL output latches and buffers are used to drive the external loads. The conversion takes one clock cycle from the input to the data outputs. The SPT7760 has 256 preamp/comparator pairs which are each supplied with the voltage from VRT to VRB divided equally by the resistive ladder as shown in the block diagram. This voltage is applied to the positive input of each preamplifier/comparator pair. An analog input voltage applied at VIN is connected to the negative inputs of each preamplifier/comparator pair. The comparators are then clocked through each one’s individual clock buffer. When the CLK pin is in the low state, the master or input stage of the comparators compare the analog input voltage to the respective reference voltage. When the CLK pin changes from low to high the comparators are latched to the state Figure 2 – Timing Diagram N VIN N+5 N+1 N+2 N+6 N+4 2.0 ns N+3 CLK CLK DRA 1.75 ns typ DRA Data Bank A N-2 N N+2 N+4 1.4 ns typ 1.75 ns typ DRB DRB Data Bank B N-1 N+1 N+3 1.4 ns typ 6 SPT7760 October 2002 Figure 3 – Subcircuit Schematics Input Circuit Output Circuit DGND AGND AGND VIN Clock Input AGND VR CLK CLK Data Out VEE VEE PACKAGE OUTLINE 80-Lead MQuad G F H I A B Symbol A B C D E F G H I J K L M J C D E K Inches Min Max 0.904 0.923 0.777 0.781 0.472 typ 0.541 0.545 0.667 0.687 0.031 typ 0.012 0.018 0.109 0.134 0.010 0.024 0.724 typ 0.099 0.110 0° 7° 0.029 0.041 Millimeters Min Max 22.95 23.45 19.74 19.84 12.00 typ 13.74 13.84 16.95 17.45 0.80 typ 0.30 0.45 2.76 3.40 0.25 0.60 18.40 typ 2.51 2.80 0° 7° 0.73 1.03 M L 7 SPT7760 October 2002 PIN FUNCTIONS D1B VEE D0B DGND DRB DGND DRB DGND D8A DGND D7A DGND D6A VEE D5A D4A AGND Analog Ground VRTF Reference Voltage Force Top, Nominally 0 V VRTS Reference Voltage Sense Top VRM Reference Voltage Middle, Nominally –1 V VRBF Reference Voltage Force Bottom, Nominally –2 V VRBS Reference Voltage Sense Bottom VIN Analog Input Voltage, Can Be Either Voltage or Sense 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 MQUAD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 N/C N/C D3A D2A VEE D1A DGND D0A DGND DRA DGND DRA AGND AGND CLK VEE CLK VEE VEE AGND AGND VRTS VRTF N/C FUNCTION VEE Negative Supply Nominally –5.2 V DGND Digital Ground D0–D7A Data Output Bank A D0–D7B Data Output Bank B DRA Data Ready Bank A DRA Not Data Ready Bank A DRB Data Ready Bank B DRB Not Data Ready Bank B D8A Overrange Output Bank A D8B Overrange Output Bank B CLK Clock Input CLK Clock Input AGND AGND VEE VEE AGND AGND N/C VIN VIN N/C VRM AGND AGND VEE VEE VEE 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 D2B D3B D4B VEE VEE D5B DGND D6B DGND D7B DGND D8B N/C N/C AGND AGND AGND AGND VEE VEE VRBF VEE VEE VRBS NAME 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PIN ASSIGNMENTS ORDERING INFORMATION PART NUMBER DESCRIPTION TEMPERATURE RANGE PACKAGE SPT7760AIK ILE = 1.0 LSB –25 to +85 °C 80L MQuad SPT7760BIK ILE = 1.5 LSB –25 to +85 °C 80L MQuad 8 SPT7760 October 2002