TL750Mxx-Q1, TL751Mxx-Q1 SGLS312J – SEPTEMBER 2005 – REVISED JUNE 2011 www.ti.com AUTOMOTIVE LOW-DROPOUT VOLTAGE REGULATORS Check for Samples: TL750Mxx-Q1, TL751Mxx-Q1 FEATURES 1 • • Qualified for Automotive Applications Low Dropout Voltage, Less Than 0.6 V at 750 mA Low Quiescent Current TTL- and CMOS-Compatible Enable on TL751M Series • • • • • • Load-Dump Protection Overvoltage Protection Internal Thermal Overload Protection Internal Overcurrent-Limiting Circuitry DESCRIPTION The TL750M and TL751M series are low-dropout positive voltage regulators specifically designed for automotive applications. The TL750M and TL751M series incorporate onboard overvoltage and current-limiting protection circuitry to protect the devices and the regulated system. Both series are fully protected against load-dump and reverse-battery conditions. Load-dump protection is up to a maximum of 60 V at the input of the device. Low quiescent current, even during full-load conditions, makes the TL750M and TL751M series ideal for use in applications that are permanently connected to the vehicle battery. The TL750M and TL751M series offers 5-V, 8-V, and 12-V options. The TL751M series has the addition of an enable (ENABLE) input. The ENABLE input gives complete control over power up, allowing sequential power up or shutdown. When ENABLE is high, the regulator output is placed in the high-impedance state. The ENABLE input is TTL and CMOS compatible. The TL750Mxx and TL751Mxx are characterized for operation over the virtual junction temperature range –40°C to 125°C. AVAILABLE OPTIONS (1) TJ VO NOM (V) 5V 8V 12 V –40°C to 125°C 5V 8V 12 V (1) (2) PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING TO-263-3 – KTT Reel of 500 TL750M05QKTTRQ1 TL750M05Q1 TO-252-3 – KVU Reel of 2500 TL750M05QKVURQ1 750M05Q TO-263-3 – KTT Reel of 500 TL750M08QKTTRQ1 TL750M08Q1 TO-252-3 – KVU Reel of 2500 TL750M08QKVURQ1 750M08Q TO-263-3 – KTT Reel of 500 TL750M12QKTTRQ1 TL750M12Q1 TO-252-3 – KVU Reel of 2500 TL750M12QKVURQ1 750M12Q TO-263-5 – KTT Reel of 500 TL751M05QKTTRQ1 TL751M05Q1 TO-252-5 – KVU Reel of 2500 TL751M05QKVURQ1 751M05Q TO-263-5 – KTT Reel of 500 TL751M08QKTTRQ1 TL751M08Q1 TO-252-5 – KVU Reel of 2500 TL751M08QKVURQ1 751M08Q TO-263-5 – KTT Reel of 500 TL751M12QKTTRQ1 TL751M12Q1 TO-252-5 – KVU Reel of 2500 TL751M12QKVURQ1 751M12Q For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2011, Texas Instruments Incorporated TL750Mxx-Q1, TL751Mxx-Q1 SGLS312J – SEPTEMBER 2005 – REVISED JUNE 2011 www.ti.com TL750M KTT (TO-263-3) PACKAGE (TOP VIEW) TL751M KTT (TO-263-5) PACKAGE (TOP VIEW) NC OUTPUT COMMOM INPUT ENABLE COMMON COMMON OUTPUT COMMON INPUT TL750M KVU (TO-252-3) PACKAGE (TOP VIEW) COMMOM COMMOM OUTPUT COMMON INPUT TL751M KVU (TO-252-5) PACKAGE (TOP VIEW) NC OUTPUT COMMON INPUT ENABLE NOTE: The COMMON terminal is in electrical contact with the mounting base. NC – No internal connection TL751Mxx FUNCTIONAL BLOCK DIAGRAM INPUT ENABLE Enable Current Limiting 28 V _ + Bandgap OUTPUT Overvoltage/ Thermal Shutdown COMMON 2 Copyright © 2005–2011, Texas Instruments Incorporated TL750Mxx-Q1, TL751Mxx-Q1 SGLS312J – SEPTEMBER 2005 – REVISED JUNE 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Continuous input voltage 26 V Transient input voltage (see Figure 4) 60 V Continuous reverse input voltage –15 V Transient reverse input voltage Package thermal impedance (2) θJA –50 V t = 100 ms (3) KTT package (3 pin) 26.9°C/W KTT package (5 pin) 26.5°C/W KVU package 38.6°C/W TJ Virtual junction temperature range –40°C to 150°C Tstg Storage temperature range –65°C to 150°C (1) (2) (3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can impact reliability. Due to variation in individual device electrical characteristics and thermal resistance, the built-in thermal overload protection may be activated at power levels slightly above or below the rated dissipation. The package thermal impedance is calculated in accordance with JESD 51. THERMAL INFORMATION TL750M05 THERMAL METRIC (1) KTT UNITS 3 PINS Junction-to-ambient thermal resistance (2) θJA 27.5 (3) θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (4) 17.3 ψJT Junction-to-top characterization parameter (5) 2.8 ψJB Junction-to-board characterization parameter (6) 9.3 θJCbot Junction-to-case (bottom) thermal resistance (7) 0.3 (1) (2) (3) (4) (5) (6) (7) 43.2 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. RECOMMENDED OPERATING CONDITIONS MIN MAX 6 26 TL75xM08 9 26 TL75xM12 13 26 15 TL75xM05 VI Input voltage VIH High-level ENABLE input voltage TL751Mxx 2 VIL Low-level ENABLE input voltage TL751Mxx 0 IO Output current TL75xMxx TJ Operating virtual junction temperature TL75xMxx Copyright © 2005–2011, Texas Instruments Incorporated –40 UNIT V V 0.8 V 750 mA 125 °C 3 TL750Mxx-Q1, TL751Mxx-Q1 SGLS312J – SEPTEMBER 2005 – REVISED JUNE 2011 www.ti.com TL751Mxx ELECTRICAL CHARACTERISTICS VI = 14 V, IO = 300 mA, TJ = 25°C TL751Mxx PARAMETER UNIT TYP Response time, ENABLE to output (start-up) µs 50 TL750M05/TL751M05 ELECTRICAL CHARACTERISTICS VI = 14 V, IO = 300 mA, ENABLE at 0 V for TL751M05, TJ = –40°C to 125°C (unless otherwise noted) (1) PARAMETER Output voltage TL750M05 TL751M05 TEST CONDITIONS VI = 6 V to 26 V UNIT MIN TYP MAX 4.85 5 5.15 VI = 9 V to 16 V, IO = 250 mA 10 25 VI = 6 V to 26 V, IO = 250 mA 12 50 Power-supply ripple rejection VI = 8 V to 18 V, f = 120 Hz 55 Load regulation IO = 5 mA to 750 mA Line regulation Dropout voltage (2) 0.5 IO = 750 mA, TJ = 25°C 0.65 IO = 750 mA Shutdown current (TL751M05 only) ENABLE VIH ≥ 2 V (2) 60 IO = 10 mA mV dB 50 IO = 500 mA, TJ = 25°C Current consumption Iq = II – IO (1) 20 V 75 5 200 mV V mA µA Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF tantalum capacitor on the output, with equivalent series resistance within the guidelines shown in Figure 4. Measured when the output voltage, VO, has dropped 100 mV from the nominal value obtained at VI = 14 V. TL750M08/TL751M08 ELECTRICAL CHARACTERISTICS VI = 14 V, IO = 300 mA, ENABLE at 0 V for TL751M08, TJ = –40°C to 125°C (unless otherwise noted) (1) PARAMETER Output voltage TL750M08 TL751M08 TEST CONDITIONS VI = 6 V to 26 V UNIT MIN TYP MAX 7.76 8 8.24 VI = 10 V to 17 V, IO = 250 mA 12 40 VI = 9 V to 26 V, IO = 250 mA 15 68 Power-supply ripple rejection VI = 11 V to 21 V, f = 120 Hz 55 Load regulation IO = 5 mA to 750 mA Line regulation Dropout voltage (2) IO = 750 mA, TJ = 25°C 0.65 Shutdown current (TL751M08 only) ENABLE VIH ≥ 2 V (2) 4 80 0.5 IO = 750 mA, TJ = 25°C IO = 10 mA 60 mV dB IO = 500 mA, TJ = 25°C Current consumption Iq = II – IO (1) 24 V 75 5 200 mV V mA µA Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF tantalum capacitor on the output, with equivalent series resistance within the guidelines shown in Figure 4. Measured when the output voltage, VO, has dropped 100 mV from the nominal value obtained at VI = 14 V. Copyright © 2005–2011, Texas Instruments Incorporated TL750Mxx-Q1, TL751Mxx-Q1 SGLS312J – SEPTEMBER 2005 – REVISED JUNE 2011 www.ti.com TL750M12/TL751M12 ELECTRICAL CHARACTERISTICS VI = 14 V, IO = 300 mA, ENABLE at 0 V for TL751M12, TJ = –40°C to 125°C (unless otherwise noted) (1) PARAMETER Output voltage TEST CONDITIONS UNIT MIN TYP MAX 11.76 12 12.24 VI = 14 V to 19 V, IO = 250 mA 15 43 VI = 13 V to 26 V, IO = 250 mA 20 78 Power-supply ripple rejection VI = 13 V to 23 V, f = 120 Hz Load regulation IO = 5 mA to 750 mA Line regulation Dropout voltage (2) VI = 13 V to 26 V TL750M12 TL751M12 30 0.5 0.6 Shutdown current (TL751M12 only) ENABLE VIH ≥ 2 V IO = 10 mA 60 mV dB 120 IO = 750 mA, TJ = 25°C IO = 750 mA, TJ = 25°C (2) 55 IO = 500 mA, TJ = 25°C Current consumption Iq = II – IO (1) 50 V 75 5 200 mV V mA µA Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into account separately. All characteristics are measured with a 0.1-µF capacitor across the input and a 10-µF tantalum capacitor on the output, with equivalent series resistance within the guidelines shown in Figure 4. Measured when the output voltage, VO, has dropped 100 mV from the nominal value obtained at VI = 14 V. Copyright © 2005–2011, Texas Instruments Incorporated 5 TL750Mxx-Q1, TL751Mxx-Q1 SGLS312J – SEPTEMBER 2005 – REVISED JUNE 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION The TL750Mxx and TL751Mxx are low-dropout regulators. The output capacitor value and the parasitic equivalent series resistance (ESR) affect the bandwidth and stability of the control loop for these devices. For this reason, the capacitor and ESR must be carefully selected for a given operating temperature and load range. Figure 2 and Figure 3 can be used to establish the appropriate capacitance value and ESR for the best regulator transient response. Figure 2 shows the recommended range of ESR for a given load with a 10-µF capacitor on the output. Figure 2 also shows a maximum ESR limit of 2 Ω and a load-dependent minimum ESR limit. For applications with varying loads, the lightest load condition should be chosen because it is the worst case. Figure 3 shows the relationship of the reciprocal of ESR to the square root of the capacitance, with a minimum capacitance limit of 10 µF and a maximum ESR limit of 2 Ω. This figure establishes the amount that the minimum ESR limit shown in Figure 2 can be adjusted for different capacitor values. For example, where the minimum load needed is 200 mA, Figure 2 suggests an ESR range of 0.8 Ω to 2 Ω for 10 µF. Figure 3 shows that changing the capacitor from 10 µF to 400 µF can change the ESR minimum by greater than 3/0.5 (or 6). Therefore, the new minimum ESR value is 0.8/6 (or 0.13 Ω). This allows an ESR range of 0.13 Ω to 2 Ω, achieving an expanded ESR range by using a larger capacitor at the output. For better stability in low-current applications, a small resistance placed in series with the capacitor (see Table 1) is recommended, so that ESRs better approximate those shown in Figure 2 and Figure 3. Table 1. Compensation for Increased Stability at Low Currents MANUFACTURER CAPACITANCE ESR TYP AVX 15 µF 0.9 Ω TAJB156M010S 1Ω KEMET 33 µF 0.6 Ω T491D336M010AS 0.5 Ω Applied Load Current PART NUMBER ADDITIONAL RESISTANCE ∆IL Load Voltage ∆VL ∆VL = ∆IL × ESR Figure 1. 6 Copyright © 2005–2011, Texas Instruments Incorporated TL750Mxx-Q1, TL751Mxx-Q1 SGLS312J – SEPTEMBER 2005 – REVISED JUNE 2011 www.ti.com OUTPUT CAPACITOR EQUIVALENT SERIES RESISTANCE (ESR) vs LOAD CURRENT RANGE STABILITY vs EQUIVALENT SERIES RESISTANCE (ESR) This Region Not Recommended for Operation 0.03 CL 2.5 Max ESR Boundary 0.5 0.4 Region of Best Stability 0.3 ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÏÏÏ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÏÏÏ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÏÏÏ ÎÎÎÎÎÎÎÎÎÎÎÎ ÏÏÏ ÎÎÎÎÎÎÎÎÎÎÎÎ ÏÏÏ ÏÏÏ ÎÎÎÎÎÎÎÎÎÎÎÎ ÏÏÏ ÏÏÏ ÎÎÎÎÎÎÎÎÎÎÎÎ ÏÏÏ ÏÏÏ ÎÎÎÎÎÎÎÎÎÎÎÎ ÏÏÏ ÏÏÏ ÎÎÎÎÎÎÎÎÎÎÎÎ ÏÏÏ ÎÎÎÎÎÎÎÎÎÎÎÎ ÏÏÏ ÏÏÏ ÏÏÏ ÎÎÎÎÎÎÎÎÎÎÎÎ ÏÏÏ ÏÏÏ ÎÎÎÎÎÎÎÎÎÎÎÎ ÏÏÏ Not Recommended Recommended Min ESR Potential Instability 0.035 Stability − Equivalent Series Resistance (ESR) - & 0.04 CL = 10 µF CI = 0.1 µF f = 120 Hz 1000 µF Region of Best Stability 0.025 400 µF 0.02 200 µF 0.015 100 µF 0.2 Min ESR Boundary 0.1 0.01 0.005 Potential Instability Region 0 0 0.1 0.2 0.3 0.4 IL - Load Current Rang e - A Figure 2. Copyright © 2005–2011, Texas Instruments Incorporated 0.5 0 0 22 µF 10 µF 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 1/ESR Figure 3. 7 TL750Mxx-Q1, TL751Mxx-Q1 SGLS312J – SEPTEMBER 2005 – REVISED JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS Table 2. Table of Graphs FIGURE Transient input voltage vs Time 4 Output voltage vs Input voltage 5 Input current vs Input voltage Dropout voltage vs Output current 8 Quiescent current vs Output current 9 IO = 10 mA 6 IO = 100 mA 7 Load transient response 10 Line transient response 11 TRANSIENT INPUT VOLTAGE vs TIME OUTPUT VOLTAGE vs INPUT VOLTAGE 14 TJ = 25°C VI = 14 V + 46e(−t/0.230) for t ≥ 5 ms 50 40 30 tr = 1 ms 20 10 10 8 TL75xM08 6 TL75xM05 4 2 0 0 8 IO = 10 mA TJ = 25°C 12 VO − Output Voltage − V V I − Transient Input Voltage − V 60 100 200 300 400 500 600 0 0 2 4 6 8 10 t − Time − ms VI − Input Voltage − V Figure 4. Figure 5. 12 14 Copyright © 2005–2011, Texas Instruments Incorporated TL750Mxx-Q1, TL751Mxx-Q1 SGLS312J – SEPTEMBER 2005 – REVISED JUNE 2011 www.ti.com INPUT CURRENT vs INPUT VOLTAGE INPUT CURRENT vs INPUT VOLTAGE 200 350 IO = 10 mA TJ = 25°C 180 IO = 100 mA TJ = 25°C 300 100 60 40 TL75_M08 80 200 150 TL75_M08 120 250 TL75_M05 I I − Input Current − mA 140 TL75_M05 I I − Input Current − mA 160 100 50 20 0 0 2 4 6 8 10 12 0 14 0 2 4 VI − Input Voltage − V 6 8 10 12 14 250 350 VI − Input Voltage − V Figure 6. Figure 7. DROPOUT VOLTAGE vs OUTPUT CURRENT QUIESCENT CURRENT vs OUTPUT CURRENT 250 12 TJ = 25°C TJ = 25°C VI = 14 V 225 IQ − Quiescent Current − mA Dropout Voltage − mV 10 200 175 150 125 100 8 6 4 2 75 50 0 50 100 150 200 IO − Output Current − mA Figure 8. Copyright © 2005–2011, Texas Instruments Incorporated 250 300 0 0 20 40 60 80 100 150 IO − Output Current − mA Figure 9. 9 TL750Mxx-Q1, TL751Mxx-Q1 SGLS312J – SEPTEMBER 2005 – REVISED JUNE 2011 www.ti.com VO − Output Voltage − mV 20 mV/DIV 200 100 0 − 100 − 200 150 VI(NOM) = VO + 1 V ESR = 2 CL = 10 µF TJ = 25°C 100 50 0 0 50 100 150 200 t − Time − µs Figure 10. 10 LINE TRANSIENT RESPONSE VI(NOM) = VO + 1 V ESR = 2 IL = 20 mA CL = 10 µF TJ = 25°C VIN − Input Voltage − V 1 V/DIV IO − Output Current − mA VO − Output Voltage − mV LOAD TRANSIENT RESPONSE 250 300 350 0 20 40 60 80 100 150 250 350 t − Time − µs Figure 11. Copyright © 2005–2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 21-Apr-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TL750M05QKTTRQ1 ACTIVE DDPAK/ TO-263 KTT 3 500 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR TL750M05QKVURQ1 ACTIVE PFM KVU 3 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR TL750M08QKVURQ1 ACTIVE PFM KVU 3 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR TL750M12QKTTRQ1 ACTIVE DDPAK/ TO-263 KTT 3 500 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR TL750M12QKVURQ1 ACTIVE PFM KVU 3 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR TL751M05QKTTRQ1 ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR TL751M05QKVURQ1 ACTIVE PFM KVU 5 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR TL751M08QKTTRQ1 ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR TL751M08QKVURQ1 ACTIVE PFM KVU 5 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR TL751M12QKTTRQ1 ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR TL751M12QKVURQ1 ACTIVE PFM KVU 5 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 21-Apr-2012 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF TL750M05-Q1, TL750M08-Q1, TL750M12-Q1, TL751M05-Q1 : • Catalog: TL750M05, TL750M08, TL750M12, TL751M05 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Apr-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TL750M05QKVURQ1 Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.9 10.5 2.7 8.0 16.0 Q2 PFM KVU 3 2500 330.0 16.4 TL750M08QKVURQ1 PFM KVU 3 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2 TL750M12QKTTRQ1 DDPAK/ TO-263 KTT 3 500 330.0 24.4 10.6 15.8 4.9 16.0 24.0 Q2 TL750M12QKVURQ1 PFM KVU 3 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2 TL751M05QKVURQ1 PFM KVU 5 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2 TL751M08QKTTRQ1 DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.6 15.8 4.9 16.0 24.0 Q2 TL751M08QKVURQ1 PFM KVU 5 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2 TL751M12QKTTRQ1 DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.6 15.8 4.9 16.0 24.0 Q2 TL751M12QKVURQ1 PFM KVU 5 2500 330.0 16.4 6.9 10.5 2.7 8.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Apr-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL750M05QKVURQ1 PFM KVU 3 2500 340.0 340.0 38.0 TL750M08QKVURQ1 PFM KVU 3 2500 340.0 340.0 38.0 TL750M12QKTTRQ1 DDPAK/TO-263 KTT 3 500 340.0 340.0 38.0 TL750M12QKVURQ1 PFM KVU 3 2500 340.0 340.0 38.0 TL751M05QKVURQ1 PFM KVU 5 2500 340.0 340.0 38.0 TL751M08QKTTRQ1 DDPAK/TO-263 KTT 5 500 340.0 340.0 38.0 TL751M08QKVURQ1 PFM KVU 5 2500 340.0 340.0 38.0 TL751M12QKTTRQ1 DDPAK/TO-263 KTT 5 500 340.0 340.0 38.0 TL751M12QKVURQ1 PFM KVU 5 2500 340.0 340.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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