CADEKA TMC2111AR3C1

www.cadeka.com
TMC2011A/2111A
Variable-Length Shift Register
Features
Applications
• Low power CMOS
• TMC2011A is a pin compatible replacement for the
TDC1011 and TMC2011
• TMC2211A is a pin compatible replacement for the
TMC2111
• Inputs and outputs are TTL compatible
• DC–40MHz clock rate
• Selectable delay lengths (TMC2011A: 3 to 18 stages,
TMC2111A: 1 to 16 stages)
• Special 4-bit wide mixed-delay mode (TMC2011A)
• Available in 24-pin CERDIP and plastic DIP and 28-lead
Plastic Leadless Chip Carrier
•
•
•
•
•
•
Video filtering
High speed data registers
Local storage registers
Digital delay lines
Television special effects
Pipeline register
Description
The TMC2011A and TMC2111A are high-speed, byte-wide
shift registers with programmable delay lengths.
The TMC2011A can be programmed to any length between
3 and 18 stages. It offers a special split-word mode which
allows for mixed delay lengths. The TMC2011A, constructed in low-power CMOS, is pin and function compatible
with the bipolar TDC1011.
The TMC2111A is a byte-wide shift register that can be programmed to lengths of 1 to 16 stages.
The TMC2011A and TMC2111A are fully synchronous,
with all operations controlled by a single master clock. Input
and output registers are positive-edge triggered D-type flipflops. The length and mode controls are also registered. Both
devices operate with a maximum clock rate of 40 MHz.
Fabricated in a submicron CMOS process, the TMC2011A
and TMC2111A are TTL-compatible, and are available in
24-pin CERDIP and Plastic DIP packages as well as a
28-lead Plastic Leadless Chip Carrier.
Block Diagrams
TMC2011A
DI3-0
R1
4
TMC2111A
R2
R3
R16
4
RL
4
RI
MC
CLK
R14
8
4
4
4-Bit Wide
1 of 16 Selector
4
4
4
R15
8
8
4
4-Bit Wide
1 of 16 Selector
4
R1
8
4
4
L3-0
DI7-0
R17
R18
R18
4
4
4
4
DO3-0
DO7-4
L3-0
CLK
4
RL
4
8
8-Bit Wide
1 of 16 Selector
8
R16
8
8
DO7-0
65-2011A-02
4
4
DI7-4
4
R1
R2
R3
R16
R17
65-2011A-01
Rev. 1.1.0
TMC2011A/2111A
PRODUCT SPECIFICATION
Functional Description
The TMC2011A consists of two 4-bit wide, programmable
length shift registers. The TMC2111A consists of a single
8-bit wide, programmable length shift register. The internal
registers of each device share control signals and a common
clock.
Pin Assignments
24 Lead DIP (B2, N2) Packages
DO0
DI0
DI1
DO1
DI1
DO1
DI2
DO2
DI2
DO2
DI3
DO3
DI3
DO3
1
L2
TMC2011A
L0
24
L1
VDD
1
24
L0
L3
L1
DO0
L2
TMC2111A
DI0
L3
GND
VDD
CLK
MC
CLK
GND
DI4
DO4
DI4
DO4
DI5
DO5
DI5
DO5
DO6
DI6
DO7
DI7
DI6
DI7
12
13
GND
DO6
12
13
DO7
65-2011A-03
DI2
DI1
DI0
DO0
DO1
DO2
DO3
DI2
DI1
DI0
DO0
DO1
DO2
DO3
28 Lead PLCC (R3) Package
DI5
DI6
DI7
DO7
DO6
DO5
DO4
TMC2011A
1 28
NC
L2
L3
GND
GND
MC
NC
DI3
L0
L1
VDD
CLK
DI4
NC
TMC2111A
DI5
DI6
DI7
DO7
DO6
DO5
DO4
1 28
DI3
L0
L1
VDD
CLK
DI4
NC
65-2011A-04
2
NC
L2
L3
GND
GND
MC
NC
PRODUCT SPECIFICATION
TMC2011A/2111A
Pin Descriptions – TMC2011A
Pin Number
Pin Name
DIP
PLCC
Pin Function Description
VDD
7
8
GND
18
21,22
12,11,10,
9,4,3,2,1
14,13,12,
10,5,4,3,2
Data Input. Eight inputs are provided for the data, which pass through the
shift register unchanged. The eight inputs on the TMC2011A are divided
into two groups of four bits to allow mixed delay operation. The lengths of
these two groups are different when the Mode Control (MC) is HIGH (see
Table 1). When MC is LOW both groups have equal delays.
13,14,15,
16,21,22,
23,24
15,16,17,
18,26,27,
28,1
Data Output. The outputs of the shift register are delayed relative to the
input signals. The amount of the delay is programmable (see Table 1).
The outputs remain valid for a minimum of tHO nanoseconds after the
leading edge of CLK. This allow the data to be latched into circuits with
non-zero hold time requirements.
CLK
8
9
Master Clock. All inputs and outputs are synchronous and operate from a
single master clock. All operations occur on the rising edge of the master
clock.
L3-0
19,20,6,5
23,24,7,6
Length Select. The length select input is used to determine the register
delay of the TMC2011A. This input is registered and affects the output tDO
after the clock edge after it is input to the device (see Timing Diagram).
Delay lengths are specified in Table 1.
MC
17
20
Mode Control. The Mode Control is used to select the special 4-bit wide
split mode. When HIGH, the delay on DO7-4 is fixed at 18 stages, while
DO3-0 have the delay specified by the length select. When MC is LOW, all
eight bits have equal delays as specified by the length select.
Power
Supply Voltage. The TMC2011A and operates from a single +5V supply.
All power and ground lines must be connected.
Ground. The TMC2011A operates from a single +5V supply. All power
and ground lines must be connected.
Data Inputs
DI7-0
Data Outputs
DO7-0
Controls
3
TMC2011A/2111A
PRODUCT SPECIFICATION
Pin Descriptions – TMC2111A
Pin Number
Pin Name
DIP
PLCC
Pin Function Description
VDD
7
8
GND
17,18
20,21,22
Ground. The TMC2111A operates from a single +5V supply. All power
and ground lines must be connected.
12,11,10,
9,4,3,2,1
14,13,12,
10,5,4,3,2
Data Input. Eight inputs are provided for the data, which pass through the
shift register unchanged. The TMC2111A consists of a single group of
eight bits with all data bits having equal delays.
13,14,15,
16,21,22,
23,24
15,16,17,
18,26,27,
28,1
Data Output. The outputs of the shift register are delayed relative to the
input signals. The amount of the delay is programmable (see Table 1).
The outputs remain valid for a minimum of tHO nanoseconds after the
leading edge of CLK. This allow the data to be latched into circuits with
non-zero hold time requirements.
CLK
8
9
Master Clock. All inputs and outputs are synchronous and operate from a
single master clock. All operations occur on the rising edge of the master
clock.
L3-0
19,20,6,5
23,24,7,6
Length Select. The length select input is used to determine the register
delay of the TMC2111A. This input is registered and affects the output tDO
after the clock edge after it is input to the device (see Timing Diagram).
Delay lengths are specified in Table 1.
Power
Supply Voltage. The TMC2111A operates from a single +5V supply. All
power and ground lines must be connected.
Data Inputs
DI7-0
Data Outputs
DO7-0
Controls
Table 1. Programming Length Controls
TMC2011A
Input Code
4
Mode (MC) =0
Mode (MC) =1
TMC2111A
L3
L2
L1
L0
DO3-0 Length
DO7-4 Length
DO3-0 Length
DO7-4 Length
DO7-0 Length
0
0
0
0
3
3
3
18
1
0
0
0
1
4
4
4
18
2
0
0
1
0
5
5
5
18
3
0
0
1
1
6
6
6
18
4
0
1
0
0
7
7
7
18
5
0
1
0
1
8
8
8
18
6
0
1
1
0
9
9
9
18
7
0
1
1
1
10
10
10
18
8
1
0
0
0
11
11
11
18
9
1
0
0
1
12
12
12
18
10
1
0
1
0
13
13
13
18
11
1
0
1
1
14
14
14
18
12
1
1
0
0
15
15
15
18
13
1
1
0
1
16
16
16
18
14
1
1
1
0
17
17
17
18
15
1
1
1
1
18
18
18
18
16
PRODUCT SPECIFICATION
TMC2011A/2111A
Absolute Maximum Ratings
(beyond which the device may be damaged)1
Parameter
Min
Supply Voltage
Input Voltage
Output, Applied
Voltage2
Output, Externally Forced Current3,4
Typ
Max
Unit
-0.5
7.0
V
-0.5
VDD + 0.5
V
-0.5
VDD + 0.5
V
-3.0
6.0
mA
1
sec
Output, Short Circuit Duration (single output in HIGH state to
ground)
Operating, Ambient Temperature
-20
Junction Temperature
Storage Temperature
-65
Lead Soldering (10 seconds)
110
°C
140
°C
150
°C
300
°C
Notes:
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if
Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
Operating Conditions
Parameter
VDD
Power Supply Voltage
fCLK
Clock frequency
Min
Nom
Max
Units
4.75
5.0
5.25
V
TMC2011A, 2111A
30
MHz
TMC2011A-1, 2111A-1
40
tPWH
CLK pulse width, HIGH
12
ns
tPWL
CLK pulse width, LOW
12
ns
tS
Input Data Set-up Time
6
ns
tH
Input Data Hold Time
1
ns
VIH
Input Voltage, Logic HIGH
DI7-0, L3-0, MC
2.0
V
CLK
2.6
VIL
Input Voltage, Logic LOW
0.8
V
IOH
Output Current, Logic HIGH
-2.0
mA
IOL
Output Current, Logic LOW
4.0
mA
TA
Ambient Temperature, Still Air
70
°C
0
5
TMC2011A/2111A
PRODUCT SPECIFICATION
Electrical Characteristics
Parameter
Conditions
Min
Typ
Max
Units
IDDU
Power Supply Current, Unloaded
VDD = Max, fCLK=30 MHz
VDD = Max, fCLK=40 MHz
30
40
mA
mA
IDDQ
Power Supply Current, Quiescent
VDD = Max, CLK = LOW
0.5
mA
CPIN
I/O Pin Capacitance
IIH
Input Current, HIGH
VDD = Max, VIN = VDD
IIL
Input Current, LOW
VDD = Max, VIN = 0 V
IOS
Short-Circuit Current
VOH
Output Voltage, HIGH
DO7-0, IOH = Max
VOL
Output Voltage, LOW
DO7-0, IOL = Max
5
pF
±10
mA
±10
mA
-100
mA
2.4
V
0.4
V
Max
Units
15
ns
Switching Characteristics
Parameter
6
Conditions
tDO
Output Delay Time
CLOAD = 25 pF
tHO
Output Hold Time
CLOAD = 25 pF
Min
3
Typ
ns
PRODUCT SPECIFICATION
TMC2011A/2111A
Timing Diagrams
1/f
CLK
1
2
tS
MC, L3-0
3
4
5
tH
Data
N+L-1
Data
N+L
Data
N+L+1
Data
N+L+2
Controls
Controls
Controls
Controls
DI7-0
tS
tPWL
tPWH
tH
Controls
tHO
Data
N-1
DO7-0
tDO
Data
N
Data
N+1
Data
N+2
L is Length from Table 1.
65-2011A-05
Figure 1. Preset Length Controls
CLK
DI7-0
L3-0
Data
10
0010
Data
11
Data
12
Data
13
Data
14
Data
15
Data
16
0010
0011
0011
0011
0011
0011
TMC2011A
DO7-0 (MC=0)
Data
5
Data
6
Data
7
Data
8
Data
8
Data
9
Data
10
TMC2111A
DO3-0 (MC=1)
Data
7
Data
8
Data
9
Data
10
Data
10
Data
11
Data
12
65-2011A-06
Figure 2. Length Control Operation
Equivalent Circuits
VDD
VDD
p
p
Data or
Control
Input
Output
n
n
27011B
27014B
GND
Figure 3. Equivalent Digital Input Circuit
GND
Figure 4. Equivalent Digital Output Circuit
7
TMC2011A/2111A
Notes:
8
PRODUCT SPECIFICATION
PRODUCT SPECIFICATION
TMC2011A/2111A
Mechanical Dimensions
24-Lead Ceramic DIP Package
Inches
Symbol
Min.
A
b1
b2
c1
D
E
e
eA
L
Q
s1
a
Millimeters
Max.
—
.200
.014
.023
.045
.065
.008
.015
—
1.280
.220
.310
.100 BSC
.300 BSC
.125
.200
.015
.060
.005
—
90¡
105¡
Min.
Notes:
Notes
1. Index area: a notch or a pin one identification mark shall be located
adjacent to pin one. The manufacturer's identification shall not be
used as pin one identification mark.
Max.
—
5.08
.36
.58
1.14
1.65
.20
.38
—
32.51
5.59
7.87
2.54 BSC
7.62 BSC
3.18
5.08
.38
1.52
.13
—
90¡
105¡
8
2, 8
2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads
number 1, 12, 13 and 24 only.
8
4
3. Dimension "Q" shall be measured from the seating plane to the base
plane.
4
5
7
4. This dimension allows for off-center lid, meniscus and glass overrun.
5. The basic pin spacing is .100 (2.54mm) between centerlines. Each
pin centerline shall be located within ±.010 (.25mm) of its exact
longitudinal position relative to pins 1 and 24.
6. Applies to all four corners (leads number 1, 12, 13, and 24).
3
6
7. "eA" shall be measured at the center of the lead bends or at the
centerline of the leads when "a" is 90¡.
8. All leads – Increase maximum limit by .003 (.08mm) measured at the
center of the flat, when lead finish applied.
9. Twenty-two spaces.
D
1
12
NOTE 1
E
24
13
s1
e
eA
Q
A
a
c1
L
b2
b1
9
TMC2011A/2111A
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
24-Lead Plastic DIP Package
Inches
Symbol
A
A1
A2
B
B1
C
D
D1
Notes
Min.
Max.
Min.
Max.
—
.015
.115
.210
—
.195
—
.38
2.53
5.33
—
4.95
.014
.022
.045
.070
.008
.015
1.125
1.275
.005
—
.300
.325
.240
.280
.100 BSC
—
.430
.115
.160
24
E
E1
e
eB
L
N
Notes:
Millimeters
.36
.56
1.14
1.78
.20
.38
28.58
32.39
.13
—
7.62
8.26
6.10
7.11
2.54 BSC
—
10.92
2.92
4.06
24
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. "D" and "E1" do not include mold flashing. Mold flash or protrusions
shall not exceed .010 inch (0.25mm).
3. Terminal numbers are shown for reference only.
4. "C" dimension does not include solder finish thickness.
5. Symbol "N" is the maximum number of terminals.
4
2
2
5
D
12
1
13
24
E1
D1
E
e
A
A1
C
L
B1
10
B
eB
PRODUCT SPECIFICATION
TMC2011A/2111A
Mechanical Dimensions (continued)
28-Lead PLCC Package
Inches
Symbol
Min.
A
A1
A2
B
B1
D/E
D1/E1
D3/E3
e
J
ND/NE
N
ccc
Max.
.165
.180
.090
.120
.020
—
.013
.021
.026
.032
.485
.495
.450
.456
.300 BSC
.050 BSC
.042
.048
7
28
—
.004
Notes:
Millimeters
Min.
Notes
1. All dimensions and tolerances conform to ANSI Y14.5M-1982
Max.
4.19
4.57
2.29
3.05
.51
—
.33
.53
.66
.81
12.32
12.57
11.43
11.58
7.62 BSC
1.27 BSC
1.07
1.22
7
28
—
0.10
2. Corner and edge chamfer (J) = 45¡
3. Dimension D1 and E1 do not include mold protrusion. Allowable
protrusion is .101" (.25mm)
3
2
E
E1
D
J
D1
D3/E3
B1
J
e
A
A1
A2
B
–C–
LEAD COPLANARITY
ccc C
11
TMC2011A/2111A
PRODUCT SPECIFICATION
Ordering Information
Product
Number
Temperature
Range
Speed
Grade
Screening
Package
Package
Marking
TMC2011AB2C
0°C to 70°C
30 MHz
Commercial
24 Pin 0.3" CerDIP
2011AB2C
TMC2011AB2C1
0°C to 70°C
40 MHz
Commercial
24 Pin 0.3" CerDIP
2011AB2C1
TMC2011AN2C
0°C to 70°C
30 MHz
Commercial
24 Pin 0.3" Plastic DIP
2011AN2C
TMC2011AN2C1
0°C to 70°C
40 MHz
Commercial
24 Pin 0.3" Plastic DIP
2011AN2C1
TMC2011AR3C
0°C to 70°C
30 MHz
Commercial
28 Lead PLCC
2011AR3C
TMC2011AR3C1
0°C to 70°C
40 MHz
Commercial
28 Lead PLCC
2011AR3C1
TMC2111AB2C
0°C to 70°C
30 MHz
Commercial
24 Pin 0.3" CerDIP
2111AB2C
TMC2111AB2C1
0°C to 70°C
40 MHz
Commercial
24 Pin 0.3" CerDIP
2111AB2C1
TMC2111AN2C
0°C to 70°C
30 MHz
Commercial
24 Pin 0.3" Plastic DIP
2111AN2C
TMC2111AN2C1
0°C to 70°C
40 MHz
Commercial
24 Pin 0.3" Plastic DIP
2111AN2C1
TMC2111AR3C
0°C to 70°C
30 MHz
Commercial
28 Lead PLCC
2111AR3C
TMC2111AR3C1
0°C to 70°C
40 MHz
Commercial
28 Lead PLCC
2111AR3C1
5/20/98 0.0m 001
Stock#DS30002011A