UCC27200-Q1 UCC27201-Q1 www.ti.com .................................................................................................................................................. SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 120-V BOOT, 3-A PEAK, HIGH-FREQUENCY HIGH-SIDE/LOW-SIDE DRIVER FEATURES APPLICATIONS • Qualified for Automotive Applications • Specified from –40°C to 140°C • Drives Two N-Channel MOSFETs in High-Side/Low-Side Configuration • Maximum Boot Voltage 120 V • Maximum VDD Voltage 20 V • On-Chip 0.65-V VF, 0.6-Ω RD Bootstrap Diode • Greater than 1 MHz of Operation • 20-ns Propagation Delay Times • 3-A Sink, 3-A Source Output Currents • 8-ns Rise/7-ns Fall Time with 1000-pF Load • 1-ns Delay Matching • Undervoltage Lockout for High-Side and Low-Side Driver • 1 2 • • • • • • Power Supplies for Telecom, Datacom, and Merchant Markets Half-Bridge Applications and Full-Bridge Converters Isolated Bus Architecture Two-Switch Forward Converters Active-Clamp Forward Converters High-Voltage Synchronous-Buck Converters Class-D Audio Amplifiers DESCRIPTION The UCC27200/1 family of high-frequency N-channel MOSFET drivers include a 120-V bootstrap diode and high-side/low-side driver with independent inputs for maximum control flexibility. This allows for N-channel MOSFET control in half-bridge, full-bridge, two-switch forward, and active clamp forward converters. The low-side and the high-side gate drivers are independently controlled and matched to 1 ns between the turn-on and turn-off of each other. An on-chip bootstrap diode eliminates the external discrete diodes. Undervoltage lockout is provided for both the high-side and the low-side drivers, forcing the outputs low if the drive voltage is below the specified threshold. Two versions of the UCC2720x are offered – the UCC27200 has high-noise-immune CMOS input thresholds, and the UCC27201 has TTL-compatible thresholds. Both devices are offered in the 8-pin PowerPad™ SOIC (DDA) package. Simplified Application Diagram +12V +100V SECONDARY SIDE CIRCUIT V DD HB DRIVE HI LI CONTROL HI PWM CONTROLLER HO HS DRIVE LO LO UCC27200/1 VSS ISOLATION AND FEEDBACK 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPad is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated UCC27200-Q1 UCC27201-Q1 SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 .................................................................................................................................................. www.ti.com ORDERING INFORMATION (1) INPUT COMPATIBILITY TJ –40°C to 140°C (1) (2) CMOS TTL PACKAGE (2) PowerPad – DDA Reel of 2500 TOP-SIDE MARKING ORDERABLE PART NUMBER UCC27200QDDARQ1 27200Q UCC27201QDDARQ1 27201Q For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. ABSOLUTE MAXIMUM RATINGS (1) (2) over operating free-air temperature (unless otherwise noted) VDD Supply voltage range VLI, VHI Input voltages on LI and HI VLO –0.3 V to 20 V –0.3 V to 20 V DC Output voltage on LO VHO Output voltage on HO VHS HS voltage range VHB HB voltage range –0.3 V to VDD + 0.3 V Repetitive pulse < 100 ns –2 V to VDD + 0.3 V DC VHS – 0.3 V to VHB + 0.3 V Repetitive pulse < 100 ns VHS – 2 V to VHB + 0.3 V, (VHB – VHS < 20) DC –1 V to 120 V Repetitive pulse < 100 ns –5 V to 120 V –0.3 V to 120 V HB-HS voltage range –0.3 V to 20 V TJ Operating virtual-junction temperature range –40°C to 150°C Tstg Storage temperature range –65°C to 150°C Tlead Lead temperature Soldering, 10 seconds 300°C PD Power dissipation TA = 25°C (3) 2.7 W (1) (2) (3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to VSS. Currents are positive into, negative out of the specified terminal. This data was taken using the JEDEC proposed high-K test PCB (See Thermal Characteristics for details). RECOMMENDED OPERATING CONDITIONS VDD VHS VHB Supply voltage range MIN NOM MAX 8 12 17 HS voltage –1 105 HS voltage (repetitive pulse <100 ns) –5 110 VHS + 8, VDD – 1 VHS + 17, 115 HB voltage Voltage slew rate on HS TJ ESD 2 Operating junction temperature –40 Electrostatic discharge protection Submit Documentation Feedback UNIT V V V 50 V/ns 140 °C Human-Body Model (HBM) 2000 Charged-Device Model (CDM) 1000 V Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200-Q1 UCC27201-Q1 UCC27200-Q1 UCC27201-Q1 www.ti.com .................................................................................................................................................. SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 THERMAL CHARACTERISTICS over operating free-air temperature range, maximum power dissipation at ambient temperature: PD = (150 – TA)/θJA (unless otherwise noted) (1) PACKAGE θJA (JUNCTION TO AMBIENT) θJC (JUNCTION TO CASE) θJP (JUNCTION TO THERMAL PAD) DDA (1) 46°C/W 71°C/W 4.8°C/W Test board conditions: a. 3-in × 3-in, four layers, 0.062-in thickness b. 2-oz copper traces located on the top and bottom of the PCB c. 2-oz copper ground planes on the internal two layers d. Six thermal vias in the PowerPad area under the device package Figure 1. Wirebond Life Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200-Q1 UCC27201-Q1 Submit Documentation Feedback 3 UCC27200-Q1 UCC27201-Q1 SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 .................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range, VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TA = TJ = –40°C to 140°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply Currents IDD VDD quiescent current VLI = VHI = 0 UCC27200 0.8 2.5 4 3.8 5.5 mA IDDO VDD operating current IHB Boot voltage quiescent current VLI = VHI = 0 V 0.4 0.8 mA IHBO Boot voltage operating current f = 500 kHz, CLOAD = 0 2.5 4 mA IHBS HB to VSS quiescent current VHS = VHB = 110 V 0.000 5 1 µA IHBSO HB to VSS operating current f = 500 kHz, CLOAD = 0 UCC27201 f = 500 kHz, CLOAD = 0 0.4 0.1 mA mA Input VHIT Input rising threshold UCC27200 VLIT Input falling threshold UCC27200 VIHYS Input voltage hysteresis UCC27200 VHIT Input voltage threshold UCC27201 VLIT Input voltage threshold UCC27201 VIHYS Input voltage hysteresis UCC27201 RIN Input pulldown resistance 5.8 3 V V 0.4 V 1.7 0.8 8 5.4 2.5 V 1.6 V 100 mV 100 200 350 kΩ 6.2 7.1 7.8 V Undervoltage Lockout (UVLO) Protection VDD rising threshold VDD threshold hysteresis 0.5 VHB rising threshold 5.8 VHB threshold hysteresis 6.7 V 7.2 0.4 V V Bootstrap Diode VF Low-current forward voltage IVDD – HB = 100 µA 0.65 0.85 VFI High-current forward voltage IVDD – HB = 100 mA 0.85 1.1 RD Dynamic resistance, ΔVF/ΔI IVDD – HB = 100 mA and 80 mA 0.6 1.0 Ω V V LO Gate Driver VLOL VLOH Low level output voltage ILO = 100 mA 0.18 0.4 TJ = –40°C to 125°C 0.25 0.4 TJ = –40°C to 140°C 0.25 0.42 High level output voltage ILO = –100 mA, VLOH = VDD – VLO Peak pullup current VLO = 0 V 3 A Peak pulldown current VLO = 12 V 3 A V HO Gate Driver VHOL VHOH 4 Low-level output voltage IHO = 100 mA 0.18 0.4 TJ = –40°C to 125°C 0.25 0.4 TJ = –40°C to 140°C 0.25 0.42 V High-level output voltage IHO = –100 mA, VHOH = VHB – VHO, Peak pullup current VHO = 0 V 3 A Peak pulldown current VHO = 12 V 3 A Submit Documentation Feedback V Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200-Q1 UCC27201-Q1 UCC27200-Q1 UCC27201-Q1 www.ti.com .................................................................................................................................................. SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TA = TJ = –40°C to 140°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Propagation Delays TDLFF VLI falling to VLO falling CLOAD = 0 TDHFF VHI falling to VHO falling CLOAD = 0 TDLRR TDHRR VLI rising to VLO rising CLOAD = 0 VHI rising to VHO rising CLOAD = 0 TJ = –40°C to 125°C 20 45 ns TJ = –40°C to 140°C 20 50 ns TJ = –40°C to 125°C 20 45 ns TJ = –40°C to 140°C 20 50 ns TJ = –40°C to 125°C 20 45 ns TJ = –40°C to 140°C 20 50 ns TJ = –40°C to 125°C 20 45 ns TJ = –40°C to 140°C 20 50 ns Delay Matching TMON LI ON, HI OFF 1 7 ns TMOFF LI OFF, HI ON 1 7 ns Output Rise and Fall Time tR LO, HO CLOAD = 1000 pF 8 tF LO, HO CLOAD = 1000 pF 7 ns tR LO, HO (3 V to 9 V) CLOAD = 0.1 µF 0.35 0.6 µs tF LO, HO (3 V to 9 V) CLOAD = 0.1 µF 0.3 0.6 µs 50 ns ns Miscellaneous Minimum input pulse width that changes the output IF = 20 mA, IREV = 0.5 A (1) (2) Bootstrap diode turn-off time (1) (2) 20 ns Typical values for TA = 25°C IF: Forward current applied to bootstrap diode. IREV: Reverse current applied to bootstrap diode. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200-Q1 UCC27201-Q1 Submit Documentation Feedback 5 UCC27200-Q1 UCC27201-Q1 SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 .................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS UCC27200 OPERATING CURRENT vs FREQUENCY UCC27201 OPERATING CURRENT vs FREQUENCY 10.0 10.0 VDD = 12 V No Load on Outputs 150oC 125oC 1.0 25oC o -40 C 125oC 1.0 -40oC 0.1 0.1 100 10 10 1000 100 1000 Frequency - kHz Frequency - kHz Figure 2. Figure 3. BOOT VOLTAGE OPERATING CURRENT vs FREQUENCY HB TO VSS OPERATING CURRENT vs FREQUENCY 10.0 1.0 HB = 12 V No Load on Outputs IHBSO - Operating Current - mA HB = 12 V No Load on Outputs IHBO - Operating Current - mA 150oC 25oC IDDO - Operating Current - mA IDDO - Operating Current - mA VDD = 12 V No Load on Outputs 150oC o 125 C 1.0 25oC -40oC 0.1 150oC 0.01 25oC 125oC 0.1 -40oC 0.001 10 100 1000 100 10 Frequency - kHz Figure 4. 6 Submit Documentation Feedback 1000 Frequency - kHz Figure 5. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200-Q1 UCC27201-Q1 UCC27200-Q1 UCC27201-Q1 www.ti.com .................................................................................................................................................. SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 TYPICAL CHARACTERISTICS (continued) UCC27200 INPUT THRESHOLD vs SUPPLY VOLTAGE UCC27201 INPUT THRESHOLD vs SUPPLY VOLTAGE 2.0 T = 25oC T = 25oC HI, LI - Input Threshold Voltage - V HI, LI - Input Threshold Voltage/VDD Voltage - % 50 Rising 48 46 Falling 44 42 1.8 Rising Falling 1.6 1.4 1.2 1.0 40 8 10 12 14 16 18 8 20 10 VDD - Supply Voltage - V 18 16 Figure 6. Figure 7. UCC27200 INPUT THRESHOLD vs TEMPERATURE UCC27201 INPUT THRESHOLD vs TEMPERATURE 50 20 2.0 VDD = 12 V VDD = 12 V HI, LI - Input Threshold Voltage - V HI, LI - Input Threshold Voltage/VDD Voltage - % 14 12 VDD - Supply Voltage - V 48 Rising 46 Falling 44 42 40 1.8 Rising 1.6 Falling 1.4 1.2 1.0 -50 -25 0 25 50 75 100 125 150 -50 -25 0 TA - Temperature - oC Figure 8. 25 50 75 TA - Temperature - 100 125 150 oC Figure 9. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200-Q1 UCC27201-Q1 Submit Documentation Feedback 7 UCC27200-Q1 UCC27201-Q1 SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 .................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) LO AND HO HIGH-LEVEL OUTPUT VOLTAGE vs TEMPERATURE LO AND HO LOW-LEVEL OUTPUT VOLTAGE vs TEMPERATURE 0.45 0.45 ILO = IHO = -100 mA 0.35 VDD = VHB = 16 V VDD = VHB = 12 V 0.30 VDD = VHB = 8 V 0.25 0.20 0.15 0.10 ILO = IHO = 100 mA 0.40 VOL - LO/HO Output Voltage - V VOH - LO/HO Output Voltage - V 0.40 VDD = VHB = 20 V 0.35 VDD = VHB = 16 V 0.30 VDD = VHB = 12 V 0.25 VDD = VHB = 8 V 0.20 0.15 0.10 0.05 0.05 VDD = VHB = 20 V 0.0 0.0 -50 -25 0 25 50 75 100 125 -50 150 -25 0 25 50 75 100 125 150 TA - Temperature - oC TA - Temperature - oC Figure 10. Figure 11. UNDERVOLTAGE LOCKOUT THRESHOLD vs TEMPERATURE UNDERVOLTAGE LOCKOUT THRESHOLD HYSTERESIS vs TEMPERATURE 7.8 0.8 7.6 0.7 7.4 Hysteresis - V Threshold - V 0.6 VDD Rising Threshold 7.2 7.0 6.8 6.6 VDD UVLO Hysteresis 0.5 0.4 0.3 HB UVLO Hysteresis HB Rising Threshold 6.4 0.2 6.2 0.1 6.0 5.8 0 -50 -25 0 25 50 75 100 125 150 -50 -25 0 TA - Temperature - oC Figure 12. 8 Submit Documentation Feedback 25 50 75 100 125 150 TA - Temperature - oC Figure 13. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200-Q1 UCC27201-Q1 UCC27200-Q1 UCC27201-Q1 www.ti.com .................................................................................................................................................. SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 TYPICAL CHARACTERISTICS (continued) UCC27200 PROPAGATION DELAYS vs TEMPERATURE UCC27201 PROPAGATION DELAYS vs TEMPERATURE 36 36 VDD = VHD = 12 V 34 32 TDHRR 28 26 24 22 20 Propagation Delay - ns 32 30 Propagation Delay - ns VDD = VHB = 12 V 34 TDHFF TDLFF 18 30 28 26 24 22 TDLFF TDLRR 20 18 16 TDHFF 16 TDLRR 14 TDHRR 14 -50 -25 0 50 75 25 100 TA - Temperature - oC 125 150 -50 -25 0 25 50 75 100 125 150 TA - Temperature - oC Figure 14. Figure 15. UCC27200 PROPAGATION DELAY vs SUPPLY VOLTAGE UCC27201 PROPAGATION DELAY vs SUPPLY VOLTAGE 26 26 T = 25oC T = 25oC 24 Propagation Delay - ns Propagation Delay - ns 24 22 LI Falling 20 LI Rising HI Falling LI Falling 22 LI Rising 20 HI Rising HI Rising 18 HI Falling 16 18 8 10 12 14 16 VDD = VHB - Supply Voltage - V 18 20 8 12 10 14 16 18 20 VDD = VHB - Supply Voltage - V Figure 16. Figure 17. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200-Q1 UCC27201-Q1 Submit Documentation Feedback 9 UCC27200-Q1 UCC27201-Q1 SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 .................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) DELAY MATCHING vs TEMPERATURE OUTPUT CURRENT vs OUTPUT VOLTAGE 3.5 7 VDD = VHB = 12 V VDD = VHB = 12 V 3.0 Delay Matching - ns 5 4 UCC27200TMOFF 3 UCC27201TMOFF UCC27201TMON UCC27200TMON 2 ILO, IHO - Output Current - A 6 2.5 Pull-Down Current Pull-Up Current 2.0 1.5 1.0 0.5 1 0 0 0 -50 -25 0 25 50 75 100 125 2 4 150 8 6 10 12 VLO, VHO - Output Voltage - V TA - Temperature - oC Figure 18. Figure 19. DIODE CURRENT vs DIODE VOLTAGE QUIESCENT CURRENT vs SUPPLY VOLTAGE 100.0 700 Inputs Low T = 25oC 600 IDD, IHB - Supply Current - mA Diode Current - mA 10.0 1.0 0.1 500 IHB 400 300 IDD 200 0.01 100 0 0.001 0.5 0.6 0.7 0.8 Diode Voltage - V 0.9 0 8 4 Figure 20. 10 Submit Documentation Feedback 12 16 20 VDD, VHB - Supply Voltage - V Figure 21. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200-Q1 UCC27201-Q1 UCC27200-Q1 UCC27201-Q1 www.ti.com .................................................................................................................................................. SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 DEVICE INFORMATION DDA PACKAGE (TOP VIEW) A. VDD 1 8 LO HB 2 7 VSS HO 3 6 LI HS 4 5 HI Thermal Pad The VSS pin and the exposed thermal die pad are internally connected. TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION VDD 1 I Positive supply to the lower gate driver. Decouple this pin to VSS (GND). Typical decoupling capacitor range is 0.22 µF to 1.0 µF. HB 2 I High-side bootstrap supply. The bootstrap diode is on-chip, but the external bootstrap capacitor is required. Connect positive side of the bootstrap capacitor to this pin. Typical range of HB bypass capacitor is 0.022 µF to 0.1 µF, however, the value is dependant on the gate charge of the high-side MOSFET. HO 3 O High-side output. Connect to the gate of the high-side power MOSFET. HS 4 I High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. HI 5 I High-side input LI 6 I Low-side input VSS 7 O Negative supply terminal for the device which is generally grounded LO 8 O Low-side output. Connect to the gate of the low-side power MOSFET. PowerPAD Electrically referenced to VSS (GND). Connect to a large thermal mass trace or GND plane to dramatically improve thermal performance. PAD Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200-Q1 UCC27201-Q1 Submit Documentation Feedback 11 UCC27200-Q1 UCC27201-Q1 SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 .................................................................................................................................................. www.ti.com FUNCTIONAL BLOCK DIAGRAM 2 HB 3 HO 4 HS 8 LO 7 VSS UVLO LEVEL SHIFT HI 5 VDD 1 UVLO LI 6 LI Input (HI, LI) HI TDLRR, TDHRR LO Output (HO, LO) TDLFF, TDHFF HO TMON TMOFF Figure 22. Timing Diagrams 12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200-Q1 UCC27201-Q1 UCC27200-Q1 UCC27201-Q1 www.ti.com .................................................................................................................................................. SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 APPLICATION INFORMATION Functional Description The UCC27200 and UCC27201 are high-side/low-side drivers. The high side and low side each have independent inputs, which allow maximum flexibility of input control signals in the application. The boot diode for the high-side driver bias supply is internal to the UCC27200 and UCC27201. The UCC27200 is the CMOS-compatible input version, and the UCC27201 is the TTL- or logic-compatible version. The high-side driver is referenced to the switch node (HS), which is typically the source pin of the high side MOSFET and drain pin of the low-side MOSFET. The low-side driver is referenced to VSS, which is typically ground. The functions contained are the input stages, UVLO protection, level shift, boot diode, and output driver stages. NOTE: The term UCC2720x applies to both the UCC27200 and UCC27201. Input Stages The input stages provide the interface to the PWM output signals. The input impedance of the UCC27200 is 200 kΩ nominal and input capacitance is approximately 2 pF. The 200 kΩ is a pulldown resistance to Vss (ground). The CMOS compatible input of the UCC27200 provides a rising threshold of 48% of VDD and falling threshold of 45% of VDD. The inputs of the UCC27200 are intended to be driven from 0 to VDD levels. The input stages of the UCC27201 incorporate an open drain configuration to provide the lower input thresholds. The input impedance is 200 kΩ nominal and input capacitance is approximately 4 pF. The 200 kΩ is a pulldown resistance to VSS (ground). The logic level compatible input provides a rising threshold of 1.7 V and a falling threshold of 1.6 V. Undervoltage Lockout (UVLO) The bias supplies for the high-side and low-side drivers have UVLO protection. VDD as well as VHB to VHS differential voltages are monitored. The VDD UVLO disables both drivers when VDD is below the specified threshold. The rising VDD threshold is 7.1 V with 0.5-V hysteresis. The VHB UVLO disables only the high-side driver when the VHB to VHS differential voltage is below the specified threshold. The VHB UVLO rising threshold is 6.7 V with 0.4-V hysteresis. Level Shift The level-shift circuit is the interface from the high-side input to the high-side driver stage, which is referenced to the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides excellent delay matching with the low-side driver. Boot Diode The boot diode necessary to generate the high-side bias is included in the UCC2720x family of drivers. The diode anode is connected to VDD and cathode connected to VHB. With the VHB capacitor connected to HB and the HS pins, the VHB capacitor charge is refreshed every switching cycle when HS transitions to ground. The boot diode provides fast recovery times, low diode resistance, and a voltage rating margin that allow for efficient and reliable operation. Output Stages The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance and high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The low-side output stage is referenced from VDD to VSS and the high-side is referenced from VHB to VHS. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200-Q1 UCC27201-Q1 Submit Documentation Feedback 13 UCC27200-Q1 UCC27201-Q1 SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 .................................................................................................................................................. www.ti.com Design Tips Switching the MOSFETs Achieving optimum drive performance at high frequency efficiently requires special attention to layout and minimizing parasitic inductances. Care must be taken at the driver die and package level as well as the PCB layout to reduce parasitic inductances as much as possible. Figure 23 shows the main parasitic inductance elements and current flow paths during the turn on and turn off of the MOSFET by charging and discharging its CGS capacitance. L bond wire L pin L trace 1 VDD I SOURCE Rsource Driver Output Stage Cvdd L pin L trace L bond wire Rg 8 LO I sink Rsink Cgs L pin L trace L bond wire 7 L trace Vss Figure 23. MOSFET Drive Paths and Circuit Parasitics 14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200-Q1 UCC27201-Q1 UCC27200-Q1 UCC27201-Q1 www.ti.com .................................................................................................................................................. SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 The ISOURCE current charges the CGS gate capacitor and the ISINK current discharges it. The rise and fall time of the voltage across the gate to source defines how quickly the MOSFET can be switched. Based on actual measurements, the analytical curves in Figure 24 and Figure 25 indicate the output voltage and current of the drivers during the discharge of the load capacitor. Figure 24 shows voltage and current as a function of time. Figure 25 indicates the relationship of voltage and current during fast switching. These figures demonstrate the actual switching process and limitations due to parasitic inductances. 12 11 12 11 10 10 9 8 9 6 8 5 7 4 3 LO Voltage, V LO Falling, V or A 7 2 1 0 1 2 5 4 3 2 3 4 5 6 1 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 0 1 t, ns Voltage 2 Current 3 2 1 0 1 2 3 4 5 LO Current, A Figure 24. Turn-Off Voltage and Current vs Time Figure 25. Turn-Off Voltage and Current Switching Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200-Q1 UCC27201-Q1 Submit Documentation Feedback 15 UCC27200-Q1 UCC27201-Q1 SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 .................................................................................................................................................. www.ti.com Turning off the MOSFET must be achieved as fast as possible to minimize switching losses. For this reason, the UCC2720x drivers are designed for high peak currents and low output resistance. The sink capability is specified as 0.18 V at 100-mA dc current, implying 1.8-Ω RDS(on). With 12-V drive voltage, no parasitic inductance, and a linear resistance, one would expect initial sink current amplitude of 6.7 A for both high-side and low-side drivers. Assuming a pure R-C discharge circuit of the gate capacitor, one would expect the voltage and current waveforms to be exponential. Due to the parasitic inductances and nonlinear resistance of the driver MOSFETs, the actual waveforms have some ringing, and the peak sink current of the drivers is approximately 3.3 A, as shown in Figure 19. The overall parasitic inductance of the drive circuit is estimated at 4 nH. Actual measured waveforms are shown in Figure 26 and Figure 27. As shown, the typical rise time of 8 ns and fall time of 7 ns is conservatively rated. Figure 26. VLO and VHO Rise Time, 1-nF Load, 5 ns/Div 16 Submit Documentation Feedback Figure 27. VLO and VHO Fall Time, 1-nF Load, 5-ns/Div Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200-Q1 UCC27201-Q1 UCC27200-Q1 UCC27201-Q1 www.ti.com .................................................................................................................................................. SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 Dynamic Switching of the MOSFETs The true behavior of MOSFETS presents a dynamic capacitive load primarily at the gate to source threshold voltage. Using the turn-off case as the example, when the gate to source threshold voltage is reached, the drain voltage starts rising, and the drain-to-gate parasitic capacitance couples charge into the gate, resulting in the turn-off plateau. The relatively low threshold voltages of many MOSFETS and the increased charge that must be removed (Miller charge) makes good driver performance necessary for efficient switching. An open-loop half-bridge power converter was utilized to evaluate performance in actual applications. The schematic of the half-bridge converter is shown in Figure 30. The turn-off waveforms of the UCC27200 driving two MOSFETs in parallel are shown in Figure 28 and Figure 29. Figure 28. VLO Fall Time in Half-Bridge Converter Figure 29. VHO Fall Time in Half-Bridge Converter Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200-Q1 UCC27201-Q1 Submit Documentation Feedback 17 UCC27200-Q1 UCC27201-Q1 SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 .................................................................................................................................................. www.ti.com 18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200-Q1 UCC27201-Q1 UCC27200-Q1 UCC27201-Q1 + + + www.ti.com .................................................................................................................................................. SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200-Q1 UCC27201-Q1 Submit Documentation Feedback 19 UCC27200-Q1 UCC27201-Q1 SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 .................................................................................................................................................. www.ti.com Figure 30. Open-Loop Half-Bridge Converter 20 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200-Q1 UCC27201-Q1 UCC27200-Q1 UCC27201-Q1 www.ti.com .................................................................................................................................................. SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 Delay Matching and Narrow Pulse Widths The total delays encountered in the PWM, driver, and power stage must be considered for a number of reasons, primarily for the delay in current limit response. Also to be considered are differences in delays between the drivers which can lead to various concerns depending on the topology. The sync-buck topology switching requires careful selection of dead time between the high- and low-side switches to avoid cross conduction and excessive body diode conduction. Bridge topologies can be affected by a resulting volt-sec imbalance on the transformer, if there is imbalance in the high- and low-side pulse widths in a steady-state condition. Narrow pulse width performance is an important consideration when transient and short circuit conditions are encountered. Although there may be relatively long steady state PWM output-driver-MOSFET signals, very narrow pulses may be encountered in soft start, large load transients, and short-circuit conditions. The UCC2720x driver family offers excellent performance in high- and low-side driver delay matching and narrow pulse width performance. The delay matching waveforms are shown in Figure 31 and Figure 32. The UCC2720x driver narrow pulse performance is shown in Figure 33 and Figure 34. Figure 31. VLO and VHO Rising Edge Delay Matching Figure 32. VLO and VHO Falling Edge Delay Matching Figure 33. 20-ns Input Pulse Delay Matching Figure 34. 10-ns Input Pulse Delay Matching Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200-Q1 UCC27201-Q1 Submit Documentation Feedback 21 UCC27200-Q1 UCC27201-Q1 SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 .................................................................................................................................................. www.ti.com Boot-Diode Performance The UCC2720x family of drivers internally incorporates the bootstrap diode necessary to generate the high-side bias. The characteristics of this diode are important to achieve efficient reliable operation. The dc characteristics to consider are VF and dynamic resistance. A low VF and high dynamic resistance results in a high forward voltage during charging of the bootstrap capacitor. The UCC2720x has a boot diode rated at 0.65-V VF and dynamic resistance of 0.6 Ω for reliable charge transfer to the bootstrap capacitor. The dynamic characteristics to consider are diode recovery time and stored charge. Diode recovery times that are specified with no conditions can be misleading. Diode recovery times at no forward current (IF) can be noticeably less than with forward current applied. The UCC2720x boot diode recovery is specified at 20 ns at IF = 20 mA, IREV = 0.5 A. At 0-mA IF, the reverse recovery time is 15 ns. Another less obvious consideration is how the stored charge of the diode is affected by applied voltage. On every switching transition when the HS node transitions from low to high, charge is removed from the boot capacitor to charge the capacitance of the reverse-biased diode. This is a portion of the driver power losses and it reduces the voltage on the HB capacitor. At higher applied voltages, the stored charge of the UCC2720x PN diode is often less than a comparable Schottky diode. Layout Recommendations To improve the switching characteristics and efficiency of a design, the following layout rules should be followed. • Locate the driver as close as possible to the MOSFETs. • Locate the VDD and VHB (bootstrap) capacitors as close as possible to the driver. • Pay close attention to the GND trace. Use the thermal pad of the DDA package as GND by connecting it to the VSS pin (GND). Note: The GND trace from the driver goes directly to the source of the MOSFET but should not be in the high current path of the MOSFET(S) drain or source current. • Use similar rules for the HS node as for GND for the high side driver. • Use wide traces for LO and HO closely following the associated GND or HS traces. Where possible, widths of 60 mil to 100 mil are preferred. • Use two or more vias if the driver outputs or SW node need to be routed from one layer to another. For GND, the number of vias should be a consideration of the thermal pad requirements as well as parasitic inductance. • Avoid LI and HI (driver input) going close to the HS node or any other high dV/dT traces that can induce significant noise into the relatively high-impedance leads. • Keep in mind that a poor layout can cause a significant drop in efficiency versus a good PCB layout and can even lead to decreased reliability of the whole system. 22 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200-Q1 UCC27201-Q1 UCC27200-Q1 UCC27201-Q1 www.ti.com .................................................................................................................................................. SLUS822A – JUNE 2008 – REVISED NOVEMBER 2008 Figure 35. Example Component Placement Additional References These references and links to additional information may be found at www.ti.com. 1. Additional layout guidelines for PCB land patterns may be found in application brief SLUA271. 2. Additional thermal performance guidelines may be found in application reports SLMA002 and SLMA004. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200-Q1 UCC27201-Q1 Submit Documentation Feedback 23 PACKAGE OPTION ADDENDUM www.ti.com 14-Jul-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp UCC27200QDDARQ1 ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR UCC27201QDDARQ1 ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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