UCC1806 UCC2806 UCC3806 SLUS272F -- FEBRUARY 2000 -- REVISED AUGUST 2006 LOW- POWER, DUAL-OUTPUT, CURRENT-MODE PWM CONTROLLER FEATURES D BiCMOS Version of UC3846 Family D 1.4-mA Maximum Operating Current D 100-μA Maximum Startup Current D ±0.5-A Peak Output Current D 125-ns Circuit Delay D Easier Parallelability D Improved Benefits of Current Mode Control for applications ranging from off-line power supplies to battery operated portable equipment. Dual high-current, MOSFET driving outputs and a fast current sense loop further enhance device versatility. DESCRIPTION These devices are available in multiple package options for both through-hole and surface mount applications; and in commercial, industrial, and military temperature ranges. The UCC3806 family of BiCMOS PWM controllers offers exceptionally improved performance with a familiar architecture. With the same block diagram and pinout of the popular UC3846 series, the UCC3806 line features increased switching frequency capability while greatly reducing the bias current used within the device. With a typical startup current of 50 μA and a well defined voltage threshold for turn-on, these devices are favored All the benefits of current mode control including simpler loop closing, voltage feed-forward, parallelability with current sharing, pulse-by-pulse current limiting, and push/pull symmetry correction are readily achievable with the UCC3806 series. The UCC1806 is specified for operation from --55°C to 125°C, the UCC2806 is specified for operation from --40°C to 85°C, and the UCC3806 is specified for operation from 0°C to 70°C. SIMPLIFIED APPLICATION DIAGRAM +VOUT +VIN 15 UC39431 13 VIN VC UCC3806 2 VREF INV 6 COMP 7 8 CT 5 NI AOUT 11 1 CURLIM BOUT 14 10 SYNC SHUT 16 DOWN 9 RT CS+ 4 CS-- GND 3 12 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999 -- 2006, Texas Instruments Incorporated www.ti.com 1 UCC1806 UCC2806 UCC3806 SLUS272F -- FEBRUARY 2000 -- REVISED AUGUST 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UCx806 UNIT Supply voltage, VIN VIN, low impedance 15 V Supply current, IIN VIN, high impedance 25 mA Output supply voltage VC 18 V Output current Analog input voltage range Continuous source or sink ± 200 Gate drive ± 500 SYNC ± 30 COMP ± 10 to --(self-limiting) CS--, CS+, NI, INV, SHUTDOWN mA --0.3 to (VIN + 0.3) V Storage temperature, Tstg --65 to 150 °C Operating temperature, TJ --55 to 150 °C 300 °C Lead temperature, Tsol, 1,6 mm (1/16 inch) from case for 10 seconds (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into and negative out of, the specified terminal. RECOMMENDED OPERATING CONDITIONS MIN Input voltage, VIN Operating junction temperature, TJ NOM 14.5 125 UCC2806 --40 85 UCC3806 0 70 Q OR L PACKAGE (TOP VIEW) 16 15 14 13 12 11 10 9 SHUTDOWN VIN BOUT VC GND AOUT SYNC RT VREF CURLIM NC SHUTDOWN VIN 1 2 3 4 5 6 7 8 CS-CS+ N/C NI INV 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 N/C -- No connection 2 www.ti.com V 8.0 --55 COMP CT N/C RT SYNC CURLIM VREF CS-CS+ NI INV COMP CT UNIT UCC1806 PACKAGE DESCRIPTION D, DW, J, M, N OR PW PACKAGE (TOP VIEW) MAX BOUT VC N/C GND AOUT °C C UCC1806 UCC2806 UCC3806 SLUS272F -- FEBRUARY 2000 -- REVISED AUGUST 2006 ORDERING INFORMATION PACKAGED DEVICES DESIGNATOR TYPE D SOIC 16 SOIC--16 DW SOICW 16 SOICW--16 J CDIP--16 TA = TJ OPTION QUANTITY -- 55°C to 125°C -- 40°C to 85°C 0°C to 70°C Tube 40 – UCC2806D – Reeled 2,500 – UCC2806DTR – Tube 40 – UCC2806DW UCC3806DW Reeled 2,000 – UCC2806DWTR UCC3806DWTR Tube 25 UCC1806J UCC2806J UCC3806J L CLCC--20 Tube 55 UCC1806L – – M SSOP--16 Reeled 2,500 – UCC2806MTR – N PDIP--16 Tube 25 – UCC2806N UCC3806N Tube 90 – UCC2806PW UCC3806PW Reeled 2,000 – UCC2806PWTR UCC3806PWTR Tube 46 – UCC2806Q UCC3806Q Reeled 1,000 – UCC2806QTR UCC3806QTR PW TSSOP 16 TSSOP--16 Q PLCC 20 PLCC--20 ELECTRICAL CHARACTERISTICS VIN = 12 V, RT = 33 kΩ, CT = 330 pF, CBYPASS on VREF = 0.01 μF, --55°C < TA < 125°C for the UCC1806, --40°C < TA < 85°C for the UCC2806, 0°C < TA < 70°C for the UCC3806, and TA = TJ (unless otherwise noted) TEST CONDITIONS MIN TYP MAX UCC1806 UCC2806 5.02 5.10 5.17 UCC3806 5.00 5.10 5.20 PARAMETER UNIT REFERENCE VREF Supply, UVLO, turn turn-on on Load regulation 0.2 mA ≤ IOUT ≤ 5 mA Total output variation (1)(2) Line, load, temperature Output noise voltage (2) 10 Hz ≤ fOSC ≤ 10 kHz, Long term stability (2) TA = 125°C, 3 --150 TJ = 25°C 70 1000 hours Output short circuit 25 150 5 --10 V mV μV 25 mV --30 mA 52 kHz OSCILLATOR Initial accuracy TJ = 25°C Temperature stability (2) T(min) ≤ TA ≤ T(max) Amplitude tDELAY Delay to output time Delay-to-output time, SYNC 42 47 2% 2.35 V UCC1806 UCC2806 VCT = 0 V, VRT = VREF 0.8 V ≤ VSYNC ≤ 2.0 V 50 125 UCC3806 VCT = 0 V, VRT = VREF 0.8 V ≤ VSYNC ≤ 2.0 V 50 100 www.ti.com ns 3 UCC1806 UCC2806 UCC3806 SLUS272F -- FEBRUARY 2000 -- REVISED AUGUST 2006 ELECTRICAL CHARACTERISTICS VIN = 12 V, RT = 33 kΩ, CT = 330 pF, CBYPASS on VREF = 0.01 μF, --55°C < TA < 125°C for the UCC1806, --40°C < TA < 85°C for the UCC2806, 0°C < TA < 70°C for the UCC3806, and TA = TJ (unless otherwise noted) TEST CONDITIONS PARAMETER MIN TYP MAX UNIT OSCILLATOR (continued) IDCHG Discharge current TJ = 25°C, VCT = 2.0 V VOL Low-level output voltage, SYNC IOUT = 1 mA VOH High-level output voltage, SYNC IOUT = --4 mA VIL Low-level input voltage, SYNC VCT = 0 V, VRT = VREF VIH High-level input voltage, SYNC VCT = 0 V, VRT = VREF ISYNC Input current, SYNC 2.5 mA 0.4 2.4 0.8 V 2.0 --1 1 μA ERROR AMPLIFIER Input offset voltage UCC1806 UCC2806 5 UCC3806 10 mV IBIAS Input bias current --1 μA IOFSET Input offset current 500 nA range(1) CMR Common mode AVOL Open loop gain 0 GBW bandwidth ICOMP_SINK Output sink current VID < --20 mV, VCOMP = 1 V 1 ICOMP_SRC Output source current VID < 20 mV, VCOMP = 3 V --80 VCOMP_L Low-level output voltage VID = --50 mV VCOMP_H High-level output voltage VID = --50 mV 1 V ≤ VOUT ≤ 4 V 80 VIN --2 100 V dB 1 MHz mA --120 μA 0.5 4.5 V CURRENT SENSE AMPLIFIER A Amplifier gain(3)(4) VCS-- = 0 V, Maximum differential input signal (VCS+ -- VCS-- ) VCURLIM = VNI = VREF, VINV = 0V Input offset voltage VCURLIM = VREF 2.75 3.00 3.35 1.1 V/V V UCC1806 UCC2806 VCURLIM = 0.5 V, VCOMP = OPEN 10 30 mV UCC3806 VCURLIM = 0.5 V, VCOMP = OPEN 10 50 mV CMRR Common mode rejection ratio PSRR Power supply rejection ratio 0 V ≤ VCM ≤ (VIN -- 3.5 V) 60 dB IBIAS Input bias current (3) VCURLIM = 0.5 V, VCOMP = OPEN --1 μA Input offset current (3) VCURLIM = 0.5 V, VCOMP = OPEN 1 μA Delay-to-output time (5) VNI = VREF, VINV = 0 V, VCURLIM = 2.75 V, (VCS+ -- VCS-- ) = 0 V to 1.5 V step 125 175 ns 0.5 0.6 V 56 dB CURRENT LIMIT ADJUST Current limit offset IBIAS VCS-- = VCS+ = 0 V, VCOMP = OPEN 1 Minimum latching current 300 Maximum non-latching current (1) (2) 4 0.4 Input bias current 200 200 Line range = 10 V to 15 V, load range = 0.2 mA to 5 mA Ensured by design. Not production tested. www.ti.com μA 80 UCC1806 UCC2806 UCC3806 SLUS272F -- FEBRUARY 2000 -- REVISED AUGUST 2006 ELECTRICAL CHARACTERISTICS VIN = 12 V, RT = 33 kΩ, CT = 330 pF, CBYPASS on VREF = 0.01 μF, --55°C to 125°C for the UCC1806, --40°C < TA < 85°C for the UCC2806, 0°C < TA < 70°C for the UCC3806, and TA = TJ (unless otherwise noted) SHUTDOWN TERMINAL Threshold voltage UCC1806 UCC2806 0.94 1.00 1.06 UCC3806 0.9 1.0 1.1 75 150 Input voltage range tDLY 0 Delay-to-output time V VIN 0 V ≤ VSHUTDOWN ≤ 1.3 V ns OUTPUT Output supply voltage Low level output voltage Low-level 2.5 UCC1806 UCC2806 UCC3806 High level output voltage High-level 15.0 ISINK = 20 mA 100 ISINK = 100 mA 0.4 1.1 ISINK = 20 mA 100 200 ISINK = 100 mA 0.4 1.1 ISRC = --20 mA 11.6 11.9 ISRC = --100 mA 11.0 11.6 300 tRISE Rise time TJ = 25°C, CLOAD = 1000 pF 35 65 tFALL Fall time TJ = 25°C, CLOAD = 1000 pF 35 65 7.5 8.0 V ns UNDERVOLTAGE LOCKOUT (UVLO) VSTART Startup threshold voltage 6.5 Threshold hysteresis ISTART Startup current I Operating supply current 0.75 VIN < VSTART VIN shunt voltage (1) (2) (3) (4) (5) IVIN = 10 mA 15.0 V V 50 100 μA 1.0 1.4 mA 17.5 Line range = 10 V to 15 V, load range = 0.2 mA to 5 mA Ensured by design. Not production tested. Parameters measured at trip point of latch with VNI = VREF , VINV = 0V. Amplifier gain defined as: G = delta change at COMP /delta change forced at CS+ delta voltage at CS+ = 0 to 1V Current-sense amplifier output is slew rate limited to provide noise immunity. THERMAL RESISTANCE TABLE (1) PACKAGE DESIGNATOR PACKAGE TYPE θJC (°C/W) θJA (°C/W) D SOIC--16 35 50 to 120(1) DW SOICW--16 27 50 to 100(1) 80 to 120 J CDIP--16 28 L CLCC--20 20 70 to 80 M SSOP--16 38 144 to 172(2) N PDIP--16 45 90(1) PW TSSOP--16 15 123 to 147(2) Q PLCC--20 34 43 to 75(1) in2 Specified θ JA (junction to ambient) is for devices mounted to 5 FR4 PC board with one ounce copper where noted. When resistance range is given, lower values are for 5 in2 aluminum PC board. Test PWB was 0.062 in thick and typically used 0.635 mm trace widths for power packages and 1.3 mm trace widths for non-power packages with a 100x100 mil probe land area at the end of each trace. (2) Modeled data. If value range given for θ JA, the lower value is for 3x3 inch1 oz internal copper ground plane, and the higher value is for 1x1 inch ground plane. All model data assumes only one trace for each non-fused lead. www.ti.com 5 UCC1806 UCC2806 UCC3806 SLUS272F -- FEBRUARY 2000 -- REVISED AUGUST 2006 TERMINAL FUNCTIONS TERMINAL PACKAGES NAME D/DW/J/M /N/PW L,Q AOUT 11 14 BOUT 14 18 COMP 7 CS-- 3 CS+ I/O DESCRIPTION O High current gate drive for the external MOSFETs High-current 9 O Output of the error amplifier 4 I Inverting input of the 3×, differential current sense amplifier 4 5 I Non-inverting input of the 3×, differential current sense amplifier CT 8 10 I Oscillator timing capacitor connection point CURLIM 1 2 I Programs the primary current limit threshold that determins latching or retry after an overcurrent situation GND 12 15 -- Reference ground and power ground for all functions of this device INV 6 8 I Inverting input of the error amplifier. NI 5 7 I Non-nverting input of the error amplifier. RT 9 12 I Connection point for the oscillator timing resistor SHUTDOWN 16 20 I Provided for enhanced protection. When SHUTDOWN is driven above 1 V, AOUT and BOUT are forced low. SYNC 10 13 I/O VC 13 17 I Input supply connection for the FET drive outputs. VIN 15 19 I Input supply connection for this device. VREF 2 3 O Reference output. Allows providing external synchronization with TTL compatible thresholds. DETAILED PIN DESCRIPTIONS AOUT and BOUT: AOUT and BOUT provide alternating high current gate drive for the external MOSFETs. Duty cycle can be varied from 0% to 50% where minimum dead time is a function of CT. Both outputs use MOS transistor switches with inherent anti-parallel body diodes to clamp voltage swings to the supply rails, allowing operation without the use of clamp diodes. COMP: COMP is the output of the error amplifier and the input of the PWM comparator. The error amplifier is a low output impedance, 2-MHz operational amplifier which allows sinking or sourcing of current at the COMP pin. The error amplifier is internally current limited, so that zero duty cycle can be commanded by externally forcing COMP to GND. CS--: CS-- is the inverting input of the 3× differential current sense amplifier. CS+: CS+ is the non-inverting input of the 3× differential current sense amplifier. CT: CT is the oscillator timing capacitor connection point, which is charged by the current set by RT. CT is discharged to GND through a 2.5-mA current sink. This causes a linear discharge of CT to 0 V which then initiates the next switching cycle. Dead time occurs during the discharge of CT, forcing AOUT and BOUT low. Switching frequency (fS) and dead time (tD) are approximated by: fS = 6 1 and t D = 956 × C T 1.96 × R T × C T + t D www.ti.com (1) UCC1806 UCC2806 UCC3806 SLUS272F -- FEBRUARY 2000 -- REVISED AUGUST 2006 DETAILED PIN DESCRIPTIONS (continued) CURLIM: CURLIM programs the primary current limit threshold and determines whether the device latches off or retries after an overcurrent condition. When a shutdown signal is generated, a 200-μA current source to ground pulls down on CURLIM. If the voltage on the pin remains above 350 mV the device remains latched and the power must be cycled to restart. If the voltage on the pin falls below 350 mV, the device attempts a restart. The voltage threshold is typically set by a resistor divider from VREF to ground. To calculate the current limit adjust voltage threshold the following equations can be used. Current limit adjust latching mode voltage is calculated in equation (2) V= V REF − (R1 × 300 mA) 1 + R1 R2 > 350 mV (2) Current limit adjust non-latching mode voltage is calculated in equation (3) V= V REF − (R1 × 80 mA) 1 + R1 R2 < 350 mV (3) where D R1 is the resistance from the VREF to CURLIM D R2 is the resistance from CURLIM to GND GND: GND is the reference ground and power ground for all functions of this part. Bypass and timing capacitors should be connected as close as possible to GND. RT: RT is the connection point for the oscillator timing resistor. It has a low impedance input and is nominally at 1.25 V. The current through RT is mirrored to the timing capacitor pin, CT. This causes a linear charging of CT from 0 V to 2.35 V. Note that the current mirror is limited to a maximum of 100 μA so RT must be greater than 12.5 kΩ. SYNC: SYNC is a bi-directional pin, allowing or providing external synchronization with TTL compatible thresholds. In a typical application RT is connected through a timing resistor to GND which allows the internal oscillator to free run. In this mode SYNC outputs a TTL compatible pulse during the oscillator dead time (when CT is being discharged). If RT is forced above 4.4 V, SYNC acts as an input with TTL compatible thresholds and the internal oscillator is disabled. When SYNC is high, greater than 2 V the outputs are held active low. When SYNC returns low, the outputs may be high until the on--time is terminated by the normal peak current signal, a fault seen at SHUTDOWN or the next high assertion of SYNC. Multiple UCC3806s can be synchronized by a single master UCC3806 or external clock. VC: VC is the input supply connection for the FET drive outputs and has an input range from 2.5 V to 15 V. VC should be capacitively bypassed for proper operation. VIN: VIN is the input supply connection for this device. The UCC1806 has a maximum startup threshold of 8 V and internally limited by means of a 15 V shunt regulator. The shunted supply current must be limited to 25 mA. For proper operation, VIN must be bypassed to GND with at least a 0.01-μF ceramic capacitor VREF: VREF is a 5.1 V ±1% trimmed reference output with a 5 mA maximum available current. VREF must be bypassed to GND with at least a 0.1-μF ceramic capacitor for proper operation. www.ti.com 7 UCC1806 UCC2806 UCC3806 SLUS272F -- FEBRUARY 2000 -- REVISED AUGUST 2006 FUNCTIONAL BLOCK DIAGRAM SYNC 10 13 VC 4.4V RT 1.5 V -+ 9 -+ 11 AOUT OSC CT CS-CS+ NI INV 3 Comparator -3X + 4 + -- QB S1 Shutdown 1 + EA -- R S1 COMP 7 Q Q 7.0 V VIN 15 7.5 V 15 V 12 GND Lockout 120 μA 0.5 V + 14 BOUT T R QB S2 -- 5 6 Q LO 8 + -+ -- 5.1 V Reference Regulator S2 R S Current Limit Restart R 4.25 V CURLIM 0.35 V S 200 μA Q -+ + -- 1.0 V 16 SHUT DOWN 200kΩ UVLO + -- 2 VREF Reference Low UDG--99035 8 www.ti.com UCC1806 UCC2806 UCC3806 SLUS272F -- FEBRUARY 2000 -- REVISED AUGUST 2006 TYPICAL APPLICATION DIAGRAM UDG--99036 TYPICAL CHARACTERISTICS Design equations for oscillator are described in the following equations. f OSC = 1 t RAMP + t FALL (4) t RAMP = 1.92 × R T × C T t FALL = (5) 2.4 × C T 0.002 − 1.25 RT (6) t DEAD = t FALL (7) www.ti.com 9 UCC1806 UCC2806 UCC3806 SLUS272F -- FEBRUARY 2000 -- REVISED AUGUST 2006 TYPICAL CHARACTERISTICS 180 135 Phase 40 20 90 45 0 Gain 0 OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE 58 fOSC -- Oscillator Frequency -- kHz Gain -- dB 60 60 Phase -- ° 80 ERROR AMPLIFIER GAIN AND PHASE vs FREQUENCY 56 54 52 50 48 46 44 42 --20 1k 10 k 100 k 1M --45 10 M fOSC -- Oscillator Frequency -- Hz --25 0 25 50 75 TJ -- Junction Temperature -- °C Figure 1. 10 40 --55 Figure 2. www.ti.com 100 125 UCC1806 UCC2806 UCC3806 SLUS272F -- FEBRUARY 2000 -- REVISED AUGUST 2006 OSCILLATOR FREQUENCY vs TIMING RESISTANCE 1M fOSC -- Oscillator Frequency -- kHz CT = 220 pF CT = 100 pF 100 k CT = 47 pF 10 k CT = 330 pF CT = 470 pF 0 10 k CT = 1.0 nF CT = 2.2 nF 100 k 1M RT -- Timing Resistance -- Ω Figure 3. REVISION HISTORY DATE REVISION DESCRIPTION 3/11/05 SLUS272D (Rev. D) Updated Equation 2 and 3 to remove x3 factor. 5/3/05 SLUS272E (Rev. E) Adjusted the factors of the switching frequency, Equation 1 and modified the typical discharge current from 2.0 mA to 2.5 mA. www.ti.com 11 PACKAGE OPTION ADDENDUM www.ti.com 16-Oct-2009 PACKAGING INFORMATION Orderable Device Status (1) 5962-9457501MEA ACTIVE CDIP J 16 1 TBD 5962-9457501Q2A ACTIVE LCCC FK 20 1 TBD Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish A42 MSL Peak Temp (3) N / A for Pkg Type POST-PLATE N / A for Pkg Type UCC1806J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type UCC1806J883B ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type UCC1806L ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type UCC1806L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type UCC2806D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC2806DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC2806DTR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC2806DTRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC2806DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC2806DWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC2806DWTR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC2806DWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC2806J ACTIVE CDIP J 16 1 TBD A42 UCC2806M ACTIVE SSOP/ QSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC2806MG4 ACTIVE SSOP/ QSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC2806MTR ACTIVE SSOP/ QSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC2806MTRG4 ACTIVE SSOP/ QSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC2806N ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UCC2806NG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UCC2806PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC2806PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC2806PWTR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC2806PWTRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC2806Q ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR UCC2806QG3 ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR UCC3806DW ACTIVE SOIC DW 16 40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR Addendum-Page 1 N / A for Pkg Type PACKAGE OPTION ADDENDUM www.ti.com 16-Oct-2009 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty UCC3806DWG4 ACTIVE SOIC DW 16 UCC3806DWTR ACTIVE SOIC DW UCC3806DWTRG4 ACTIVE SOIC Lead/Ball Finish MSL Peak Temp (3) no Sb/Br) 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC3806J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type UCC3806N ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UCC3806NG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UCC3806PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC3806PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC3806Q ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR UCC3806QG3 ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR UCC3806QTR ACTIVE PLCC FN 20 1000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR UCC3806QTRG3 ACTIVE PLCC FN 20 1000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 16-Oct-2009 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UCC1806, UCC2806, UCC2806M, UCC3806, UCC3806M : • Space: UCC1806-SP NOTE: Qualified Version Definitions: • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3 PACKAGE OPTION ADDENDUM www.ti.com 18-Jun-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) 5962-9457501MEA ACTIVE CDIP J 16 1 TBD Call TI Call TI -55 to 125 5962-9457501ME A UCC1806J/883B 5962-9457501Q2A ACTIVE LCCC FK 20 1 TBD Call TI Call TI -55 to 125 59629457501Q2A UCC1806L/ 883B UCC1806J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 UCC1806J UCC1806J883B ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9457501ME A UCC1806J/883B UCC1806L ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 UCC1806L UCC1806L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629457501Q2A UCC1806L/ 883B UCC2806D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2806D UCC2806DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2806D UCC2806DTR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2806D UCC2806DTRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2806D UCC2806DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2806DW UCC2806DWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2806DW UCC2806DWTR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2806DW UCC2806DWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2806DW UCC2806J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -40 to 85 UCC2806J Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 18-Jun-2013 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) UCC2806M ACTIVE SSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2806M UCC2806MG4 ACTIVE SSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2806M UCC2806MTR ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2806M UCC2806MTRG4 ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2806M UCC2806N ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 UCC2806N UCC2806NG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 UCC2806N UCC2806PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 2806 UCC2806PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 2806 UCC2806PWTR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 2806 UCC2806PWTRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 2806 UCC2806Q ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 85 UCC2806Q UCC2806QG3 ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 85 UCC2806Q UCC3806DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3806DW UCC3806DWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3806DW UCC3806DWTR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3806DW UCC3806DWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3806DW UCC3806J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type 0 to 70 UCC3806J UCC3806N ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UCC3806N Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 18-Jun-2013 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) UCC3806NG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UCC3806N UCC3806PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 3806 UCC3806PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 3806 UCC3806Q ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR 0 to 70 UCC3806Q UCC3806QG3 ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR 0 to 70 UCC3806Q UCC3806QTR ACTIVE PLCC FN 20 1000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR 0 to 70 UCC3806Q UCC3806QTRG3 ACTIVE PLCC FN 20 1000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR 0 to 70 UCC3806Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com 18-Jun-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UCC1806, UCC2806, UCC2806M, UCC3806, UCC3806M : • Catalog: UCC3806, UCC2806, UCC3806M, UCC3806 • Military: UCC2806M, UCC1806 • Space: UCC1806-SP NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 4 PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device UCC2806DTR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 UCC2806MTR SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC2806PWTR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 UCC3806DWTR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC2806DTR SOIC D 16 2500 367.0 367.0 38.0 UCC2806MTR SSOP DBQ 16 2500 367.0 367.0 35.0 UCC2806PWTR TSSOP PW 16 2000 367.0 367.0 35.0 UCC3806DWTR SOIC DW 16 2000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56) 44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10) 52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37) 68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91) 84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45) 4040005 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated