CM2030
HDMI Transmitter Port Protection and Interface Device
Features
Product Description
•
•
•
•
The CM2030 HDMI Transmitter Port Protection and
Interface Device is specifically designed for next gener
ation HDMI Host interface protection.
•
•
•
•
•
•
•
HDMI 1.3 compliant
Supports thin dielectric and 2-layer boards
Minimizes TMDS skew with 0.05pF matching
Long HDMI cable support with integrated I2C
accelerator
Active termination and slew rate limiting for CEC
Supports direct connection to CEC microcontroller
Integrated I2C level shifting to CMOS level includ
ing low logic level voltages
Integrated 8kV ESD protection and backdrive pro
tection on all external I/O lines
Integrated overcurrent output protection per HDMI
1.3
Multiport I2C support eliminates need for analog
mux on DDC lines
Simplified layout with matched 0.5mm trace spac
ing
An integrated package provides all ESD, slew rate lim
iting on CEC line, level shifting/isolation, overcurrent
output protection and backdrive protection for an HDMI
port in a single 38-Pin TSSOP package.
The CM2030 part is specifically designed to provide
the designer with the most reliable path to HDMI 1.3
CTS compliance.
The CM2030 also incorporates a silicon overcurrent
protection device for +5V supply voltage output to the
connector.
Applications
•
•
PC and consumer electronics
Set top box, DVD RW, PC, graphics cards
Electrical Schematic
5V_SUPPLY
TMDS_D2+
TMDS_D1+
TMDS_D0+
TMDS_CK+
TMDS_GND
TMDS_GND
TMDS_GND
TMDS_GND
TMDS_D2-
TMDS_D1
TMDS_D0
TMDS_CK
5V_SUPPLY
LV_SUPPLY
DDC_CLK_IN
CMOS/I2C
LEVEL SHIFT
5V_SUPPLY
LV_SUPPLY
DYNAMIC
PULLUP
DDC_DAT_IN
DYNAMIC
PULLUP
CMOS/I2C
LEVEL SHIFT
DDC_CLK_OUT
DDC_DAT_OUT
CE_SUPPLY
CE_SUPPLY
LV_SUPPLY
ACTIVE SLEW
RATE
LIMITING
IS
HOTPLUG_DET_IN
HOTPLUG_DET_OUT
CE_REMOTE_IN
CE_REMOTE_OUT
3IS
5V_SUPPLY
55mA
OVERCURRENT
SWITCH
5V_OUT
© 2007 California Micro Devices Corp. All rights reserved.
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
● Tel: 408.263.3214
Issue A – 11/16/07
● Fax: 408.263.7846
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1
CM2030
PACKAGE / PINOUT DIAGRAM
TOP VIEW
5V_SUPPLY
1
38
5V_OUT
LV_SUPPLY
2
37
CE_SUPPLY
GND
3
36
GND
TMDS_D2+
4
35
TMDS_D2+
TMDS_GND
5
34
TMDS_GND
TMDS_D2–
6
33
TMDS_D2–
TMDS_D1+
7
32
TMDS_D1+
TMDS_GND
8
31
TMDS_GND
TMDS_D1–
9
30
TMDS_D1–
TMDS_D0+
10
29
TMDS_D0+
TMDS_GND
11
28
TMDS_GND
TMDS_D0–
12
27
TMDS_D0–
TMDS_CK+
13
26
TMDS_CK+
TMDS_GND
25
TMDS_GND
TMDS_CK–
14
15
24
TMDS_CK–
CE_REMOTE_IN
16
23
CE_REMOTE_OUT
DDC_CLK_IN
17
22
DDC_CLK_OUT
DDC_DAT_IN
18
21
DDC_DAT_OUT
HOTPLUG_DET_IN
19
20
HOTPLUG_DET_OUT
38-PIN TSSOP PACKAGE
Note: This drawing is not to scale.
PIN DESCRIPTIONS
PINS
4, 35
NAME
TMDS_D2+
ESD Level
3
DESCRIPTION
8kV
TMDS 0.9pF ESD protection.1
6, 33
TMDS_D2–
8kV3
TMDS 0.9pF ESD protection.1
7, 32
TMDS_D1+
3
8kV
TMDS 0.9pF ESD protection.1
9, 30
TMDS_D1–
8kV3
TMDS 0.9pF ESD protection.1
10, 29
TMDS_D0+
8kV3
TMDS 0.9pF ESD protection.1
12, 27
TMDS_D0–
8kV3
TMDS 0.9pF ESD protection.1
13, 26
TMDS_CK+
8kV3
TMDS 0.9pF ESD protection.1
15, 24
TMDS_CK–
8kV3
16
CE_REMOTE_IN
2kV4
TMDS 0.9pF ESD protection.1
CE_SUPPLY referenced logic level in.
23
CE_REMOTE_OUT
8kV3
17
DDC_CLK_IN
2kV4
22
DDC_CLK_OUT
8kV3
18
DDC_DAT_IN
2kV4
21
DDC_DAT_OUT
8kV3
19
HOTPLUG_DET_IN
2kV4
20
HOTPLUG_DET_OUT
8kV3
2
LV_SUPPLY
2kV4
5V_SUPPLY referenced logic level out plus 10pF ESD. A 0.1μF
bypass ceramic capacitor is recommended on this pin.2
Bias for CE / DDC / HOTPLUG level shifters.
37
CE_SUPPLY
2kV4,2
CEC bias voltage. Previously CM2020 ESD_BYP pin.
1
5V_SUPPLY
2kV4
Current source for 5V_OUT, VREF for DDC I2C voltage references,
and bias for 8kV ESD pins.
5V_SUPPLY referenced logic level out plus 10pF ESD.6
LV_SUPPLY referenced logic level in.
5V_SUPPLY referenced logic level out plus 10pF ESD.6
LV_SUPPLY referenced logic level in.
5V_SUPPLY referenced logic level out plus 10pF ESD.6
LV_SUPPLY referenced logic level in.
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CM2030
PIN DESCRIPTIONS (CONTINUED)
38
5V_OUT
8kV3
3, 5, 8, 11,
14, 25,
28, 31, 34,
36
GND / TMDS_GND
N/A
55mA minimum overcurrent protected 5V output. This output must be
bypassed with a 0.1μF ceramic capacitor.
GND reference.
Note 1: These 2 pins need to be connected together in-line on the PCB. See recommended layout diagram.
Note 2: This output can be connected to an external 0.1μF ceramic capacitor/pads to maintain backward compatibility with the
CM2020.
Note 3: Standard IEC 61000-4-2, CDISCHARGE=150pF, RDISCHARGE=330Ω, 5V_SUPPLY and LV_SUPPLY within recommended
operating conditions, GND=0V, 5V_OUT (pin 38), and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1μF ceramic
capacitor connected to GND.
Note 4: Human Body Model per MIL-STD-883, Method 3015, CDISCHARGE=100pF, RDISCHARGE=1.5kΩ, 5V_SUPPLYand
LV_SUPPLY within recommended operating conditions, GND=0V, 5V_OUT (pin 38), and HOTPLUG_DET_OUT (pin 20)
each bypassed with a 0.1μF ceramic capacitor connected to GND.
Note 5: These pins should be routed directly to the associated GND pins on the HDMI connector with single point ground vias at the
connector.
Note 6: The slew-rate control and active acceleration circuitry dynamically offsets the system capacitive load on these pins.
© 2007 California Micro Devices Corp. All rights reserved.
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
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3
CM2030
Backdrive Protection and Isolation
Backdrive current is defined as the undesirable current
flow through an I/O pin when that I/O pin’s voltage
exceeds the related local supply voltage for that cir
cuitry. This is a potentially common occurrence in mul
timedia
entertainment systems
with multiple
components and several power plane domains in each
system.
For example, if a DVD player is switched off and an
HDMI connected TV is powered on, there is a possibil
ity of reverse current flow back into the main power
supply rail of the DVD player from pull-ups in the TV. As
little as a few milliamps of backdrive current flowing
back into the power rail can charge the DVD player’s
bulk bypass capacitance on the power rail to some
intermediate level. If this level rises above the poweron-reset (POR) voltage level of some of the integrated
LV_SUPPLY =OFF LOW VOLTAGE
HDMI ASIC
HDMI SOURCE circuits in the DVD player, then these devices may not
reset properly when the DVD player is turned back on.
If any SOC devices are incorporated in the design
which have built-in level shifter and/or ESD protection
structures, there can be a risk of permanent damage
due to backdrive. In this case, backdrive current can
forward bias the on-chip ESD protection structure. If
the current flow is high enough, even as little as a few
milliamps, it could destroy one of the SOC chip’s inter
nal DRC diodes, as they are not designed for passing
DC.
To avoid either of these situations, the CM2030 was
designed to block backdrive current, guaranteeing less
than 5μA into any I/O pin when the I/O pin voltage
exceeds its related operating CM2030 supply voltage.
+5V
+5V
LV_SUPPLY
=OFF
LOW VOLTAGE
HDMI ASIC
ASIC
HDMI SINK ASIC
HDMI SINK
HDMI SOURCE
Figure 1. Backdrive Protection Diagram.
Display Data Channel (DDC) lines
DYNAMIC PULLUPS
For this reason, the CM2030 was designed with an
internal I2C accelerator to meet the AC timing specifi
cation even with very long and non-compliant cables.
Based on the HDMI specification, the maximum capac
itance of the DDC line can approach 800pF (50pF from
source, 50pF from sink, and 700pF from cable). At the
upper range of capacitance values (i.e. long cables), it
becomes impossible for the DDC lines to meet the I2C
timing specifications with the minimum pull-up resistor
of 1.5kΩ.
The internal accelerator increases the positive slew
rate of the DDC_CLK_OUT and DDC_DAT_OUT lines
whenever the sensed voltage level exceeds
0.3*5V_SUPPLY (approximately 1.5V). This provides
faster overall risetime in heavily loaded situations with
out overloading the multi-drop open drain I2C outputs
elsewhere.
The DDC interface is based on the I2C serial bus proto
col for EDID configuration.
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CM2030
DYNAMIC PULLUPS (CONT’D)
Figure 2. Dynamic DDC Pullups (Discrete - Top, CM2030 - Bottom; 3.3V ASIC - Left, 5V Cable - Right.)
Figure 2 demonstrates the “worst case” operation of
the dynamic CM2030 DDC level shifting circuitry (bot
tom) against a discrete NFET common-gate level
shifter circuit with a typical 1.5kΩ pullup at the source
(top.) Both are shown driving an off-spec, but unfortu
nately readily available 31m HDMI cable which
exceeds the 700pF HDMI specification. Some widely
available HDMI cables have been measured at over
4nF.
When the standard I/OD cell releases the NFET dis
crete shifter, the risetime is limited by the pullup and
the parasitics of the cable, source and sink. For long
cables, this can extend the risetime and reduce the
margin for reading a valid “high” level on the data line.
In this case, an HDMI source may not be able to read
uncorrupted data and will not be able to initiate a link.
With the CM2030’s dynamic pullups, when the ASIC
driver releases its DDC line and the “OUT” line reaches
at least 0.3*VDD (of 5V_SUPPLY), then the “OUT”
active pullups are enabled and the CM2030 takes over
driving the cable until the “OUT” voltage approaches
the 5V_SUPPLY rail.
The internal pass element and the dynamic pullups
also work together to damp reflections on the longer
cables and keep them from glitching the local ASIC.
I2C LOW LEVEL SHIFTING
In addition to the Dynamic Pullups described in the
previous section, the CM2030 also incorporates
improved I2C low-level shifting on the DDC_CLK_IN
and DDC_DAT_IN lines for enhanced compatibility.
Typical discrete NFET level shifters can advertise
specifications for low RDS[on], but usually state rela
tively high V[GS] test parameters, requiring a 'switch'
signal (gate voltage) as high as 10V or more. At a sink
current of 4mA for the ASIC on DDC_XX_IN, the
CM2030 guarantees no more than 140mV increase to
DDC_XX_OUT, even with a switching control of 2.5V
on LV_SUPPLY.
When I2C devices are driving the external cable, an
internal pulldown on DDC_XX_IN guarantees that the
VOL seen by the ASIC on DDC_XX_IN is equal to or
lower than DDC_XX_OUT.
Multiport DDC Multiplexing
By switching LV_SUPPLY, the DDC/HPD blocks can be
independently disabled by engaging their inherent
“backdrive” protection. This allows N:1 multiplexing of
the low-speed HDMI signals without any additional
FET switches.
Consumer Electronics Control (CEC)
The Consumer Electronics Control (CEC) line is a high
level command and control protocol, based on a single
wire multidrop open drain communication bus running
at approximately 1kHz (See Figure 3). While the HDMI
link provides only a single point-to-point connection, up
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5
CM2030
to ten (10) CEC devices may reside on the bus, and
they may be daisy chained out through other physical
connectors including other HDMI ports or other dedi
cated CEC links. The high level protocol of CEC can be
implemented in a simple microcontroller or other inter
face with any I/OD (input/open-drain) GPIO.
levels and HDMI slew-rate and isolation specifications
(See Figure 5).
CEC
CEC
RX
I/OD
GPIO
CEC I/F
μP
TX
CM2030
Figure 3. Typical μC I/OD Driver
Figure 5. Integrated CM2030 Solution
To limit possible EMI and ringing in this potentially
complex connection topology, the rise- and fall-time of
this line are limited by the specification. However,
meeting the slew-rate limiting requirements with addi
tional discrete circuitry in this bi-directional block is not
trivial without an additional RX/TX control line to limit
the output slew-rate without affecting the input sensing
(See Figure 4).
The CM2030 also includes an internal backdrive pro
tected static pullup 120μA current source from the
CE_SUPPLY rail in addition to the dynamic slew rate
control circuitry.
Figure 6 shows a typical shaped CM2030 CEC output
(bottom) against a ringing uncontrolled discrete solu
tion (top).
CEC
RX
TX
TX_EN
Slew Rate
Limited
3-State Buffer
Figure 4. Three-Pin External Buffer Control
Simple CMOS buffers cannot be used in this applica
tion since the load can vary so much (total pullup of
27kΩ to less than 2kΩ, and up to 7.3nF total capaci
tance.) The CM2030 targets an output drive slew-rate
of less than 100mV/μs regardless of static load for the
CEC line. Additionally, the same internal circuitry will
perform active termination, thus reducing ringing and
overshoot in entertainment systems connected to leg
acy or poorly designed CEC nodes.
Figure 6. CM2030 CEC Output
The CM2030’s bi-directional slew rate limiting is inte
grated into the CEC level-shifter functionality thus
allowing the designer to directly interface a simple low
voltage CMOS GPIO directly to the CEC bus and
simultaneously guarantee meeting all CEC output logic
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CM2030
Hotplug Detect Logic
The CM2030 ensures that the local ASIC will properly
detect an HDMI compliant Sink. The current sink main-
tains a local logic “low” when no system is connected.
A valid pullup on the HDMI connector pin will overdrive
the internal pulldown and deliver a logic “high” to the
local ASIC.
CM2030
5V_SUPPLY
LV_SUPPLY
IS
HP_IN
19
HP_OUT
3IS
HDMI CONN
Figure 7. Hotplug Detect Circuit
© 2007 California Micro Devices Corp. All rights reserved.
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7
CM2030
Ordering Information
PART NUMBERING INFORMATION
Lead-free Finish
Pins
Package
Ordering Part Number1
Part Marking
38
TSSOP-38
CM2030-A0TR
CM2030-A0TR
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNITS
6.0
V
[GND - 0.5] to [VCC + 0.5]
V
–65 to +150
°C
VCC5, VCCLV
DC Voltage at any Channel Input
Storage Temperature Range
STANDARD (RECOMMENDED) OPERATING CONDITIONS
SYMBOL
5V_SUPPLY
PARAMETER
MIN
Operating Supply Voltage
TYP
MAX
UNITS
5
5.5
V
LV_SUPPLY
Bias Supply Voltage
1
3.3
5.5
V
CE_SUPPLY
Bias Supply Voltage
3
3.3
3.6
V
85
°C
Operating Temperature Range
–40
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)
SYMBOL
PARAMETER
CONDITIONS
TYP
MAX
UNITS
Operating Supply Current
5V_SUPPLY = 5.0V, CEC_OUT =
3.3V, LV_SUPPLY= CE_SUPPLY=
3.3V, DDC=5V; Note 7
300
350
μA
ICCLV
Bias Supply Current
LV_SUPPLY=3.3V; Note 7
60
150
μA
ICCCE
Bias Supply Current
CE_SUPPLY=3.3V,
CEC_OUT=0V; Note 7
60
150
μA
VDROP
5V_OUT Overcurrent Out
put Drop
5V_SUPPLY=5.0V,
IOUT=55mA
65
100
mV
ISC
5V_OUT Short Circuit Cur
rent Limit
5V_SUPPLY=5.0V,
5V_OUT=GND
135
175
mA
IOFF
OFF state leakage current,
level shifting NFET
LV_SUPPLY=0V; Note 2
0.1
5
μA
Current through
CE-REMOTE_OUT when
powered down
CE-REMOTE_IN = CE_SUPPLY <
CE_REMOTE_OUT
0.1
1.8
μA
Current through TMDS pins
when powered down
All Supplies = 0V; TMDS_[2:0]+/–,
TMDS_CK+/– = 4V
0.1
5
μA
ICC5
IBACKDRIVECEC
IBACKDRIVETMDS
MIN
90
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CM2030
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)
Current through
5V_OUT when powered
down
All Supplies = 0V; 5V_OUT_PIN =
5V
0.1
5
μA
IBACKDRIVEDDC
Current through
DDC_DAT/CLK_OUT when
powered down
All Supplies = 0V;
DDC_DAT/CLK_OUT = 5V;
DDC_DAT/CLK_IN = 0V
0.1
5
μA
IBACKDRIVEHOTPLUG
Current through
HOTPLUG_DET_OUT when
powered down
All Supplies = 0V;
HOTPLUG_DET_OUT = 5V;
HOTPLUG_IN = 0V
0.1
5
μA
CECSL
CEC Slew Limit
Measured from 10-90% or 90-10%
0.26
0.65
V/μs
CECRT
CEC Rise Time
Measured from 10-90%
Assumes a signal swing from 0
3.3V
26.4
250
μs
CECFT
CEC Fall Time
Measured from 90-10%
Assumes a signal swing from 0
3.3V
4
50
μs
VACC
Turn On Threshold of I2C/
DDC Accelerator
Voltage is 0.3 ±10% X 5V_Supply;
Note 2
1.5
1.65
V
VON(DDC_OUT)
Voltage drop across DDC
level shifter
LV_SUPPLY=3.3V, 3mA Sink at
DDCIN, DDCOUT < VACC
150
225
mV
VOL(DDC_IN)
Logic Level (ASIC side)
when I2C/DDC Logic Low
Applied;
DDC_OUT=0.4V,
LV_SUPPLY=3.3V, 1.5kΩ pullup
on DDC_OUT to 5.0V; Note 2
0.3
0.4
V
1
μs
0.95
0.95
V
V
IBACKDRIVE5V_OUT
1.35
(I2C pass-through compatibility)
tr(DDC)
DDC_OUT Line Risetime,
VACC < VDDC_OUT <
(5V_Supply-0.5V)
DDC_IN floating,
LV_SUPPLY=3.3V, 1.5kΩ pullup
on DDC_OUT to 5.0V, Bus
Capacitance = 1500pF
Diode Forward Voltage
Top Diode
Bottom Diode
IF = 8mA, TA = 25°C; Note 2
VESD
ESD Withstand Voltage
(IEC)
Pins 4, 7, 10, 13, 20, 21, 22, 23,
24, 27, 30, 33, TA = 25°C;
Notes 2 and 3
±8
kV
VESD
ESD Withstand Voltage
(HBM)
Pins 1, 2, 16, 17, 18, 19, 37, 38,
TA = 25°C; Note 2
±2
kV
VCL
Channel Clamp Voltage
Positive Transients
Negative Transients
TA=25°C, IPP = 1A, tP = 8/20μS;
Notes 2 & 6
Dynamic Resistance
Positive Transients
Negative Transients
TA=25°C, IPP = 1A, tP = 8/20μS
Any I/O pin to Ground; Note 6
TMDS Channel Leakage
Current
TA = 25°C; Note 2
0.01
1
μA
TMDS Channel Input
Capacitance
5V_SUPPLY=5.0V, Measured at
1MHz, VBIAS=2.5V; Note 2
0.9
1.2
pF
VF
RDYN
ILEAK
CIN, TMDS
0.6
0.6
0.85
0.85
11.0
–2.0
V
V
1.4
0.9
Ω
Ω
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9
CM2030
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)
ΔCIN, TMDS
CMUTUAL
TMDS Channel Input
Capacitance Matching
5V_SUPPLY=5.0V, Measured at
1MHz, VBIAS=2.5V; Notes 2 and 5
Mutual Capacitance
5V_SUPPLY=0V, Measured at
between signal pin and adja 1MHz, VBIAS=2.5V; Note 2
cent signal pin
0.05
pF
0.07
pF
CIN, DDCOUT
Level Shifting Input Capaci
tance, Capacitance to GND
5V_SUPPLY=0V,
Measured at 100KHz,
VBIAS=2.5V; Note 2
10
pF
CIN, CECOUT
Level Shifting Input Capaci
tance, Capacitance to GND
5V_SUPPLY=0V,
Measured at 100KHz,
VBIAS=1.65V; Note 2
10
pF
CIN, HPOUT
Level Shifting Input Capaci
tance, Capacitance to GND
5V_SUPPLY=0V,
Measured at 100KHz,
VBIAS=2.5V; Note 2
10
pF
Note 1: Operating Characteristics are over Standard Operating Conditions unless otherwise specified.
Note 2: This parameter is guaranteed by design and verified by device characterization.
Note 3: Standard IEC61000-4-2, CDISCHARGE=150pF, RDISCHARGE=330Ω, 5V_SUPPLY=5V, 3.3V_SUPPLY=3.3V,
LV_SUPPLY=3.3V, GND=0V.
Note 4: Human Body Model per MIL-STD-883, Method 3015, CDISCHARGE=100pF, RDISCHARGE=1.5kΩ, 5V_SUPPLY=5V,
3.3V_SUPPLY=3.3V, LV_SUPPLY=3.3V, GND=0V.
Note 5: Intra-pair matching, each TMDS pair (i.e. D+, D–)
Note 6: These measurements performed with no external capacitor on VP (VP floating)
Note 7: These static measurements do not include AC activity on controlled I/O lines
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CM2030
Performance Information
Typical Filter Performance (TA=25°C, DC Bias=0V, 50 Ohm Environment)
Figure 8. Insertion Loss vs. Frequency (TMDS_D1– to GND)
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11
CM2030
Application Information
ROPT(See NOTE 4)
5V_SUPPLY
5V_OUT
CM2020/2030
1
38
VCEC
2
37
CBYP
3
36
4
35
TMDS_D2+
5
34
TMDS_GND
6
33
TMDS_D2–
7
32
TMDS_D1+
8
31
TMDS_GND
9
30
TMDS_D1–
10
29
TMDS_D0+
11
28
TMDS_GND
12
27
TMDS_D0–
13
26
TMDS_CK+
14
15
25
TMDS_GND
24
TMDS_CK–
ASIC_CEC2
16
23
CE_REMOTE
ASIC_SCL2
17
22
ASIC_SDA2
18
21
N/C
DDC_CLK
HOTPLUG_DETECT2
19
20
LV_SUPPLY
NOTE 1
{
TMDS_D2+
TMDS_D2–
TMDS_D1+
TMDS_D1–
TMDS_D0+
TMDS_D0–
TMDS_CK+
TMDS_CK–
100nF
DDC_DAT
NOTE 3
GND
+5V OUT
HOTPLUG_DET
DCEC
HDMI
Connector
RDAT
2kΩ
RSCL
2kΩ
EEPROM_CLK
27kΩ
CEC
VCEC
EEPROM_DAT
RCEC
RPD CHP
15kΩ 100nF
CVOUT
100nF
Figure 9. Typical Application for CM2030
LAYOUT NOTES
Differential TMDS Pairs should be designed as
normal 100Ω HDMI Microstrip. Single Ended
(decoupled) TMDS traces underneath MediaGuardTM, and traces between MediaGuardTM and
Connector should be tuned to match chip/connec
tor IBIS parasitics. (See MediaGuardTM Layout
Application Notes.)
1
Level Shifter signals should be biased with a weak
pullup to the desired local LV_SUPPLY. If the local
ASIC includes sufficient pullups to register a logic high,
then external pullups may not be needed.
2
avoid placing any silk-screen printing over TMDS
traces.
CM2020/CM2030 footprint compatibility. For the
CM2030, Pin 37 becomes the VCEC power supply pin for
the slew-rate limiting circuitry. This can be supplied by
a 0Ω jumper to VCEC which should be depopulated to uti
lize the CM2020. The 100nF CBYP is recommended for
all applications.
4
Place MediaGuardTM as close to the connector as pos
sible, and as with any controlled impedance line always
3
© 2007 California Micro Devices Corp. All rights reserved.
12
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
● Tel: 408.263.3214
Issue A – 11/16/07
● Fax: 408.263.7846
● www.cmd.com
CM2030
Application Information
Design Considerations
1. 5V out (pin 38)
Maximum overcurrent protection output drop at 55mA
on 5V_OUT is 100mV. To meet HDMI output require
ments of 4.8-5.3V, an input of greater than 4.9V should
be used (i.e. 5.1V ±4%)
figurations can be forward biased when their VDD rail
is lower than the I/O pin bias, thereby exhibiting
extremely high apparent capacitance measurements,
for example. The MediaGuardΤΜ backdrive isolation
circuitry limits this current to less than 5μA, and will
help ensure HDMI compliance.
2. DUT On vs. DUT Off
Many HDMI CTS tests require a power off condition on
the System Under Test. Many discrete ESD diode con
Please review all of the current HDMI design guidelines available at:
http://www.calmicro.com/applications/customer/downloads/current-cmd-mediaguard-design-guidelines.zip
© 2007 California Micro Devices Corp. All rights reserved.
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
● Tel: 408.263.3214
Issue A – 11/16/07
● Fax: 408.263.7846
● www.cmd.com
13
CM2030
Mechanical Details
TSSOP-38 Mechanical Specifications
Mechanical Package Diagrams
CM2030 devices are supplied in 38-pin TSSOP pack
ages. Dimensions are presented below.
PACKAGE DIMENSIONS
TOP VIEW
Package
TSSOP
JEDEC No.
MO-153 (Variation BD-1)
Pins
38
Dimensions
D
Millimeters
Min
Max
38
Inches
Min
E
A
—
1.20
—
0.047
0.05
0.15
0.002
0.006
b
0.17
0.27
0.007
0.011
c
0.09
0.20
0.004
0.008
D
9.60
9.80
0.378
0.386
E1
e
6.40 BSC
4.30
L
0.45
35 34
33 32 31 30
29
28 27 26
25 24
23 22 21
20
E1
Pin 1 Marking
1
2
3
4
5
6
7
8
9
10
11 12 13
14 15
16 17 18
19
SIDE VIEW
0.252 BSC
4.50
0.50 BSC
# per tape
and reel
36
Max
A1
E
37
0.169
0.177
A
A1
SEATING
PLANE
b
e
0.020 BSC
0.75
0.018
0.030
2500 pieces
END VIEW
Controlling dimension: millimeters
c
L
Package Dimensions for TSSOP-38
© 2007 California Micro Devices Corp. All rights reserved.
14
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
● Tel: 408.263.3214
Issue A – 11/16/07
● Fax: 408.263.7846
● www.cmd.com