TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 1 TMS320F2803x (Piccolo™) MCUs • • • • • • High-Efficiency 32-Bit CPU (TMS320C28x™) – 60 MHz (16.67-ns Cycle Time) – 16 x 16 and 32 x 32 MAC Operations – 16 x 16 Dual MAC – Harvard Bus Architecture – Atomic Operations – Fast Interrupt Response and Processing – Unified Memory Programming Model – Code-Efficient (in C/C++ and Assembly) Programmable Control Law Accelerator (CLA) – 32-bit floating-point math accelerator – Executes code independently of the main CPU Low Device and System Cost: – Single 3.3-V Supply – No Power Sequencing Requirement – Integrated Power-on Reset and Brown-out Reset – Low Power – No Analog Support Pins Clocking: – 2 Internal Zero-pin Oscillators – On-chip Crystal Oscillator/External Clock Input – Dynamic PLL Ratio Changes Supported – Watchdog Timer Module – Missing Clock Detection Circuitry Up to 45 Individually Programmable, Multiplexed GPIO Pins With Input Filtering Peripheral Interrupt Expansion (PIE) Block That Supports All Peripheral Interrupts • • • • • • • • Three 32-Bit CPU Timers Independent 16-bit Timer in Each ePWM Module On-Chip Memory – Flash, SARAM, OTP, Boot ROM Available 128-Bit Security Key/Lock – Protects Secure Memory Blocks – Prevents Firmware Reverse Engineering Serial Port Peripherals – One SCI (UART) Module – Two SPI Modules – One Inter-Integrated-Circuit (I2C) Bus – One Local Interconnect Network (LIN) Bus – One Enhanced Controller Area Network (eCAN) Bus Advanced Emulation Features – Analysis and Breakpoint Functions – Real-Time Debug via Hardware Enhanced Control Peripherals – Enhanced Pulse Width Modulator (ePWM) – High-resolution PWM (HRPWM) – Enhanced Capture (eCAP) – Enhanced Quadrature Encoder Pulse (eQEP) – Analog-to-Digital Converter (ADC) – On-Chip Temperature Sensor – Comparator 2803x Packages – 64-Pin PAG Plastic Small-Outline Package (TQFP) – 80-Pin PN Plastic Quad Flatpack (LQFP) 1.2 Description The F2803x Piccolo™ family of microcontrollers provides the power of the C28x™ core and Control Law Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family is code compatible with previous C28-based code, as well as providing a high level of analog integration. An internal voltage regulator allows for single rail operation. Enhancements have been made to the HRPWM module to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3-V fixed full scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low overhead/latency. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. Piccolo, TMS320C28x, C28x, TMS320C2000, Code Composer Studio, XDS510 are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2009–2009, Texas Instruments Incorporated PRODUCT PREVIEW 1.1 Features TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 1.3 Getting Started This section gives a brief overview of the steps to take when first developing for a C28x device. For more detail on each of these steps, see the following: • Getting Started With TMS320C28x Digital Signal Controllers (literature number SPRAAM0). • C2000 Getting Started Website (http://www.ti.com/c2000getstarted) • TMS320F28x MCU Development and Experimenter's Kits (http://www.ti.com/f28xkits) PRODUCT PREVIEW 2 TMS320F2803x (Piccolo™) MCUs Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 Contents 2 3 4 TMS320F2803x (Piccolo™) MCUs .................... 1 4.8 Enhanced PWM Modules (ePWM1/2/3/4/5/6/7) 1.1 Features .............................................. 1 4.9 High-Resolution PWM (HRPWM) ................... 73 1.2 Description ............................................ 1 4.10 Enhanced Capture Module (eCAP1) ................ 74 1.3 Getting Started........................................ 2 4.11 Enhanced Quadrature Encoder Pulse (eQEP) ...... 76 ...................................... 4 2.1 Pin Assignments ...................................... 5 2.2 Signal Descriptions ................................... 7 Functional Overview ................................... 14 3.1 Block Diagram ....................................... 14 3.2 Memory Maps ...................................... 15 3.3 Brief Descriptions.................................... 20 3.4 Register Map ........................................ 27 3.5 Device Emulation Registers ......................... 28 3.6 Interrupts ............................................ 29 3.7 VREG/BOR/POR .................................... 33 3.8 System Control ...................................... 35 3.9 Low-power Modes Block ............................ 42 Peripherals............................................... 44 4.1 Control Law Accelerator (CLA) Overview ........... 44 4.2 Analog Block ........................................ 47 4.3 Serial Peripheral Interface (SPI) Module ........... 51 4.4 Serial Communications Interface (SCI) Module .... 54 4.5 Local Interconnect Network (LIN) ................... 57 4.12 JTAG Port ........................................... 78 4.13 GPIO MUX Hardware Features 4.6 Enhanced Controller Area Network (eCAN) Module 60 4.7 Inter-Integrated Circuit (I2C) Submit Documentation Feedback ........................ 64 5 6 Device Support .......................................... ......................................... 66 79 84 5.1 Device and Development Support Tool Nomenclature ....................................... 84 5.2 Related Documentation ............................. 86 Electrical Specifications .............................. 88 6.1 Absolute Maximum Ratings ......................... 88 6.2 Recommended Operating Conditions ............... 88 6.3 Electrical Characteristics 6.4 Current Consumption................................ 89 6.5 6.6 Thermal Design Considerations ..................... 93 Emulator Connection Without Signal Buffering for the MCU ............................................. 93 6.7 Timing Parameter Symbology ....................... 94 6.8 Clock Requirements and Characteristics 6.9 Power Sequencing .................................. 97 6.10 General-Purpose Input/Output (GPIO)............. 100 6.11 Enhanced Control Peripherals ..................... 106 ........................... ........... .............................. Revision History ...................................... Mechanicals ............................................ 6.12 7 8 .... Detailed Descriptions Contents 89 96 121 122 123 3 PRODUCT PREVIEW 1 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 2 Hardware Features Table 2-1 lists the features of the TMS320F2803x devices. Table 2-1. Hardware Features FEATURE 28032 (60 MHz) TYPE 64-Pin PAG TQFP Package Type 28033 (60 MHz) 80-Pin PN LQFP 64-Pin PAG TQFP 28034 (60 MHz) 80-Pin PN LQFP 64-Pin PAG TQFP 28035 (60 MHz) 80-Pin PN LQFP 64-Pin PAG TQFP 80-Pin PN LQFP PRODUCT PREVIEW Instruction cycle – 16.67 ns 16.67 ns 16.67 ns Control Law Accelerator 0 No Yes No Yes On-chip flash (16-bit word) – 32K 32K 64K 64K On-chip SARAM (16-bit word) – 10K 10K 10K 10K Code security for on-chip flash/SARAM/OTP blocks – Yes Yes Yes Yes Boot ROM (8K X16) – Yes Yes Yes Yes One-time programmable (OTP) ROM (16-bit word) – 1K 1K 1K 1K ePWM outputs 1 eCAP inputs 0 eQEP modules 0 1 1 1 1 Watchdog timer – Yes Yes Yes Yes 12 MSPS Conversion Time 12-Bit ADC 14 12 1 14 12 1 16.67 ns 14 12 1 14 1 4.6 4.6 4.6 4.6 216.67 ns 216.67 ns 216.67 ns 216.67 ns 3 Channels 14 Temperature Sensor 16 14 Yes 16 14 Yes 14 – HiRES ePWM Channels 1 Comparators w/ Integrated DACs 0 3 3 3 3 Inter-integrated circuit (I2C) 0 1 1 1 1 Enhanced Controller Area Network (eCAN) 0 1 1 1 1 Local Interconnect Network (LIN) 0 Serial Peripheral Interface (SPI) 1 Serial Communications Interface (SCI) 0 – AIO – 6 3 16 Yes 32-Bit CPU timers GPIO 3 16 Yes 7 6 1 1 6 1 2 1 1 33 3 7 33 6 1 2 1 1 45 3 7 1 2 1 1 45 33 7 2 1 45 33 45 I/O pins (shared) 6 6 6 6 External interrupts – 3 3 3 3 Supply voltage (nominal) – 3.3 V 3.3 V 3.3 V 3.3 V Temperature options T: - 40°C to 105°C – Yes Yes Yes Yes S: - 40°C to 125°C – TBD TBD TBD TBD – TMX TMX TMX TMX Product status 4 Hardware Features Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 2.1 Pin Assignments PRODUCT PREVIEW 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 GPIO28/SCIRXDA/SDAA/TZ2 GPIO9/EPWM5B/LINTXA TEST2 VDDIO VSS GPIO29/SCITXDA/SCLA/TZ3 GPIO30/CANRXA GPIO31/CANTXA ADCINB7 ADCINB6/COMP3B/AIO14 ADCINB4/COMP2B/AIO12 ADCINB3 ADCINB2/COMP1B/AIO10 ADCINB1 ADCINB0 VSSA/VREFLO ADCINA7 ADCINA6/COMP3A/AIO6 ADCINA4/COMP2A/AIO4 ADCINA3 ADCINA2/COMP1A/AIO2 ADCINA1 ADCINA0/VREFHI VDDA GPIO22/EQEP1S/LINTXA GPIO32/SDAA/EPWMSYNCI/ADCSOCAO GPIO33/SCLA/EPWMSYNCO/ADCSOCBO GPIO23/EQEP1I/LINRXA VDD VSS XRS TRST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GPIO11/EPWM6B/LINRXA GPIO5/EPWM3B/SPSIMOA/ECAP1 GPIO4/EPWM3A GPIO10/EPWM6A/ADCSOCBO GPIO3/EPWM2B/SPISOMIA/COMP2OUT GPIO2/EPWM2A GPIO1/EPWM1B/COMP1OUT GPIO0/EPWM1A VDDIO VSS VDD VREGENZ GPIO34/COMP2OUT/COMP3OUT GPIO20/EQEP1A/COMP1OUT GPIO21/EQEP1B/COMP2OUT GPIO24/ECAP1 40 39 38 37 36 35 34 33 48 47 46 45 44 43 42 41 GPIO36/TMS GPIO35/TDI GPIO37/TDO GPIO38/TCK/XCLKIN GPIO19/XCLKIN/SPISTEA/LINRXA/ECAP1 VDD VSS X1 X2 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO GPIO7/EPWM4B/SCIRXDA GPIO12/TZ1/SCITXDA GPIO16/SPISIMOA/TZ2 GPIO8/EPWM5A/ADCSOCAO GPIO17/SPISOMIA/TZ3 GPIO18/SPICLKA/LINTXA/XCLKOUT Figure 2-1 shows the 64-pin PAG Plastic Small Outline Package (TQFP) pin assignments. Figure 2-2 shows the 80-pin PN Plastic Quad Flatpack (LQFP) pin assignments. Figure 2-1. 2803x 64-Pin PAG TQFP (Top View) Submit Documentation Feedback Hardware Features 5 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers GPIO8/EPWM5A/ADCSOCAO GPIO17/SPISOMIA/TZ3 GPIO18/SPICLKA/LINTXA/XCLKOUT 43 42 41 GPIO44 GPIO25/SPISOMIB 46 44 GPIO16/SPISIMOA/TZ2 47 45 GPIO41/EPWM7B GPIO12/TZ1/SCITXDA/SPISIMOB 48 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO GPIO7/EPWM4B/SCIRXDA 50 49 X1 X2 VSS 51 VDD 54 53 52 GPIO39 GPIO19/XCLKIN/SPISTEA/LINRXA/ECAP1 56 57 55 GPIO37/TDO GPIO38/TCK/XCLKIN 58 GPIO36/TMS GPIO35/TDI 60 www.ti.com 59 SPRS584A – APRIL 2009 – REVISED MAY 2009 ADCINB4/COMP2B/AIO12 GPIO15/TZ1/LINRXA/SPISTEB 75 26 ADCINB3 GPIO13/TZ2/SPISOMIB 76 25 ADCINB2/COMP1B/AIO10 GPIO14/TZ3/LINTXA/SPICLKB 77 24 ADCINB1 GPIO20/EQEP1A/COMP1OUT 78 23 ADCINB0 GPIO21/EQEP1B/COMP2OUT 79 22 VREFLO GPIO24/ECAP1/SPISIMOB 80 21 VSSA 20 27 VDDA 74 18 ADCINB5 GPIO34/COMP2OUT/COMP3OUT 19 28 VREFHI 73 ADCINA0 ADCINB6/COMP3B/AIO14 VREGENZ 17 29 ADCINA1 72 15 ADCINB7 VDD 16 30 ADCINA3 71 ADCINA2/COMP1A/AIO2 GPIO27/SPISTEB VSS 13 31 14 70 ADCINA5 GPIO31/CANTXA VDDIO ADCINA4/COMP2A/AIO4 32 11 69 12 GPIO30/CANRXA GPIO0/EPWM1A ADCINA7 33 ADCINA6/COMP3A/AIO6 68 10 GPIO29/SCITXDA/SCLA/TZ3 GPIO1/EPWM1B/COMP1OUT TRST 34 9 67 XRS VSS GPIO2/EPWM2A 7 35 8 66 VSS VDDIO GPIO3/EPWM2B/SPISOMIA/COMP2OUT VDD 36 5 65 6 GPIO26/SPICLKB GPIO10/EPWM6A/ADCSOCBO GPIO42/COMP1OUT 37 GPIO43/COMP2OUT 64 3 TEST2 GPIO40/EPWM7A 4 38 GPIO23/EQEP1I/LINRXA 63 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO GPIO9/EPWM5B/LINTXA GPIO4/EPWM3A 1 GPIO28/SCIRXDA/SDAA/TZ2 39 2 40 62 GPIO22/EQEP1S/LINTXA 61 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO PRODUCT PREVIEW GPIO11/EPWM6B/LINRXA GPIO5/EPWM3B/SPISIMOA/ECAP1 Figure 2-2. 2803x 80-Pin PN LQFP (Top View) 6 Hardware Features Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 2.2 Signal Descriptions Table 2-2. TERMINAL FUNCTIONS (1) TERMINAL NAME PN PIN # PAG PIN # I/O/Z DESCRIPTION I JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: TRST is an active high test pin and must be maintained low at all times during normal device operation. An external pulldown resistor is recommended on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application. (↓) TRST 10 8 TCK See GPIO38 I See GPIO38. JTAG test clock with internal pullup (↑) TMS See GPIO36 I See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. (↑) TDI See GPIO35 I See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. (↑) TDO See GPIO37 O/Z See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. (8 mA drive) PRODUCT PREVIEW JTAG FLASH TEST2 38 30 I/O Test Pin. Reserved for TI. Must be left unconnected. O/Z See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin. CLOCK XCLKOUT See GPIO18 XCLKIN See GPIO19 and GPIO38 I See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default selection. This pin feeds a clock from an external 3.3-V oscillator. In this case, the X1 pin, if available, must be tied to GND and the on-chip crystal oscillator must be disabled via bit 14 in the CLKCTL register. If a crystal/resonator is used, the XCLKIN path must be disabled by bit 13 in the CLKCTL register. Note: Designs that use the GPIO38/TCK/XCLKIN pin to supply an external clock for normal device operation may need to incorporate some hooks to disable this path during debug using the JTAG connector. This is to prevent contention with the TCK signal, which is active during JTAG debug sessions. The zero-pin internal oscillators may be used during this time to clock the device. X1 52 41 I On-chip crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic resonator must be connected across X1 and X2. In this case, the XCLKIN path must be disabled by bit 13 in the CLKCTL register. If this pin is not used, it must be tied to GND. (I) X2 51 40 O On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be connected across X1 and X2. If X2 is not used, it must be left unconnected. (O) (1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown Submit Documentation Feedback Hardware Features 7 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Table 2-2. TERMINAL FUNCTIONS (continued) TERMINAL NAME PN PIN # PAG PIN # I/O/Z DESCRIPTION I/O Device Reset (in) and Watchdog Reset (out). Piccolo devices have a built-in power-on-reset (POR) and brown-out-reset (BOR) circuitry. As such, no external circuitry is needed to generate a reset pulse. During a power-on or brown-out condition, this pin is driven low by the device. See the electrical section for thresholds of the POR/BOR block. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. If need be, an external circuitry may also drive this pin to assert a device reset. In this case, it is recommended that this pin be driven by an open-drain device An R-C circuit must be connected to this pin for noise immunity reasons. Regardless of the source, a device reset causes the device to terminate execution. The program counter points to the address contained at the location 0x3FFFC0. When reset is deactivated, execution begins at the location designated by the program counter. The output buffer of this pin is an open-drain with an internal pullup. (I/OD) RESET XRS 9 7 PRODUCT PREVIEW ADC, COMPARATOR, ANALOG I/O ADCINA7 11 9 I ADC Group A, Channel 7 input ADCINA6 COMP3A AIO6 12 10 I I/O ADC Group A, Channel 6 input Comparator Input 3A Digital AIO 6 ADCINA5 13 – ADCINA4 COMP2A AIO4 14 11 I I I/O ADC Group A, Channel 4 input Comparator Input 2A Digital AIO 4 ADCINA3 15 12 I ADC Group A, Channel 3 input ADC Group A, Channel 2 input Comparator Input 1A Digital AIO 2 ADCINA2 COMP1A AIO2 16 13 I I I/O ADCINA1 17 14 I ADC Group A, Channel 1 input ADCINA0 18 15 I ADC Group A, Channel 0 input VREFHI 19 15 ADCINB7 30 24 I ADC Group B, Channel 7 input ADCINB6 COMP3B AIO14 29 23 I I/O ADC Group B, Channel 6 input Comparator Input 3B Digital AIO 14 ADCINB5 28 – ADCINB4 COMP2B AIO12 27 22 I I I/O ADC Group B, Channel 4 input Comparator Input 2B Digital AIO12 ADCINB3 26 21 I ADC Group B, Channel 3 input ADCINB2 COMP1B AIO10 25 20 I I I/O ADC Group B, Channel 2 input Comparator Input 1B Digital AIO 10 ADCINB1 24 19 I ADC Group B, Channel 1 input ADCINB0 23 18 VREFLO 22 17 ADC External Reference – only used when in ADC external reference mode. See ADC Section. CPU AND I/O POWER VDDA 20 16 Analog Power Pin VSSA 21 17 Analog Ground Pin VDD 7 5 VDD 54 43 VDD 72 59 8 Hardware Features CPU and Logic Digital Power Pins – no supply source needed when using internal VREG. Tie with 1.2 µF (minimum) ceramic capacitor to ground when using internal VREG. Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 Table 2-2. TERMINAL FUNCTIONS (continued) TERMINAL PN PIN # PAG PIN # VDDIO 36 29 VDDIO 70 57 VSS 8 6 VSS 35 28 VSS 53 42 VSS 71 58 NAME I/O/Z DESCRIPTION Digital I/O and Flash Power Pin – Single Supply source when VREG is enabled Digital Ground Pins VOLTAGE REGULATOR CONTROL SIGNAL VREGENZ 73 60 I Internal VREG Enable/Disable – pull low to enable VREG, pull high to disable VREG GPIO AND PERIPHERAL SIGNALS 69 56 I/O/Z General purpose input/output 0 EPWM1A O Enhanced PWM1 Output A and HRPWM channel – – – – – – GPIO1 68 55 EPWM1B I/O/Z O – 67 54 EPWM2A Enhanced PWM1 Output B O Direct output of Comparator 1 I/O/Z General purpose input/output 2 O – Enhanced PWM2 Output A and HRPWM channel – – GPIO3 General purpose input/output 1 – COMP1OUT GPIO2 – 66 53 I/O/Z General purpose input/output 3 EPWM2B O Enhanced PWM2 Output B SPISOMIA I/O SPI-A slave out, master in COMP2OUT O Direct output of Comparator 2 I/O/Z General purpose input/output 4 GPIO4 63 51 EPWM3A O – Enhanced PWM3 output A and HRPWM channel – – GPIO5 – 62 50 I/O/Z General purpose input/output 5 EPWM3B O Enhanced PWM3 output B SPISIMOA I/O SPI slave in, master out ECAP1 I/O Enhanced Capture input/output 1 GPIO6 50 39 I/O/Z General purpose input/output 6 EPWM4A O Enhanced PWM4 output A and HRPWM channel EPWMSYNCI I External ePWM sync pulse input EPWMSYNCO O External ePWM sync pulse output GPIO7 49 38 I/O/Z General purpose input/output 7 EPWM4B O Enhanced PWM4 output B SCIRXDA I SCI-A receive data – GPIO8 PRODUCT PREVIEW GPIO0 – 43 35 EPWM5A I/O/Z O – ADCSOCAO Submit Documentation Feedback General purpose input/output 8 Enhanced PWM5 output A – O ADC start-of-conversion A Hardware Features 9 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Table 2-2. TERMINAL FUNCTIONS (continued) TERMINAL NAME GPIO9 PN PIN # PAG PIN # I/O/Z 39 31 I/O/Z EPMW5B O LINTXA DESCRIPTION General purpose input/output 9 Enhanced PWM5 output B LIN transmit A – – GPIO10 65 52 EPWM6A I/O/Z O – General purpose input/output 10 Enhanced PWM6 output A – ADCSOCBO GPIO11 O 61 49 I/O/Z ADC start-of-conversion B General purpose input/output 11 PRODUCT PREVIEW EPWM6B Enhanced PWM6 output B LINRXA LIN receive A – – GPIO12 47 37 I/O/Z General purpose input/output 12 TZ1 I Trip Zone input 1 SCITXDA O SCI-A transmit data SPISIMOB I/O SPI slave in, master out GPIO13 76 – TZ2 I/O/Z I SPISOMIB I/O – General purpose input/output 13 Trip Zone input 2 SPI slave out, master in – GPIO14 77 – I/O/Z General purpose input/output 14 TZ3 I Trip zone input 3 LINTXA O LIN transmit I/O SPI-B clock input/output SPICLKB GPIO15 75 – I/O/Z General purpose input/output 15 TZ1 I Trip zone input 1 LINRXA I LIN receive SPISTEB GPIO16 I/O 46 36 SPISIMOA I/O/Z I/O – SPI-B slave transmit enable input/output General purpose input/output 16 SPI slave in, master out – TZ2 I GPIO17 42 34 SPISOMIA I/O/Z I/O – Trip Zone input 2 General purpose input/output 17 SPI-A slave out, master in – TZ3 I GPIO18 41 33 I/O/Z Trip zone input 3 General purpose input/output 18 SPICLKA I/O SPI-A clock input/output LINTXA O LIN transmit XCLKOUT (2) 10 (2) O/Z Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin. SPI-B peripheral is only available in the PN package Hardware Features Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 Table 2-2. TERMINAL FUNCTIONS (continued) TERMINAL NAME GPIO19 PN PIN # PAG PIN # I/O/Z 55 44 I/O/Z DESCRIPTION General purpose input/output 19 External Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken not to enable this path for clocking if it is being used for the other periperhal functions XCLKIN SPISTEA I/O SPI-A slave transmit enable input/output LINRXA I ECAP1 I/O Enhanced Capture input/output 1 I/O/Z General purpose input/output 20 GPIO20 78 62 EQEP1A I Enhanced QEP1 input A – COMP1OUT GPIO21 O 79 63 EQEP1B I/O/Z I – Direct output of Comparator 1 General purpose input/output 21 Enhanced QEP1 input B – COMP2OUT GPIO22 O 1 1 I/O/Z Direct output of Comparator 2 General purpose input/output 22 EQEP1S I/O Enhanced QEP1 strobe LINTXA O LIN transmit – – GPIO23 4 4 I/O/Z EQEP1I I/O LINRXA I – General purpose input/output 23 Enhanced QEP1 index LIN receive – GPIO24 I/O/Z General purpose input/output 24 ECAP1 I/O Enhanced Capture input/output 1 SPISIMOB I/O SPI-B slave in, master out 80 64 – (1) – GPIO25 44 - SPISOMIB I/O/Z I/O – General purpose input/output 25 SPI-B slave out , master in – – – GPIO26 37 - I/O/Z – General purpose input/output 26 – SPICLKB I/O – SPI-B clock input/output – GPIO27 31 - I/O/Z – General purpose input/output 27 – SPISTEB I/O – SPI-B slave transmit enable input/output – GPIO28 40 32 SCIRXDA SDAA TZ2 (1) PRODUCT PREVIEW – LIN receive I/O/Z I I/OC I General purpose input/output 28 SCI receive data I2C data open-drain bidirectional port Trip zone input 2 SPI-B peripheral is only available in the PN package Submit Documentation Feedback Hardware Features 11 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Table 2-2. TERMINAL FUNCTIONS (continued) TERMINAL NAME GPIO29 PN PIN # PAG PIN # I/O/Z 34 27 I/O/Z SCITXDA O SCLA I/OC TZ3 I GPIO30 33 26 CANRXA I/O/Z I – DESCRIPTION General purpose input/output 2 SCI transmit data I2C clock open-drain bidirectional port Trip zone input 3 General purpose input/output 30 CAN receive – – – GPIO31 32 25 PRODUCT PREVIEW CANTXA I/O/Z O – General purpose input/output 31 CAN transmit – – – GPIO32 2 2 SDAA I/O/Z General purpose input/output 32 I/OC I2C data open-drain bidirectional port EPWMSYNCI I Enhanced PWM external sync pulse input ADCSOCAO O ADC start-of-conversion A GPIO33 3 3 SCLA I/O/Z General-Purpose Input/Output 33 I/OC I2C clock open-drain bidirectional port EPWMSYNCO O Enhanced PWM external synch pulse output ADCSOCBO O ADC start-of-conversion B GPIO34 74 61 I/O/Z General-Purpose Input/Output 34 COMP2OUT O Direct output of Comparator 2 COMP3OUT O Direct output of Comparator 3 – – GPIO35 59 47 TDI I/O/Z I GPIO36 60 48 TMS I/O/Z I GPIO37 58 46 TDO GPIO38 57 45 General-Purpose Input/Output 35 JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK General-Purpose Input/Output 36 JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. I/O/Z General-Purpose Input/Output 37 O/Z JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA drive) I/O/Z General-Purpose Input/Output 38 TCK I JTAG test clock with internal pullup XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken to not enable this path for clocking if it is being used for the other functions. – – GPIO39 56 - I/O/Z General-Purpose Input/Output 39 – – – – – – GPIO40 64 EPWM7A - I/O/Z O General-Purpose Input/Output 40 Enhanced PWM7 output A – – – – 12 Hardware Features Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 Table 2-2. TERMINAL FUNCTIONS (continued) TERMINAL GPIO41 PN PIN # PAG PIN # I/O/Z 48 - I/O/Z EPWM7B O – - I/O/Z O – General-Purpose Input/Output 42 Direct output of Comparator 1 – – – 6 - COMP2OUT I/O/Z O – General-Purpose Input/Output 43 Direct output of Comparator 2 – – GPIO44 Enhanced PWM7 output B – 5 COMP1OUT GPIO43 General-Purpose Input/Output 41 – – GPIO42 DESCRIPTION PRODUCT PREVIEW NAME – 45 - I/O/Z General-Purpose Input/Output 44 – – – – – – Submit Documentation Feedback Hardware Features 13 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 3 Functional Overview 3.1 Block Diagram Memory Bus M0 SARAM 1Kx16 (0-wait) M1 SARAM 1Kx16 (0-wait) OTP 1K x 16 Secure SARAM 8K x 16 (CLA Only on 6K) (0-wait) Secure FLASH 32K/64K x 16 Secure Code Security Module Boot-ROM 8Kx16 (0-wait) OTP/Flash Wrapper PSWD CLA Bus PRODUCT PREVIEW Memory Bus CLA TRST COMP1A COMP1B COMP2A COMP2B COMP3A COMP3B COMP C28x 32-bit CPU 3 External Interrupts PIE CPU Timer 0 AIO CPU Timer 1 MUX CPU Timer 2 GPIO Mux XCLKIN OSC1, OSC2, Ext, PLL, LPM, WD X1 X2 LPM Wakeup XRS ADC A7:0 Memory Bus POR/ BOR B7:0 32-bit Peripheral Bus (CLA accessible) eCAN (32-mail box) eQEP EQE PxI EQ EPxB EQ EPxA ECA Px LINA T X From COMP1OUT, COMP2OUT, COMP3OUT L IN A RX ESYN C O EPW MxB TZx HRPWM CA N TXx eCAP C AN R Xx LIN EPW MxA SC L x SDA x SPIC LK x VREG 32-Bit Peripheral Bus ePWM I2C (4L FIFO) SPISTEx SPISOMIx SPI (4L FIFO) SPISIMO x SCIR XDx SC IT XD x SCI (4L FIFO) ESY NC I 16-bit Peripheral Bus EQEPxS MUX 32-bit periph eral bus ( C LA accessible) COMP1OUT COMP2OUT COMP3OUT GPIO TCK TDI TMS TDO GPIO MUX A. Not all peripheral pins are available at the same time due to multiplexing. Figure 3-1. Functional Block Diagram 14 Functional Overview Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 3.2 Memory Maps PRODUCT PREVIEW In Figure 3-2 and Figure 3-3, the following apply: • Memory blocks are not to scale. • Peripheral Frame 0, Peripheral Frame 1 and Peripheral Frame 2 memory maps are restricted to data memory only. A user program cannot access these memory maps in program space. • Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline order. • Certain memory ranges are EALLOW protected against spurious writes after configuration. • Locations 0x3D7C80 – 0x3D7CC0 contain the internal oscillator and ADC calibration routines. These locations are not programmable by the user. Submit Documentation Feedback Functional Overview 15 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Data Space 0x00 0000 M0 Vector RAM (Enabled if VMAP = 0) 0x00 0040 M0 SARAM (1K x 16, 0-Wait) 0x00 0400 M1 SARAM (1K x 16, 0-Wait) 0x00 0800 0x00 0D00 PRODUCT PREVIEW Low 64K (24x/240x Equivalent Data Space) Prog Space 0x00 0E00 Peripheral Frame 0 PIE Vector - RAM (256 x 16) (Enabled if VMAP = 1, ENPIE = 1) Reserved Peripheral Frame 0 0x00 2000 Reserved 0x00 6000 Peripheral Frame 1 (4K x 16, Protected) Reserved 0x00 7000 Peripheral Frame 2 (4K x 16, Protected) 0x00 8000 L0 SARAM (2K x 16) (0-Wait, Secure Zone + ECSL, Dual Mapped) 0x00 8800 L1 DPSARAM (1K x 16) (0-Wait, Secure Zone + ECSL, CLA Data RAM 0) 0x00 8C00 L2 DPSARAM (1K x 16) (0-Wait, Secure Zone + ECSL, CLA Data RAM 1) 0x00 9000 L3 DPSARAM (4K x 16) (0-Wait, Secure Zone + ECSL, CLA Prog RAM) 0x00 A000 Reserved 0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL) 0x3D 7C00 0x3D 7C80 0x3D 7CC0 0x3D 7CE0 0x3D 7E80 0x3D 7E81 Reserved Calibration Data Get_mode function Reserved PARTID Reserved High 64K (24x/240x Equivalent Program Space) 0x3D 8000 Reserved 0x3E 8000 0x3F 0000 0x3F 7FF8 0x3F 8000 0x3F 8800 FLASH (64K x 16, 8 Sectors, Secure Zone + ECSL) 128-Bit Password L0 SARAM (2K x 16) (0-Wait, Secure Zone + ECSL, Dual Mapped) Reserved 0x3F E000 Boot ROM (8K x 16, 0-Wait) 0x3F FFC0 Vector (32 Vectors, Enabled if VMAP = 1) Figure 3-2. 28034/28035 Memory Map 16 Functional Overview Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 Data Space 0x00 0000 M0 Vector RAM (Enabled if VMAP = 0) 0x00 0040 M0 SARAM (1K x 16, 0-Wait) 0x00 0400 0x00 0800 0x00 0D00 0x00 0E00 M1 SARAM (1K x 16, 0-Wait) Peripheral Frame 0 PIE Vector - RAM (256 x 16) (Enabled if VMAP = 1, ENPIE = 1) Reserved Peripheral Frame 0 0x00 2000 Reserved 0x00 6000 Peripheral Frame 1 (4K x 16, Protected) PRODUCT PREVIEW Low 64K (24x/240x Equivalent Data Space) Prog Space Reserved 0x00 7000 Peripheral Frame 2 (4K x 16, Protected) 0x00 8000 L0 SARAM (2K x 16) (0-Wait, Secure Zone + ECSL, Dual Mapped) 0x00 8800 L1 DPSARAM (1K x 16) (0-Wait, Secure Zone + ECSL, CLA Data RAM 0) 0x00 8C00 L2 DPSARAM (1K x 16) (0-Wait, Secure Zone + ECSL, CLA Data RAM 1) 0x00 9000 L3 DPSARAM (4K x 16) (0-Wait, Secure Zone + ECSL, CLA Prog RAM) 0x00 A000 Reserved 0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL) 0x3D 7C00 0x3D 7C80 0x3D 7CC0 0x3D 7CE0 0x3D 7E80 0x3D 7E81 Reserved Calibration Data Get_mode function Reserved PARTID Reserved High 64K (24x/240x Equivalent Program Space) 0x3D 8000 Reserved 0x3F 0000 0x3F 7FF8 0x3F 8000 0x3F 8800 FLASH (32K x 16, 8 Sectors, Secure Zone + ECSL) 128-Bit Password L0 SARAM (2K x 16) (0-Wait, Secure Zone + ECSL, Dual Mapped) Reserved 0x3F E000 Boot ROM (8K x 16, 0-Wait) 0x3F FFC0 Vector (32 Vectors, Enabled if VMAP = 1) Figure 3-3. 28032/28033 Memory Map Submit Documentation Feedback Functional Overview 17 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Table 3-1. Addresses of Flash Sectors in F28034/28035 ADDRESS RANGE PROGRAM AND DATA SPACE 0x3E 8000 - 0x3E 9FFF Sector H (8K x 16) 0x3E A000 - 0x3E BFFF Sector G (8K x 16) 0x3E C000 - 0x3E DFFF Sector F (8K x 16) 0x3E E000 - 0x3E FFFF Sector E (8K x 16) 0x3F 0000 - 0x3F 1FFF Sector D (8K x 16) 0x3F 2000 - 0x3F 3FFF Sector C (8K x 16) 0x3F 4000 - 0x3F 5FFF Sector B (8K x 16) PRODUCT PREVIEW 0x3F 6000 - 0x3F 7F7F Sector A (8K x 16) 0x3F 7F80 - 0x3F 7FF5 Program to 0x0000 when using the Code Security Module 0x3F 7FF6 - 0x3F 7FF7 Boot-to-Flash Entry Point (program branch instruction here) 0x3F 7FF8 - 0x3F 7FFF Security Password (128-Bit) (Do not program to all zeros) Table 3-2. Addresses of Flash Sectors in F28032/28033 ADDRESS RANGE PROGRAM AND DATA SPACE 0x3F 0000 - 0x3F 0FFF Sector H (4K x 16) 0x3F 1000 - 0x3F 1FFF Sector G (4K x 16) 0x3F 2000 - 0x3F 2FFF Sector F (4K x 16) 0x3F 3000 - 0x3F 3FFF Sector E (4K x 16) 0x3F 4000 - 0x3F 4FFF Sector D (4K x 16) 0x3F 5000 - 0x3F 5FFF Sector C (4K x 16) 0x3F 6000 - 0x3F 6FFF Sector B (4K x 16) 0x3F 7000 - 0x3F 7F7F Sector A (4K x 16) 0x3F 7F80 - 0x3F 7FF5 Program to 0x0000 when using the Code Security Module 0x3F 7FF6 - 0x3F 7FF7 Boot-to-Flash Entry Point (program branch instruction here) 0x3F 7FF8 - 0x3F 7FFF Security Password (128-Bit) (Do not program to all zeros) NOTE • When the code-security passwords are programmed, all addresses between 0x3F 7F80 and 0x3F 7FF5 cannot be used as program code or data. These locations must be programmed to 0x0000. • If the code security feature is not used, addresses 0x3F 7F80 through 0x3F 7FEF may be used for code or data. Addresses 0x3F 7FF0 – 0x3F 7FF5 are reserved for data and should not contain program code. Table 3-3 shows how to handle these memory locations. Table 3-3. Impact of Using the Code Security Module ADDRESS 0x3F 7F80 - 0x3F 7FEF 0x3F 7FF0 - 0x3F 7FF5 18 Functional Overview FLASH CODE SECURITY ENABLED Fill with 0x0000 CODE SECURITY DISABLED Application code and data Reserved for data only Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 Peripheral Frame 1 and Peripheral Frame 2 are grouped together to enable these blocks to be write/read peripheral block protected. The protected mode makes sure that all accesses to these blocks happen as written. Because of the pipeline, a write immediately followed by a read to different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications where the user expected the write to occur first (as written). The CPU supports a block protection mode where a region of memory can be protected so that operations occur as written (the penalty is extra cycles are added to align the operations). This mode is programmable and by default, it protects the selected zones. The wait-states for the various spaces in the memory map area are listed in Table 3-4. Table 3-4. Wait-states WAIT-STATES (CPU) 0-wait Peripheral Frame 0 0-wait Peripheral Frame 1 0-wait (writes) Peripheral Frame 2 0-wait (writes) COMMENTS Fixed PRODUCT PREVIEW AREA M0 and M1 SARAMs Cycles can be extended by peripheral generated ready. 2-wait (reads) Fixed. Cycles cannot be extended by the peripheral. 2-wait (reads) L0 SARAM 0-wait data and program Assumes no CPU conflicts L1 SARAM 0-wait data and program Assumes no CPU conflicts L2 SARAM 0-wait data and program Assumes no CPU conflicts L3 SARAM 0-wait data and program Assumes no CPU conflicts OTP Programmable Programmed via the Flash registers. 1-wait minimum 1-wait is minimum number of wait states allowed. Programmable Programmed via the Flash registers. FLASH 0-wait Paged min 1-wait Random min Random ≥ Paged FLASH Password 16-wait fixed Boot-ROM 0-wait Submit Documentation Feedback Wait states of password locations are fixed. Functional Overview 19 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 3.3 Brief Descriptions 3.3.1 CPU PRODUCT PREVIEW The 2803x (C28x) family is a member of the TMS320C2000™ microcontroller (MCU) platform. The C28x-based controllers have the same 32-bit fixed-point architecture as existing C28x MCUs. It is a very efficient C/C++ engine, enabling users to develop not only their system control software in a high-level language, but also enabling development of math algorithms using C/C++. The device is as efficient at MCU math tasks as it is at system control tasks that typically are handled by microcontroller devices. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC 64-bit processing capabilities enable the controller to handle higher numerical resolution problems efficiently. Add to this the fast interrupt response with automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency. The device has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables it to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional operations further improve performance. 3.3.2 Control Law Accelerator (CLA) The C28x control law accelerator is a single-precision (32-bit) floating-point unit that extends the capabilities of the C28x CPU by adding parallel processing. The CLA is an independent processor with its own bus structure, fetch mechanism, and pipeline. Eight individual CLA tasks, or routines, can be specified. Each task is started by software or a peripheral such as the ADC, an ePWM, or CPU Timer 0. The CLA executes one task at a time to completion. When a task completes the main CPU is notified by an interrupt to the PIE and the CLA automatically begins the next highest-priority pending task. The CLA can directly access the ADC Result registers and the ePWM+HRPWM registers. Dedicated message RAMs provide a method to pass additional data between the main CPU and the CLA. 3.3.3 Memory Bus (Harvard Bus Architecture) As with many MCU-type devices, multiple busses are used to move data between the memories and peripherals and the CPU. The memory bus architecture contains a program read bus, data read bus, and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to the memory bus prioritize memory accesses. Generally, the priority of memory bus accesses can be summarized as follows: Highest: Data Writes (Simultaneous data and program writes cannot occur on the memory bus.) Program Writes (Simultaneous data and program writes cannot occur on the memory bus.) Data Reads Lowest: 20 Program Reads (Simultaneous program reads and fetches cannot occur on the memory bus.) Fetches (Simultaneous program reads and fetches cannot occur on the memory bus.) Functional Overview Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com 3.3.4 SPRS584A – APRIL 2009 – REVISED MAY 2009 Peripheral Bus To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral bus are supported. One version supports only 16-bit accesses (called peripheral frame 2). Another version supports both 16- and 32-bit accesses (called peripheral frame 1). Real-Time JTAG and Analysis The devices implement the standard IEEE 1149.1 JTAG (1) interface for in-circuit based debug. Additionally, the devices support real-time mode of operation allowing modification of the contents of memory, peripheral, and register locations while the processor is running and executing code and servicing interrupts. The user can also single step through non-time-critical code while enabling time-critical interrupts to be serviced without interference. The device implements the real-time mode in hardware within the CPU. This is a feature unique to the 28x family of devices, requiring no software monitor. Additionally, special analysis hardware is provided that allows setting of hardware breakpoint or data/address watch-points and generating various user-selectable break events when a match occurs. These devices do not support boundary scan; however, IDCODE and BYPASS features are available if the following considerations are taken into account. The IDCODE does not come by default. The user needs to go through a sequence of SHIFT IR and SHIFT DR state of JTAG to get the IDCODE. For BYPASS instruction, the first shifted DR value would be 1. 3.3.6 Flash The F28035/34 devices contain 64K x 16 of embedded flash memory, segregated into eight 8K x 16 sectors. The F28033/32 devices contain 32K x 16 of embedded flash memory, segregated into eight 4K x 16 sectors. All devices also contain a single 1K x 16 of OTP memory at address range 0x3D 7800 – 0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms that erase/program other sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance. The flash/OTP is mapped to both program and data space; therefore, it can be used to execute code or store data information. Addresses 0x3F 7FF0 – 0x3F 7FF5 are reserved for data variables and should not contain program code. NOTE The Flash and OTP wait-states can be configured by the application. This allows applications running at slower frequencies to configure the flash to use fewer wait-states. Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options register. With this mode enabled, effective performance of linear code execution will be much faster than the raw performance indicated by the wait-state configuration alone. The exact performance gain when using the Flash pipeline mode is application-dependent. For more information on the Flash options, Flash wait-state, and OTP wait-state registers, see the TMS320x2803x Piccolo System Control and Interrupts Reference Guide (literature number SPRUGL8). 3.3.7 M0, M1 SARAMs All devices contain these two blocks of single access memory, each 1K x 16 in size. The stack pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute code or for data variables. The partitioning is performed within the linker. The C28x device presents a unified memory map to the programmer. This makes for easier programming in high-level languages. (1) IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture Submit Documentation Feedback Functional Overview 21 PRODUCT PREVIEW 3.3.5 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 3.3.8 www.ti.com L0, L1, L2, and L3 SARAMs The device contains a total of 8K x 16 of single-access memory. Block L0 is 2K in size and is dual mapped to both program and data space. Blocks L1 and L2 are both 1K in size and are shared with the CLA which can ultilize these blocks for its data space. Block L3 is 4K in size and is shared with the CLA which can ultilize this block for its program space. 3.3.9 Boot ROM The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell the bootloader software what boot mode to use on power up. The user can select to boot normally or to download new software from an external connection or to select boot software that is programmed in the internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math-related algorithms. PRODUCT PREVIEW Table 3-5. Boot Mode Selection MODE GPIO37/TDO GPIO34/COMP2OUT/ COMP3OUT TRST 3 1 1 0 GetMode 2 1 0 0 Wait (see Section 3.3.10 for description) 1 0 1 0 SCI 0 0 0 0 Parallel IO EMU x x 1 Emulation Boot MODE 3.3.9.1 Emulation Boot When the emulator is connected, the GPIO37/TDO pin cannot be used for boot mode selection. In this case, the boot ROM detects that an emulator is connected and uses the contents of two reserved SARAM locations in the PIE vector table to determine the boot mode. If the content of either location is invalid, then the Wait boot option is used. All boot mode options can be accessed in emulation boot. 3.3.9.2 GetMode The default behavior of the GetMode option is to boot to flash. This behavior can be changed to another boot option by programming two locations in the OTP. One of the following loaders can be specified: SCI, SPI, I2C, or OTP. If the content of either OTP location is invalid, then boot to flash is used 3.3.10 Security The devices support high levels of security to protect the user firmware from being reverse engineered. The security features a 128-bit password (hardcoded for 16 wait-states), which the user programs into the flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1 SARAM blocks. The security feature prevents unauthorized users from examining the memory contents via the JTAG port, executing code from external memory or trying to boot-load some undesirable software that would export the secure memory contents. To enable access to the secure blocks, the user must write the correct 128-bit KEY value that matches the value stored in the password locations within the Flash. In addition to the CSM, the emulation code security logic (ECSL) has been implemented to prevent unauthorized users from stepping through secure code. Any code or data access to flash, user OTP, or L0 memory while the emulator is connected will trip the ECSL and break the emulation connection. To allow emulation of secure code, while maintaining the CSM protection against secure memory reads, the user must write the correct value into the lower 64 bits of the KEY register, which matches the value stored in the lower 64 bits of the password locations within the flash. Note that dummy reads of all 128 bits of the password in the flash must still be performed. If the lower 64 bits of the password locations are all ones (unprogrammed), then the KEY value does not need to match. When initially debugging a device with the password locations in flash programmed (i.e., secured), the CPU will start running and may execute an instruction that performs an access to a protected ECSL area. If this happens, the ECSL will trip and cause the emulator connection to be cut. 22 Functional Overview Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 The solution is to use the Wait boot option. This will sit in a loop around a software breakpoint to allow an emulator to be connected without tripping security. Piccolo devices do not support a hardware wait-in-reset mode. NOTE When the code-security passwords are programmed, all addresses between 0x3F7F80 and 0x3F7FF5 cannot be used as program code or data. These locations must be programmed to 0x0000. • If the code security feature is not used, addresses 0x3F7F80 through 0x3F7FEF may be used for code or data. Addresses 0x3F7FF0 – 0x3F7FF5 are reserved for data and should not contain program code. The 128-bit password (at 0x3F 7FF8 – 0x3F 7FFF) must not be programmed to zeros. Doing so would permanently lock the device. PRODUCT PREVIEW • Disclaimer Code Security Module Disclaimer THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE. TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS. 3.3.11 Peripheral Interrupt Expansion (PIE) Block The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the F2803x, 54 of the possible 96 interrupts are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be enabled/disabled within the PIE block. Submit Documentation Feedback Functional Overview 23 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 3.3.12 External Interrupts (XINT1-XINT3) The devices support three masked external interrupts (XINT1-XINT3). Each of the interrupts can be selected for negative, positive, or both negative and positive edge triggering and can also be enabled/disabled. These interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. There are no dedicated pins for the external interrupts. XINT1, XINT2, and XINT3 interrupts can accept inputs from GPIO0 – GPIO31 pins. 3.3.13 Internal Zero Pin Oscillators, Oscillator, and PLL PRODUCT PREVIEW The device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a crystal attached to the on-chip oscillator circuit (48-pin devices only). A PLL is provided supporting up to 12 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is desired. Refer to the Electrical Specification section for timing details. The PLL block can be set in bypass mode. 3.3.14 Watchdog Each device contains two watchdogs: CPU-Watchdog that monitors the core and NMI-Watchdog that is a missing clock-detect circuit. The user software must regularly reset the CPU-watchdog counter within a certain time frame; otherwise, the CPU-watchdog generates a reset to the processor. The CPU-watchdog can be disabled if necessary. The NMI-Watchdog engages only in case of a clock failure and can either generate an interrupt or a device reset. 3.3.15 Peripheral Clocking The clocks to each individual peripheral can be enabled/disabled to reduce power consumption when a peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) can be scaled relative to the CPU clock. 3.3.16 Low-power Modes The devices are full static CMOS devices. Three low-power modes are provided: IDLE: Place CPU in low-power mode. Peripheral clocks may be turned off selectively and only those peripherals that need to function during IDLE are left operating. An enabled interrupt from an active peripheral or the watchdog timer will wake the processor from IDLE mode. STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional. An external interrupt event will wake the processor and the peripherals. Execution begins on the next valid cycle after detection of the interrupt event HALT: This mode basically shuts down the device and places it in the lowest possible power consumption mode. If the internal zero-pin oscillators are used as the clock source, the HALT mode turns them off, by default. To keep these oscillators from shutting down, the INTOSCnHALTI bits in CLKCTL register may be used. The zero-pin oscillators may thus be used to clock the CPU-watchdog in this mode. If the on-chip crystal oscillator is used as the clock source, it is shut down in this mode. A reset or an external signal (through a GPIO pin) or the CPU-watchdog can wake the device from this mode. 3.3.17 Peripheral Frames 0, 1, 2 (PFn) The device segregates peripherals into three sections. The mapping of peripherals is as follows: PF0: 24 PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector Table Flash: Flash Waitstate Registers Timers: CPU-Timers 0, 1, 2 Registers Functional Overview Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 PF1: PF2: CSM: Code Security Module KEY Registers ADC: ADC Result Registers CLA Control Law Accelrator Registers and Message RAMs GPIO: GPIO MUX Configuration and Control Registers eCAN: Enhanced Control Area Network Configuration and Control Registers LIN: Local Interconnect Network Configuration and Control Registers ePWM: Enhanced Pulse Width Modulator Module and Registers eCAP: Enhanced Capture Module and Registers eQEP: Enhanced Quadrature Encoder Pulse Module and Registers Comparators: Comparator Modules SYS: System Control Registers SCI: Serial Communications Interface (SCI) Control and RX/TX Registers SPI: Serial Port Interface (SPI) Control and RX/TX Registers ADC: ADC Status, Control, and Configuration Registers I2C: Inter-Integrated Circuit Module and Registers XINT: External Interrupt Registers 3.3.18 General-Purpose Input/Output (GPIO) Multiplexer Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power modes. 3.3.19 32-Bit CPU-Timers (0, 1, 2) CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is connected to INT14 of the CPU. It can be clocked by any one of the following: • • • • SYSCLKOUT (default) Internal zero-pin oscillator 1 (INTOSC1) Internal zero-pin oscillator 2 (INTSOC2) External clock source CPU-Timer 1 is for general use and can be connected to INT13 of the CPU. CPU-Timer 0 is also for general use and is connected to the PIE block. Submit Documentation Feedback Functional Overview 25 PRODUCT PREVIEW www.ti.com TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 3.3.20 Control Peripherals The devices support the following peripherals that are used for embedded control and communication: PRODUCT PREVIEW ePWM: The enhanced PWM peripheral supports independent/complementary PWM generation, adjustable dead-band generation for leading/trailing edges, latched/cycle-by-cycle trip mechanism. Some of the PWM pins support the HRPWM high resolution duty and period features. The type 1 module found on 2803x devices also supports increased dead-band resolution, enhanced SOC and interrupt generation, and advanced triggering including trip functions based on comparator outputs. eCAP: The enhanced capture peripheral uses a 32-bit time base and registers up to four programmable events in continuous/one-shot capture modes. This peripheral can also be configured to generate an auxiliary PWM signal. eQEP: The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed measurement using capture unit and high-speed measurement using a 32-bit unit timer. This peripheral has a watchdog timer to detect motor stall and input error detection logic to identify simultaneous edge transition in QEP signals. ADC: The ADC block is a 12-bit converter. It has up to 13 single-ended channels pinned out, depending on the device. It contains two sample-and-hold units for simultaneous sampling. Comparator: Each comparator block consists of one analog comparator along with an internal 10-bit reference for supplying one input of the comparator. 3.3.21 Serial Port Peripherals The devices support the following serial communication peripherals: 26 SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the MCU and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multi-device communications are supported by the master/slave operation of the SPI. The SPI contains a 4-level receive and transmit FIFO for reducing interrupt servicing overhead. SCI: The serial communications interface is a two-wire asynchronous serial port, commonly known as UART. The SCI contains a 4-level receive and transmit FIFO for reducing interrupt servicing overhead. I2C: The inter-integrated circuit (I2C) module provides an interface between a MCU and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the MCU through the I2C module. The I2C contains a 4-level receive and transmit FIFO for reducing interrupt servicing overhead. eCAN: This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time stamping of messages, and is CAN 2.0B-compliant. LIN: LIN 1.3 or 2.0 compatible peripheral. Can also be configured as additional SCI port Functional Overview Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 3.4 Register Map The devices contain four peripheral register spaces. The spaces are categorized as follows: Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus. See Table 3-6. Peripheral Frame 1 These are peripherals that are mapped to the 32-bit peripheral bus. See Table 3-7. Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See Table 3-8. NAME Device Emulation Registers FLASH Registers (3) ADDRESS RANGE SIZE (×16) EALLOW PROTECTED (2) 0x00 0880 - 0x00 09FF 384 Yes 0x00 0A80 - 0x00 0ADF 96 Yes Code Security Module Registers 0x00 0AE0 - 0x00 0AEF 16 Yes ADC registers (0 wait read only) 0x00 0B00 - 0x00 0B0F 16 No CPU–TIMER0/1/2 Registers 0x00 0C00 - 0x00 0C3F 64 No PIE Registers 0x00 0CE0 - 0x00 0CFF 32 No PIE Vector Table 0x00 0D00 - 0x00 0DFF 256 No CLA Registers 0x00 1400 - 0x00 147F 128 Yes CLA to CPU Message RAM (CPU writes ignored) 0x00 1480 - 0x00 14FF 128 NA CPU to CLA Message RAM (CLA writes ignored) 0x00 1500 - 0x00 157F 128 NA (1) (2) (3) PRODUCT PREVIEW Table 3-6. Peripheral Frame 0 Registers (1) Registers in Frame 0 support 16-bit and 32-bit accesses. If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction disables writes to prevent stray code or pointers from corrupting register contents. The Flash Registers are also protected by the Code Security Module (CSM). Table 3-7. Peripheral Frame 1 Registers NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED eCAN-A registers 0x00 6000 - 0x00 61FF 512 (1) Comparator 1 registers 0x00 6400 - 0x00 641F 32 (1) Comparator 2 registers 0x00 6420 - 0x00 643F 32 (1) Comparator 3 registers 0x00 6440 - 0x00 645F 32 (1) ePWM1 + HRPWM1 registers 0x00 6800 - 0x00 683F 64 (1) ePWM2 + HRPWM2 registers 0x00 6840 - 0x00 687F 64 (1) ePWM3 + HRPWM3 registers 0x00 6880 - 0x00 68BF 64 (1) ePWM4 + HRPWM4 registers 0x00 68C0 - 0x00 68FF 64 (1) ePWM5 + HRPWM5 registers 0x00 6900 - 0x00 693F 64 (1) ePWM6 + HRPWM6 registers 0x00 6940 - 0x00 697F 64 (1) ePWM7 + HRPWM7 registers 0x00 6980 - 0x00 69BF 64 (1) eCAP1 registers 0x00 6A00 - 0x00 6A1F 32 No eQEP1 registers 0x00 6B00 - 0x00 6B3F 64 (1) LIN-A registers 0x00 6C00 - 0x00 6C7F 128 (1) GPIO registers 0x00 6F80 - 0x00 6FFF 128 (1) (1) Some registers are EALLOW protected. See the module reference guide for more information. Submit Documentation Feedback Functional Overview 27 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Table 3-8. Peripheral Frame 2 Registers ADDRESS RANGE SIZE (×16) EALLOW PROTECTED System Control Registers NAME 0x00 7010 - 0x00 702F 32 Yes SPI-A Registers 0x00 7040 - 0x00 704F 16 No SCI-A Registers 0x00 7050 - 0x00 705F 16 No NMI Watchdog Interrupt Registers 0x00 7060 - 0x00 706F 16 Yes External Interrupt Registers 0x00 7070 - 0x00 707F 16 Yes ADC Registers 0x00 7100 - 0x00 717F 32 (1) I2C-A Registers 0x00 7900 - 0x00 793F 64 (1) SPI-B Registers 0x00 7740 - 0x00 774F 16 No (1) Some registers are EALLOW protected. See the module reference guide for more information. 3.5 Device Emulation Registers PRODUCT PREVIEW These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals. The registers are defined in Table 3-9. Table 3-9. Device Emulation Registers NAME DEVICECNF PARTID (1) CLASSID REVID (1) 28 ADDRESS RANGE SIZE (x16) 0x0880 0x0881 2 Device Configuration Register 0x3D 7E80 1 Part ID Register 0x0882 0x0883 1 1 EALLOW PROTECTED DESCRIPTION Class ID Register Revision ID Register Yes TMS320F28035PN 0x00BF TMS320F28035PAG 0x00BE TMS320F28034PN 0x00BB TMS320F28034PAG 0x00BA TMS320F28033PN 0x00B7 TMS320F28033PAG 0x00B6 TMS320F28032PN 0x00B3 TMS320F28032PAG 0x00B2 TMS320F28035 0x00BF TMS320F28034 0x00BB TMS320F28033 0x00B7 TMS320F28032 0x00B3 0x0000 - Silicon Rev. 0 - TMX No No No For TMS320F2803x devices, the PARTID register location differs from the TMS320F2802x devices' location of 0x3D7FFF. Functional Overview Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 3.6 Interrupts Figure 3-4 shows how the various interrupt sources are multiplexed. Peripherals (SPI, SCI, ePWM, I2C, HRPWM, eCAP, ADC, eQEP, CLA, LIN, eCAN) WDINT WAKEINT Sync Watchdog LPMINT Low Power Modes XINT1 Interrupt Control MUX SYSCLKOUT XINT1 GPIOXINT1SEL(4:0) ADC XINT2 XINT2SOC XINT2 Interrupt Control PRODUCT PREVIEW C28 Core XINT2CTR(15:0) MUX PIE INT1 to INT12 Up to 96 Interrupts XINT1CR(15:0) XINT2CR(15:0) XINT3CTR(15:0) GPIOXINT2SEL(4:0) XINT3 Interrupt Control MUX GPIO0.int XINT3 XINT3CR(15:0) GPIO MUX GPIO31.int XINT3CTR(15:0) GPIOXINT3SEL(4:0) TINT0 INT13 TINT1 INT14 TINT2 NMI CPU TIMER 0 CPU TIMER 1 CPU TIMER 2 NMI interrupt with watchdog function (See the NMI Watchdog section.) CPUTMR2CLK CLOCKFAIL NMIRS System Control (See the System Control section.) Figure 3-4. External and PIE Interrupt Sources Submit Documentation Feedback Functional Overview 29 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96 possible interrupts. Table 3-10 shows the interrupts used by 2803x devices. The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore, TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior. When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector from INT1.1, TRAP #2 fetches the vector from INT2.1, and so forth. IFR(12:1) IER(12:1) INTM PRODUCT PREVIEW INT1 INT2 1 CPU MUX 0 INT11 INT12 (Flag) INTx INTx.1 INTx.2 INTx.3 INTx.4 INTx.5 INTx.6 INTx.7 INTx.8 MUX PIEACKx (Enable/Flag) Global Enable (Enable) (Enable) (Flag) PIEIERx(8:1) PIEIFRx(8:1) From Peripherals or External Interrupts Figure 3-5. Multiplexing of Interrupts Using the PIE Block 30 Functional Overview Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 INT1.y INT2.y INT3.y INT4.y INT5.y INT6.y INT7.y INT8.y INT9.y INT10.y INT11.y INT12.y INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 WAKEINT TINT0 ADCINT9 XINT2 XINT1 Reserved ADCINT2 ADCINT1 (LPM/WD) (TIMER 0) (ADC) Ext. int. 2 Ext. int. 1 – (ADC) (ADC) 0xD4E 0xD4C 0xD4A 0xD48 0xD46 0xD44 0xD42 0xD40 Reserved EPWM7_TZINT EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT – (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1) 0xD5E 0xD5C 0xD5A 0xD58 0xD56 0xD54 0xD52 0xD50 Reserved EPWM7_INT EPWM6_INT EPWM5_INT EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT (ePWM1) – (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) 0xD6E 0xD6C 0xD6A 0xD68 0xD66 0xD64 0xD62 0xD60 Reserved Reserved Reserved Reserved Reserved Reserved Reserved ECAP1_INT (eCAP1) – – – – – – – 0xD7E 0xD7C 0xD7A 0xD78 0xD76 0xD74 0xD72 0xD70 Reserved Reserved Reserved Reserved Reserved Reserved Reserved EQEP1_INT (eQEP1) – – – – – – – 0xD8E 0xD8C 0xD8A 0xD88 0xD86 0xD84 0xD82 0xD80 Reserved Reserved Reserved Reserved SPITXINTB SPIRXINTB SPITXINTA SPIRXINTA (SPI-A) – – – – (SPI-B) (SPI-B) (SPI-A) 0xD9E 0xD9C 0xD9A 0xD98 0xD96 0xD94 0xD92 0xD90 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved – – – – – – – – 0xDAE 0xDAC 0xDAA 0xDA8 0xDA6 0xDA4 0xDA2 0xDA0 Reserved Reserved Reserved Reserved Reserved Reserved I2CINT2A I2CINT1A – – – – – – (I2C-A) (I2C-A) 0xDBE 0xDBC 0xDBA 0xDB8 0xDB6 0xDB4 0xDB2 0xDB0 Reserved Reserved ECAN1_INTA ECAN0_INTA LIN1_INTA LIN0_INTA SCITXINTA SCIRXINTA (SCI-A) – – (CAN-A) (CAN-A) (LIN-A) (LIN-A) (SCI-A) 0xDCE 0xDCC 0xDCA 0xDC8 0xDC6 0xDC4 0xDC2 0xDC0 ADCINT8 ADCINT7 ADCINT6 ADCINT5 ADCINT4 ADCINT3 ADCINT2 ADCINT1 (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) 0xDDE 0xDDC 0xDDA 0xDD8 0xDD6 0xDD4 0xDD2 0xDD0 CLA1_INT8 CLA1_INT7 CLA1_INT6 CLA1_INT5 CLA1_INT4 CLA1_INT3 CLA1_INT2 CLA1_INT1 (CLA) (CLA) (CLA) (CLA) (CLA) (CLA) (CLA) (CLA) 0xDEE 0xDEC 0xDEA 0xDE8 0xDE6 0xDE4 0xDE2 0xDE0 LUF LVF Reserved Reserved Reserved Reserved Reserved XINT3 (CLA) (CLA) – – – – – Ext. Int. 3 0xDFE 0xDFC 0xDFA 0xDF8 0xDF6 0xDF4 0xDF2 0xDF0 Submit Documentation Feedback Functional Overview PRODUCT PREVIEW Table 3-10. PIE MUXed Peripheral Interrupt Vector Table 31 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Table 3-11. PIE Configuration and Control Registers NAME PRODUCT PREVIEW SIZE (x16) PIECTRL 0x0CE0 1 PIE, Control Register PIEACK 0x0CE1 1 PIE, Acknowledge Register PIEIER1 0x0CE2 1 PIE, INT1 Group Enable Register PIEIFR1 0x0CE3 1 PIE, INT1 Group Flag Register PIEIER2 0x0CE4 1 PIE, INT2 Group Enable Register PIEIFR2 0x0CE5 1 PIE, INT2 Group Flag Register PIEIER3 0x0CE6 1 PIE, INT3 Group Enable Register PIEIFR3 0x0CE7 1 PIE, INT3 Group Flag Register PIEIER4 0x0CE8 1 PIE, INT4 Group Enable Register PIEIFR4 0x0CE9 1 PIE, INT4 Group Flag Register PIEIER5 0x0CEA 1 PIE, INT5 Group Enable Register PIEIFR5 0x0CEB 1 PIE, INT5 Group Flag Register PIEIER6 0x0CEC 1 PIE, INT6 Group Enable Register PIEIFR6 0x0CED 1 PIE, INT6 Group Flag Register PIEIER7 0x0CEE 1 PIE, INT7 Group Enable Register PIEIFR7 0x0CEF 1 PIE, INT7 Group Flag Register PIEIER8 0x0CF0 1 PIE, INT8 Group Enable Register PIEIFR8 0x0CF1 1 PIE, INT8 Group Flag Register PIEIER9 0x0CF2 1 PIE, INT9 Group Enable Register PIEIFR9 0x0CF3 1 PIE, INT9 Group Flag Register PIEIER10 0x0CF4 1 PIE, INT10 Group Enable Register PIEIFR10 0x0CF5 1 PIE, INT10 Group Flag Register PIEIER11 0x0CF6 1 PIE, INT11 Group Enable Register PIEIFR11 0x0CF7 1 PIE, INT11 Group Flag Register PIEIER12 0x0CF8 1 PIE, INT12 Group Enable Register PIEIFR12 0x0CF9 1 PIE, INT12 Group Flag Register Reserved 0x0CFA 0x0CFF 6 Reserved (1) 3.6.1 DESCRIPTION (1) ADDRESS The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected. External Interrupts Table 3-12. External Interrupt Registers NAME 32 ADDRESS SIZE (x16) XINT1CR 0x00 7070 1 XINT1 configuration register XINT2CR 0x00 7071 1 XINT2 configuration register XINT3CR 0x00 7072 1 XINT3 configuration register XINT1CTR 0x00 7078 1 XINT1 counter register XINT2CTR 0x00 7079 1 XINT2 counter register XINT3CTR 0x00 707A 1 XINT3 counter register Functional Overview DESCRIPTION Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and negative edge. For more information, see the TMS320x2803x Piccolo System Control and Interrupts Reference Guide (literature number SPRUGL8). 3.7 VREG/BOR/POR Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip voltage regulator (VREG) to generate the VDD voltage from the VDDIO supply. This eliminates the cost and space of a second external regulator on an application board. Additionally, internal power-on reset (POR) and brown-out reset (BOR) circuits monitor both the VDD and VDDIO rails during power-up and run mode, eliminating a need for any external voltage supervisory circuits. On-chip Voltage Regulator (VREG) A linear regulator generates the core voltage (VDD) from the VDDIO supply. Therefore, although capacitors are required on each VDD pin to stabilize the generated voltage, power need not be supplied to these pins to operate the device. Conversely, the VREG can be disabled, should power or redundancy be the primary concern of the application. 3.7.1.1 Using the On-chip VREG To utilize the on-chip VREG, the VREGENZ pin should be pulled low and the appropriate recommended operating voltage should be supplied to the VDDIO and VDDA pins. In this case, the VDD voltage needed by the core logic will be generated by the VREG. Each VDD pin requires on the order of 1.2 µF (minimum) capacitance for proper regulation of the VREG. These capacitors should be located as close as possible to the VDD pins. 3.7.1.2 Disabling the On-chip VREG To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to the VDD pins with a more efficient external regulator. To enable this option, the VREGENZ pin must be pulled high. 3.7.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit Two on-chip supervisory circuits, the power-on reset (POR) and the brown-out reset (BOR) remove the burden of monitoring the VDD and VDDIO supply rails from the application board. The purpose of the POR is to create a clean reset throughout the device during the entire power-up procedure. The trip point is a looser, lower trip point than the BOR, which watches for dips in the VDD or VDDIO rail during device operation. The POR function is present on both VDD and VDDIO rails at all times. After initial device power-up, the BOR function is present on VDDIO at all times, and on VDD when the internal VREG is enabled (VREGENZ pin is pulled low). Both functions pull the XRS pin low when one of the voltages is below their respective trip point. See Section 6 for the various trip points as well as the delay time from the voltage rising past the trip point and the release of the XRS pin. Figure 3-6 shows the VREG, POR, and BOR. Submit Documentation Feedback Functional Overview 33 PRODUCT PREVIEW 3.7.1 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com In I/O Pin Out (Force Hi-Z When High) DIR (0 = Input, 1 = Output) SYSRS Internal Weak PU SYSCLKOUT PRODUCT PREVIEW Deglitch Filter XRS Sync RS MCLKRS PLL + Clocking Logic XRS Pin C28 Core JTAG TCK Detect Logic VREGHALT (A) WDRST (B) PBRS POR/BOR Generating Module A. WDRST is the reset signal from the CPU-watchdog. B. PBRS is the reset signal from the POR/BOR module. On-Chip Voltage Regulator (VREG) VREGENZ Figure 3-6. VREG + POR + BOR + Reset Signal Connectivity 34 Functional Overview Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 3.8 System Control This section describes the oscillator and clocking mechanisms, the watchdog function and the low power modes. Table 3-13. PLL, Clocking, Watchdog, and Low-Power Mode Registers DESCRIPTION (1) ADDRESS SIZE (x16) XCLK 0x00 7010 1 XCLKOUT Control PLLSTS 0x00 7011 1 PLL Status Register CLKCTL 0x00 7012 1 Clock Control Register PLLLOCKPRD 0x00 7013 1 PLL Lock Period INTOSC1TRIM 0x00 7014 1 Internal Oscillator 1 Trim Register INTOSC2TRIM 0x00 7016 1 Internal Oscillator 2 Trim Register LOSPCP 0x00 701B 1 Low-Speed Peripheral Clock Prescaler Register PCLKCR0 0x00 701C 1 Peripheral Clock Control Register 0 PCLKCR1 0x00 701D 1 Peripheral Clock Control Register 1 LPMCR0 0x00 701E 1 Low Power Mode Control Register 0 PCLKCR3 0x00 7020 1 Peripheral Clock Control Register 3 PLLCR 0x00 7021 1 PLL Control Register SCSR 0x00 7022 1 System Control and Status Register WDCNTR 0x00 7023 1 Watchdog Counter Register WDKEY 0x00 7025 1 Watchdog Reset Key Register WDCR 0x00 7029 1 Watchdog Control Register (1) PRODUCT PREVIEW NAME All registers in this table are EALLOW protected. Submit Documentation Feedback Functional Overview 35 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Figure 3-7 shows the various clock domains that are discussed. Figure 3-8 shows the various clock sources (both internal and external) that can provide a clock for device operation. SYSCLKOUT LOSPCP (System Ctrl Regs) PCLKCR0/1/3 (System Ctrl Regs) Clock Enables I/O CLKIN LSPCLK SPI-A, SPI-B, SCI-A Clock Enables I/O C28x Core eCAN-A, LIN-A Peripheral Registers PF2 /2 PRODUCT PREVIEW Peripheral Registers PF1 Peripheral Registers PF1 Peripheral Registers PF1 Peripheral Registers PF2 Clock Enables GPIO Mux I/O eCAP1, eQEP1 Clock Enables I/O ePWM1/.../7 Clock Enables I/O I2C-A Clock Enables 16 Ch ADC Registers PF2 PF0 Analog GPIO Mux Clock Enables 6 A. 12-Bit ADC COMP1/2/3 COMP Registers PF1 CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency as SYSCLKOUT). Figure 3-7. Clock and Reset Domains 36 Functional Overview Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 CLKCTL[WDCLKSRCSEL] INTOSC1TRIM Reg Internal OSC 1 (10 MHz) (A) 0 OSC1CLK OSCCLKSRC1 WDCLK CPU-watchdog (OSC1CLK on XRS reset) OSCE 1 CLKCTL[INTOSC1OFF] 1 = Turn OSC Off PRODUCT PREVIEW CLKCTL[OSCCLKSRCSEL] CLKCTL[INTOSC1HALT] WAKEOSC 1 = Ignore HALT INTOSC2TRIM Reg Internal OSC2CLK OSC 2 (10 MHz) (A) 0 OSCCLK PLL Missing-Clock-Detect Circuit (OSC1CLK on XRS reset) (B) 1 OSCE CLKCTL[TRM2CLKPRESCALE] CLKCTL[TMR2CLKSRCSEL] 1 = Turn OSC Off 10 CLKCTL[INTOSC2OFF] 11 1 = Ignore HALT 1 Prescale /1, /2, /4, /8, /16 01, 10, 11 CPUTMR2CLK 01 00 CLKCTL[INTOSC2HALT] SYSCLKOUT OSCCLKSRC2 0 0 = GPIO38 1 = GPIO19 XCLK[XCLKINSEL] SYNC Edge Detect CLKCTL[OSCCLKSRC2SEL] CLKCTL[XCLKINOFF] 0 XCLKIN GPIO19 or GPIO38 1 0 XCLKIN X1 (Crystal) OSC XTAL EXTCLK WAKEOSC (Oscillators enabled when this signal is high) X2 CLKCTL[XTALOSCOFF] 0 = OSC on (default on reset) 1 = Turn OSC off A. Register loaded from TI OTP-based calibration function. B. See Section 3.8.4 for details on missing clock detection. Figure 3-8. Clock Tree Submit Documentation Feedback Functional Overview 37 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 3.8.1 www.ti.com Internal Zero Pin Oscillators The F2803x devices contain two independent internal zero pin oscillators. By default both oscillators are turned on at power up, and internal oscillator 1 is the default clock source at this time. For power savings, unused oscillators may be powered down by the user. The center frequency of these oscillators is determined by their respective oscillator trim registers, written to in the calibration routine as part of the boot ROM execution. See the electrical section for more information on these oscillators. 3.8.2 Crystal Oscillator Option The typical specifications for the external quartz crystal (fundamental mode, parallel resonant) are listed in Table 3-14. Furthermore, ESR range = 30 to 150 Ω. Table 3-14. Typical Specifications for External Quartz Crystal PRODUCT PREVIEW FREQUENCY (MHz) Rd (Ω) CL1 (pF) CL2 (pF) CL (pF) 5 2200 18 18 12 10 470 15 15 12 15 0 12 15 12 20 0 12 12 12 XCLKIN/GPIO19/38 Turn off XCLKIN path in CLKCTL register A. X1 X2 Rbias CL1 Rd CL2 Crystal X1/X2 pins are available in 48-pin package only. Figure 3-9. Using the On-chip Crystal Oscillator NOTE 1. CL1 and CL2 are the total capacitance of the circuit board and components excluding the IC and crystal. The value is usually approximately twice the value of the crystal's load capacitance. 2. Rbias is generally 2.0 MΩ. 3. The load capacitance of the crystal is described in the crystal specifications of the manufacturers. 4. TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the MCU chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding the proper tank component values that will produce proper start up and stability over the entire operating range. XCLKIN/GPIO19/38 External Clock Signal (Toggling 0−VDDIO) X1 X2 NC Figure 3-10. Using a 3.3-V External Oscillator 38 Functional Overview Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com 3.8.3 SPRS584A – APRIL 2009 – REVISED MAY 2009 PLL-Based Clock Module The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes 1 ms. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the PLL (VCOCLK) is at least 50 MHz. Table 3-15. PLL Settings (1) (2) (3) SYSCLKOUT (CLKIN) PLLSTS[DIVSEL] = 0 or 1 (3) PLLSTS[DIVSEL] = 2 PLLSTS[DIVSEL] = 3 0000 (PLL bypass) OSCCLK/4 (Default) (1) OSCCLK/2 OSCCLK 0001 (OSCCLK * 1)/4 (OSCCLK * 1)/2 – 0010 (OSCCLK * 2)/4 (OSCCLK * 2)/2 – 0011 (OSCCLK * 3)/4 (OSCCLK * 3)/2 – 0100 (OSCCLK * 4)/4 (OSCCLK * 4)/2 – 0101 (OSCCLK * 5)/4 (OSCCLK * 5)/2 – 0110 (OSCCLK * 6)/4 (OSCCLK * 6)/2 – 0111 (OSCCLK * 7)/4 (OSCCLK * 7)/2 – 1000 (OSCCLK * 8)/4 (OSCCLK * 8)/2 – 1001 (OSCCLK * 9)/4 (OSCCLK * 9)/2 – 1010 (OSCCLK * 10)/4 (OSCCLK * 10)/2 – 1011 (OSCCLK * 11)/4 (OSCCLK * 11)/2 – 1100 (OSCCLK * 12)/4 (OSCCLK * 12)/2 – The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog reset only. A reset issued by the debugger or the missing clock detect logic has no effect. This register is EALLOW protected. See the TMS320x2803x Piccolo System Control and Interrupts Reference Guide (literature number SPRUGL8 ) for more information. By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /1.) PLLSTS[DIVSEL] must be 0 before writing to the PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1. Table 3-16. CLKIN Divide Options (1) PLLSTS [DIVSEL] CLKIN DIVIDE 0 /4 1 /4 2 /2 3 /1 (1) This mode can be used only when the PLL is bypassed or off. The PLL-based clock module provides four modes of operation: • INTOSC1 (Internal Zero-pin Oscillator 1): This is the on-chip internal oscillator 1. This can provide the clock for the Watchdog block, core and CPU-Timer 2 • INTOSC2 (Internal Zero-pin Oscillator 2): This is the on-chip internal oscillator 2. This can provide the clock for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can be independently chosen for the Watchdog block, core and CPU-Timer 2. • Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an external crystal/resonator attached to the device to provide the time base. The crystal/resonator is connected to the X1/X2 pins. Some devices may not have the X1/X2 pins. See for details. • External Clock Source Operation: If the on-chip (crystal) oscillator is not used, this mode allows it to be bypassed. The device clocks are generated from an external clock source input on the XCLKIN pin. Note that the XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The XCLKIN input can be selected as GPIO19 or GPIO38 via the XCLKINSEL bit in XCLK register. The CLKCTL[XCLKINOFF] bit Submit Documentation Feedback Functional Overview 39 PRODUCT PREVIEW PLLCR[DIV] VALUE (1) (2) TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com disables this clock input (forced low). If the clock source is not used or the respective pins are used as GPIOs, the user should disable at boot time. Before changing clock sources, ensure that the target clock is present. If a clock is not present, then that clock source must be disabled (using the CLKCTL register) before switching clocks. Table 3-17. Possible PLL Configuration Modes REMARKS PLLSTS[DIVSEL] CLKIN AND SYSCLKOUT Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block is disabled in this mode. This can be useful to reduce system noise and for low power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass) before entering this mode. The CPU clock (CLKIN) is derived directly from the input clock on either X1/X2, X1 or XCLKIN. 0, 1 2 3 OSCCLK/4 OSCCLK/2 OSCCLK/1 0, 1 2 3 OSCCLK/4 OSCCLK/2 OSCCLK/1 0, 1 2 OSCCLK*n/4 OSCCLK*n/2 PLL MODE PLL Off PRODUCT PREVIEW PLL Bypass is the default PLL configuration upon power-up or after an external reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or PLL Bypass while the PLL locks to a new frequency after the PLLCR register has been modified. In this mode, the PLL itself is bypassed but the PLL is not turned off. PLL Enable 3.8.4 Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the PLLCR the device will switch to PLL Bypass mode until the PLL locks. Loss of Input Clock (NMI Watchdog Function) The 2803x devices may be clocked from either one of the internal zero-pin oscillators (INTOSC1/INTOSC2), the on-chip crystal oscillator, or from an external clock input. Regardless of the clock source, in PLL-enabled and PLL-bypass mode, if the input clock to the PLL vanishes, the PLL will issue a limp-mode clock at its output. This limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1-5 MHz. When the limp mode is activated, a CLOCKFAIL signal is generated that is latched as an NMI interrupt. Depending on how the NMIRESETSEL bit has been configured, a reset to the device can be fired immediately or the NMI watchdog counter can issue a reset when it overflows. In addition to this, the Missing Clock Status (MCLKSTS) bit is set. The NMI interrupt could be used by the application to detect the input clock failure and initiate necessary corrective action such as switching over to an alternative clock source (if available) or initiate a shut-down procedure for the system. If the software does not respond to the clock-fail condition, the NMI watchdog triggers a reset after a preprogrammed time interval. Figure 3-11 shows the interrupt mechanisms involved. 40 Functional Overview Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 NMIFLG[NMINT] NMIFLGCLR[NMINT] Clear Latch Set Clear XRS NMINT Generate Interrupt Pulse When Input = 1 1 0 NMIFLG[CLOCKFAIL] Clear Latch Clear Set 0 NMIFLGCLR[CLOCKFAIL] CLOCKFAIL SYNC? SYSCLKOUT XRS NMIFLGFRC[CLOCKFAIL] SYSCLKOUT SYSRS NMIWDPRD[15:0] NMIWDCNT[15:0] NMI Watchdog NMIRS See System Control Section Figure 3-11. NMI-watchdog 3.8.5 CPU-Watchdog Module The CPU-watchdog module on the 2803x device is similar to the one used on the 281x/280x/283xx devices. This module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value. To prevent this, the user must disable the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register that resets the watchdog counter. Figure 3-12 shows the various functional blocks within the watchdog module. Normally, when the input clocks are present, the CPU-watchdog counter decrements to initiate a CPU-watchdog reset or WDINT interrupt. However, when the external input clock fails, the CPU-watchdog counter stops decrementing (i.e., the watchdog counter does not change with the limp-mode clock). NOTE The CPU-watchdog is different from the NMI watchdog. It is the legacy watchdog that is present in all 28x devices. NOTE Applications in which the correct CPU operating frequency is absolutely critical should implement a mechanism by which the MCU will be held in reset, should the input clocks ever fail. For example, an R-C circuit may be used to trigger the XRS pin of the MCU, should the capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent it from getting fully charged. Such a circuit would also help in detecting failure of the flash memory. Submit Documentation Feedback Functional Overview 41 PRODUCT PREVIEW NMICFG[CLOCKFAIL] TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com WDCR (WDPS[2:0]) WDCR (WDDIS) WDCNTR(7:0) WDCLK Watchdog Prescaler /512 WDCLK 8-Bit Watchdog Counter CLR Clear Counter Internal Pullup WDKEY(7:0) Watchdog 55 + AA Key Detector WDRST Generate Output Pulse WDINT (512 OSCCLKs) Good Key PRODUCT PREVIEW XRS Bad WDCHK Key Core-reset WDCR (WDCHK[2:0]) 1 WDRST(A) A. 0 SCSR (WDENINT) 1 The WDRST signal is driven low for 512 OSCCLK cycles. Figure 3-12. CPU-watchdog Module The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode. In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is the CPU-watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section 3.9, Low-power Modes Block, for more details. In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE mode. In HALT mode, the CPU-watchdog can be used to wake up the device through a device reset. 3.9 Low-power Modes Block Table 3-18 summarizes the various modes. Table 3-18. Low-power Modes EXIT (1) MODE LPMCR0(1:0) OSCCLK CLKIN SYSCLKOUT IDLE 00 On On On XRS, CPU-watchdog interrupt, any enabled interrupt STANDBY 01 On (CPU-watchdog still running) Off Off XRS, CPU-watchdog interrupt, GPIO Port A signal, debugger (2) 1X Off (on-chip crystal oscillator and PLL turned off, zero-pin oscillator and CPU-watchdog state dependent on user code.) Off Off XRS, GPIO Port A signal, debugger (2), CPU-watchdog HALT (1) (2) (3) 42 (3) The Exit column lists which signals or under what conditions the low power mode is exited. A low signal, on any of the signals, exits the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the low-power mode will not be exited and the device will go back into the indicated low power mode. The JTAG port can still function even if the CPU clock (CLKIN) is turned off. The WDCLK must be active for the device to go into HALT mode. Functional Overview Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 The various low-power modes operate as follows: This mode is exited by any enabled interrupt that is recognized by the processor. The LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0. STANDBY Mode: Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY mode. The user must select which signal(s) will wake the device in the GPIOLPMSEL register. The selected signal(s) are also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the LPMCR0 register. HALT Mode: CPU-watchdog, XRS, and any GPIO port A signal (GPIO[31:0]) can wake the device from HALT mode. The user selects the signal in the GPIOLPMSEL register. PRODUCT PREVIEW IDLE Mode: NOTE The low-power modes do not affect the state of the output pins (PWM pins included). They will be in whatever state the code left them in when the IDLE instruction was executed. See the TMS320x2803x Piccolo System Control and Interrupts Reference Guide (literature number SPRUGL8) for more details. Submit Documentation Feedback Functional Overview 43 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 4 Peripherals 4.1 Control Law Accelerator (CLA) Overview PRODUCT PREVIEW The control law accelerator extends the capabilities of the C28x CPU by adding parallel processing. Time-critical control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA enables faster system response and higher frequency control loops. Utilizing the CLA for time-critical tasks frees up the main CPU to perform other system and communication functions concurently. The following is a list of major features of the CLA. • Clocked at the same rate as the main CPU (SYSCLKOUT). • An independent architecture allowing CLA algorithm execution independent of the main C28x CPU. – Complete bus architecture: • Program address bus and program data bus • Data address bus, data read bus, and data write bus – Independent eight-stage pipeline. – 12-bit program counter (MPC) – Four 32-bit result registers (MR0–MR3) – Two 16-bit auxillary registers (MAR0, MAR1) – Status register (MSTF) • Instruction set includes: – IEEE single-precision (32-bit) floating-point math operations – Floating-point math with parallel load or store – Floating-point multiply with parallel add or subtract – 1/X and 1/sqrt(X) estimations – Data type conversions. – Conditional branch and call – Data load/store operations • The CLA program code can consist of up to eight tasks or interrupt service routines. – The start address of each task is specified by the MVECT registers. – No limit on task size as long as the tasks fit within the CLA program memory space. – One task is serviced at a time through to completion. There is no nesting of tasks. – Upon task completion, a task-specific interrupt is flagged within the PIE. – When a task finishes, the next highest-priority pending task is automatically started. • Task trigger mechanisms: – C28x CPU via the IACK instruction – Task1 to Task7: the corresponding ADC or ePWM module interrupt. For example: • Task1: ADCINT1 or EPWM1_INT • Task2: ADCINT2 or EPWM2_INT • Task7: ADCINT7 or EPWM7_INT – Task8: ADCINT8 or by CPU Timer 0. • Memory and Shared Peripherals: – Two dedicated message RAMs for communication between the CLA and the main CPU. – The C28x CPU can map CLA program and data memory to the main CPU space or CLA space. – The CLA has direct access to the ADC Result registers, comparator registers, and the ePWM+HRPWM registers. 44 Peripherals Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 IACK Peripheral Interrupts CLA Control Registers CPU Timer 0 CLA_INT1 to CLA_INT8 MPISRCSEL1 CLA Program Data Bus Map to CLA or CPU Space Main CPU BUS LVF LUF Main CPU Read/Write Data Bus MVECT1 MVECT2 MVECT3 MVECT4 MVECT5 MVECT6 MVECT7 MVECT8 CLA Program Address Bus CLA Program Memory MMEMCFG CLA Data Memory Map to CLA or CPU Space MCTL SYSCLKOUT CLAENCLK SYSRS CLA Shared Message RAMs CLA Execution Registers MPC(12) MSTF(32) MR0(32) MR1(32) MR2(32) MR3(32) MAR0(32) MAR1(32) Main CPU Read Data Bus Main 28x CPU INT11 INT12 PIE MEALLOW CLA Data Read Address Bus CLA Data Read Data Bus CLA Data Write Address Bus PRODUCT PREVIEW MIFR MIOVF MICLR MICLROVF MIFRC MIER MIRUN MPERINT1 to MPERINT8 CLA Data Bus EPWM1_INT to EPWM8_INT INT Main CPU Bus ADCINT1 to ADCINT8 ADC Result Registers ePWM and HRPWM Registers CLA Data Write Data Bus Comparator Registers Figure 4-1. CLA Block Diagram Table 4-1. CLA Control Registers (1) REGISTER NAME CLA1 ADDRESS SIZE (x16) EALLOW PROTECTED MVECT1 0x1400 1 Yes CLA Interrupt/Task 1 Start Address MVECT2 0x1401 1 Yes CLA Interrupt/Task 2 Start Address MVECT3 0x1402 1 Yes CLA Interrupt/Task 3 Start Address MVECT4 0x1403 1 Yes CLA Interrupt/Task 4 Start Address MVECT5 0x1404 1 Yes CLA Interrupt/Task 5 Start Address MVECT6 0x1405 1 Yes CLA Interrupt/Task 6 Start Address MVECT7 0x1406 1 Yes CLA Interrupt/Task 7 Start Address MVECT8 0x1407 1 Yes CLA Interrupt/Task 8 Start Address DESCRIPTION (1) All registers in this table are CSM protected Submit Documentation Feedback Peripherals 45 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Table 4-1. CLA Control Registers (continued) REGISTER NAME CLA1 ADDRESS SIZE (x16) EALLOW PROTECTED MCTL 0x1410 1 Yes CLA Control Register MMEMCFG 0x1411 1 Yes CLA Memory Configure Register MPISRCSEL1 0x1414 2 Yes Peripheral Interrupt Source Select Register 1 MIFR 0x1420 1 Yes Interrupt Flag Register MIOVF 0x1421 1 Yes Interrupt Overflow Register MIFRC 0x1422 1 Yes Interrupt Force Register MICLR 0x1423 1 Yes Interrupt Clear Register MICLROVF 0x1424 1 Yes Interrupt Overflow Clear Register PRODUCT PREVIEW MIER 0x1425 1 Yes Interrupt Enable Register MIRUN 0x1426 1 Yes Interrupt RUN Register MIPCTL 0x1427 1 Yes Interrupt Priority Control Register MPC (2) 0x1428 1 – CLA Program Counter MAR0 (2) 0x142A 1 – CLA Aux Register 0 MAR1 (2) 0x142B 1 – CLA Aux Register 1 (2) MSTF 0x142E 2 – CLA STF Register MR0 (2) 0x1430 2 – CLA R0H Register MR1 (2) 0x1434 2 – CLA R1H Register MR2 (2) 0x1438 2 – CLA R2H Register (2) 0x143C 2 – CLA R3H Register MR3 (2) DESCRIPTION (1) The main C28x CPU has read only access to this register for debug purposes. The main CPU cannot perform CPU or debugger writes to this register. Table 4-2. CLA Message RAM ADDRESS RANGE SIZE (x16) EALLOW PROTECTED DESCRIPTION 0x1480 - 0x14FF 80 Yes CLA to CPU Message RAM 0x1500 - 0x157F 80 Yes CPU to CLA Message RAM 46 Peripherals Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 4.2 Analog Block A 12-bit ADC core is implemented that has different timings than the 12-bit ADC used on F280x/F2833x. The ADC wrapper is modified to incorporate the new timings and also other enhancements to improve the timing control of start of conversions. 80-Pin VDDA VDDA (3.3 V) VDDA (Agnd) VSSA VREFLO VREFLO VSSA Tied To VSSA VREFLO Interface Reference Diff VREFHI VREFHI Tied To A0 A0 A1 A2 A2 A3 A3 A4 A4 A5 A6 A6 A7 A7 B0 B0 B1 B1 B2 B2 B3 B3 B4 B4 B5 B6 B6 B7 B7 A1 B1 COMP1OUT A2 AIO2 AIO10 B2 Simultaneous Sampling Channels A1 VREFHI A0 B0 10-Bit DAC Comp1 A3 B3 PRODUCT PREVIEW 64-Pin ADC COMP2OUT A4 AIO4 AIO12 B4 10-Bit DAC Comp2 B5 Temperature Sensor A5 COMP3OUT A6 Signal Pinout AIO6 AIO14 B6 10-Bit DAC Comp3 A7 B7 Figure 4-2. Analog Pin Configurations Figure 4-3 shows the interaction of the analog module with the rest of the F2803x system. 4.2.1 ADC Table 4-3. ADC Configuration and Control Registers ADDRESS SIZE (x16) EALLOW PROTECTED ADCCTL1 0x7100 1 Yes Control 1 Register ADCINTFLG 0x7104 1 No Interrupt Flag Register ADCINTFLGCLR 0x7105 1 No Interrupt Flag Clear Register ADCINTOVF 0x7106 1 No Interrupt Overflow Register ADCINTOVFCLR 0x7107 1 No Interrupt Overflow Clear Register ADCINTSEL1AND2 0x7108 1 Yes Interrupt 1 and 2 Selection Register ADCINTSEL3AND4 0x7109 1 Yes Interrupt 3 and 4 Selection Register ADCINTSEL5AND6 0x710A 1 Yes Interrupt 5 and 6 Selection Register ADCINTSEL7AND8 0x710B 1 Yes Interrupt 7 and 8 Selection Register ADCINTSEL9AND10 0x710C 1 Yes Interrupt 9 Selection Register (reserved Interrupt 10 Selection) ADCSOCPRIORITYCTL 0x7110 1 Yes SOC Priority Control Register ADCSAMPLEMODE 0x7112 1 Yes Sampling Mode Register ADCINTSOCSEL1 0x7114 1 Yes Interrupt SOC Selection 1 Register (for 8 channels) ADCINTSOCSEL2 0x7115 1 Yes Interrupt SOC Selection 2 Register (for 8 channels) ADCSOCFLG1 0x7118 1 No SOC Flag 1 Register (for 16 channels) ADCSOCFRC1 0x711A 1 No SOC Force 1 Register (for 16 channels) REGISTER NAME Submit Documentation Feedback DESCRIPTION Peripherals 47 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Table 4-3. ADC Configuration and Control Registers (continued) ADDRESS SIZE (x16) EALLOW PROTECTED 0x711C 1 No SOC Overflow 1 Register (for 16 channels) ADCSOCOVFCLR1 0x711E 1 No SOC Overflow Clear 1 Register (for 16 channels) ADCSOC0CTL to ADCSOC15CTL 0x7120 0x712F 1 Yes SOC0 Control Register to SOC15 Control Register 0x7140 1 Yes Reference Trim Register ADCOFFTRIM 0x7141 1 Yes Offset Trim Register ADCREV 0x714F 1 No Revision Register REGISTER NAME ADCSOCOVF1 ADCREFTRIM DESCRIPTION Table 4-4. ADC Result Registers (Mapped to PF0) REGISTER NAME ADDRESS PRODUCT PREVIEW ADCRESULT0 to ADCRESULT15 0xB00 0xB0F SIZE (x16) EALLOW PROTECTED 1 No 0-Wait Result Registers DESCRIPTION ADC Result 0 Register to ADC Result 15 Register PF0 (CPU) PF2 (CPU) SYSCLKOUT ADCENCLK ADCINT 1 PIE ADCINT 9 ADCTRIG 1 ADCTRIG 2 AIO MUX ADC Channels ADC Core 12-Bit ADCTRIG 3 ADCTRIG 4 ADCTRIG 5 ADCTRIG 6 ADCTRIG 7 ADCTRIG 8 ADCTRIG 9 ADCTRIG 10 ADCTRIG 11 ADCTRIG 12 ADCTRIG 13 ADCTRIG 14 ADCTRIG 15 ADCTRIG 16 ADCTRIG 17 ADCTRIG 18 TINT 0 TINT 1 TINT 2 XINT 2SOC CPUTIMER 0 CPUTIMER 1 CPUTIMER 2 XINT 2 SOCA 1 SOCB 1 EPWM 1 SOCA 2 SOCB 2 EPWM 2 SOCA 3 SOCB 3 EPWM 3 SOCA 4 SOCB 4 EPWM 4 SOCA 5 SOCB 5 EPWM 5 SOCA 6 SOCB 6 EPWM 6 SOCA 7 SOCB 7 EPWM 7 Figure 4-3. ADC Connections 48 Peripherals Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com 4.2.2 SPRS584A – APRIL 2009 – REVISED MAY 2009 ADC MUX To COMPy A or B input To ADC Channel X Logic implemented in GPIO MUX block AIOx Pin SYSCLK AIOxIN 1 AIOxINE PRODUCT PREVIEW AIODAT Reg (Read) SYNC 0 AIOxDIR (1 = Input, 0 = Output) AIODAT Reg (Latch) AIOSET, AIOCLEAR, AIOTOGGLE Regs AIOMUX 1 Reg AIODIR Reg (Latch) 1 1 (0 = Input, 1 = Output) IORS 0 0 Figure 4-4. ADC MUX The ADC channel and Comparator functions are always available. The digital I/O function is available only when the respective bit in the AIOMUX1 register is set to 1. In this mode, reading the AIODAT register reflects the actual pin state. The digital I/O function is disabled when the respective bit in the AIOMUX1 register is cleared to 0. In this mode, reading the AIODAT register reflects the output latch of the AIODAT register and the input digital I/O buffer is disabled to prevent analog signals from generating noise. On reset, the digital function is disabled. If the pin is used as an analog input, users should keep the AIO function disabled for that pin. Submit Documentation Feedback Peripherals 49 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 4.2.3 www.ti.com Comparator Block Figure 4-5 shows the interaction of the Comparator modules with the rest of the system. COMP x A COMP x B + COMP - GPIO MUX COMP x + DAC x Wrapper AIO MUX TZ1/2/3 ePWM COMPxOUT DAC Core 10-Bit PRODUCT PREVIEW Figure 4-5. Comparator Block Diagram Table 4-5. Comparator Control Registers 50 REGISTER NAME COMP1 ADDRESS COMP2 ADDRESS COMP3 ADDRESS SIZE (x16) EALLOW PROTECTED DESCRIPTION COMPCTL 0x6400 0x6420 0x6440 1 Yes Comparator Control Register COMPSTS 0x6402 0x6422 0x6442 1 No Comparator Status Register DACVAL 0x6406 0x6426 0x6446 1 Yes DAC Value Register Peripherals Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 4.3 Serial Peripheral Interface (SPI) Module The SPI module features include: • Four external pins: – SPISOMI: SPI slave-output/master-input pin – SPISIMO: SPI slave-input/master-output pin – SPISTE: SPI slave transmit-enable pin – SPICLK: SPI serial-clock pin NOTE: All four pins can be used as GPIO if the SPI module is not used. • Two operational modes: master and slave Baud rate: 125 different programmable rates. • • • • • Baud rate = LSPCLK (SPIBRR ) 1) Baud rate = LSPCLK 4 when SPIBRR = 3 to 127 when SPIBRR = 0,1, 2 Data word length: one to sixteen data bits Four clocking schemes (controlled by clock polarity and clock phase bits) include: – Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. – Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. – Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. – Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. Simultaneous receive and transmit operation (transmit function can be disabled in software) Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms. Nine SPI module control registers: Located in control register frame beginning at address 7040h. NOTE All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7-0), and the upper byte (15-8) is read as zeros. Writing to the upper byte has no effect. Enhanced feature: • 4-level transmit/receive FIFO • Delayed transmit control • Bi-directional 3 wire SPI mode support • Audio data receive support via SPISTE inversion The SPI port operation is configured and controlled by the registers listed in Table 4-6. Submit Documentation Feedback Peripherals 51 PRODUCT PREVIEW The device includes the four-pin serial peripheral interface (SPI) module. One SPI module (SPI-A) is available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the MCU and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI. TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Table 4-6. SPI-A Registers PRODUCT PREVIEW (1) DESCRIPTION (1) NAME ADDRESS SIZE (x16) EALLOW PROTECTED SPICCR 0x7040 1 No SPI-A Configuration Control Register SPICTL 0x7041 1 No SPI-A Operation Control Register SPISTS 0x7042 1 No SPI-A Status Register SPIBRR 0x7044 1 No SPI-A Baud Rate Register SPIRXEMU 0x7046 1 No SPI-A Receive Emulation Buffer Register SPIRXBUF 0x7047 1 No SPI-A Serial Input Buffer Register SPITXBUF 0x7048 1 No SPI-A Serial Output Buffer Register SPIDAT 0x7049 1 No SPI-A Serial Data Register SPIFFTX 0x704A 1 No SPI-A FIFO Transmit Register SPIFFRX 0x704B 1 No SPI-A FIFO Receive Register SPIFFCT 0x704C 1 No SPI-A FIFO Control Register SPIPRI 0x704F 1 No SPI-A Priority Control Register Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. Table 4-7. SPI-B Registers (1) 52 DESCRIPTION (1) NAME ADDRESS SIZE (x16) EALLOW PROTECTED SPICCR 0x7740 1 No SPI-B Configuration Control Register SPICTL 0x7741 1 No SPI-B Operation Control Register SPISTS 0x7742 1 No SPI-B Status Register SPIBRR 0x7744 1 No SPI-B Baud Rate Register SPIRXEMU 0x7746 1 No SPI-B Receive Emulation Buffer Register SPIRXBUF 0x7747 1 No SPI-B Serial Input Buffer Register SPITXBUF 0x7748 1 No SPI-B Serial Output Buffer Register SPIDAT 0x7749 1 No SPI-B Serial Data Register SPIFFTX 0x774A 1 No SPI-B FIFO Transmit Register SPIFFRX 0x774B 1 No SPI-B FIFO Receive Register SPIFFCT 0x774C 1 No SPI-B FIFO Control Register SPIPRI 0x774F 1 No SPI-B Priority Control Register Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. Peripherals Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 Figure 4-6 is a block diagram of the SPI in slave mode. SPIFFENA SPIFFTX.14 Receiver Overrun Flag RX FIFO Registers SPISTS.7 Overrun INT ENA SPICTL.4 SPIRXBUF RX FIFO _0 RX FIFO _1 ----- SPIINT RX FIFO Interrupt RX FIFO _3 RX Interrupt Logic 16 SPIRXBUF Buffer Register SPIFFOVF FLAG SPIFFRX.15 To CPU SPITXBUF TX FIFO _3 SPITX 16 16 TX Interrupt Logic TX FIFO Interrupt ----TX FIFO _1 TX FIFO _0 PRODUCT PREVIEW TX FIFO Registers SPI INT ENA SPI INT FLAG SPITXBUF Buffer Register SPISTS.6 SPICTL.0 TRIWIRE SPIPRI.0 16 M M SPIDAT Data Register TW S S SPIDAT.15 - 0 SW1 SPISIMO M TW M TW SPISOMI S S STEINV SW2 SPIPRI.1 Talk STEINV SPICTL.1 SPISTE State Control Master/Slave SPI Char SPICCR.3 - 0 3 2 M SPI Bit Rate SW3 S SPIBRR.6 - 0 LSPCLK 6 A. SPICTL.2 S 0 1 5 4 3 2 1 0 Clock Polarity Clock Phase SPICCR.6 SPICTL.3 SPICLK M SPISTE is driven low by the master for a slave device. Figure 4-6. SPI Module Block Diagram (Slave Mode) Submit Documentation Feedback Peripherals 53 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 4.4 Serial Communications Interface (SCI) Module The devices include one serial communications interface (SCI) module (SCI-A). The SCI module supports digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-select register. PRODUCT PREVIEW Features of each SCI module include: • Two external pins: – SCITXD: SCI transmit-output pin – SCIRXD: SCI receive-input pin NOTE: Both pins can be used as GPIO if not used for SCI. – Baud rate programmable to 64K different rates: • • • • • • • • Baud rate = LSPCLK (BRR ) 1) * 8 when BRR ≠ 0 Baud rate = LSPCLK 16 when BRR = 0 Data-word format – One start bit – Data-word length programmable from one to eight bits – Optional even/odd/no parity bit – One or two stop bits Four error-detection flags: parity, overrun, framing, and break detection Two wake-up multiprocessor modes: idle-line and address bit Half- or full-duplex operation Double-buffered receive and transmit functions Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags. – Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY flag (transmitter-shift register is empty) – Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break condition occurred), and RX ERROR flag (monitoring four interrupt conditions) Separate enable bits for transmitter and receiver interrupts (except BRKDT) NRZ (non-return-to-zero) format NOTE All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7-0), and the upper byte (15-8) is read as zeros. Writing to the upper byte has no effect. Enhanced features: • Auto baud-detect hardware logic • 4-level transmit/receive FIFO 54 Peripherals Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 The SCI port operation is configured and controlled by the registers listed in Table 4-8. Table 4-8. SCI-A Registers (1) ADDRESS SIZE (x16) EALLOW PROTECTED SCICCRA 0x7050 1 No SCI-A Communications Control Register SCICTL1A 0x7051 1 No SCI-A Control Register 1 SCIHBAUDA 0x7052 1 No SCI-A Baud Register, High Bits SCILBAUDA 0x7053 1 No SCI-A Baud Register, Low Bits SCICTL2A 0x7054 1 No SCI-A Control Register 2 SCIRXSTA 0x7055 1 No SCI-A Receive Status Register SCIRXEMUA 0x7056 1 No SCI-A Receive Emulation Data Buffer Register SCIRXBUFA 0x7057 1 No SCI-A Receive Data Buffer Register SCITXBUFA 0x7059 1 No SCI-A Transmit Data Buffer Register SCIFFTXA (2) 0x705A 1 No SCI-A FIFO Transmit Register (2) 0x705B 1 No SCI-A FIFO Receive Register SCIFFCTA (2) 0x705C 1 No SCI-A FIFO Control Register SCIPRIA 0x705F 1 No SCI-A Priority Control Register SCIFFRXA (1) (2) DESCRIPTION PRODUCT PREVIEW NAME Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. These registers are new registers for the FIFO mode. Submit Documentation Feedback Peripherals 55 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Figure 4-7 shows the SCI module block diagram. SCICTL1.1 SCITXD Frame Format and Mode Parity Even/Odd Enable TXSHF Register TXENA 8 SCICCR.6 SCICCR.5 TX EMPTY SCICTL2.6 TXRDY TXWAKE SCICTL1.3 1 Transmitter-Data Buffer Register 8 TX INT ENA SCICTL2.7 SCICTL2.0 TX FIFO Interrupts TX FIFO _0 TX FIFO _1 TXINT TX Interrupt Logic To CPU ----- TX FIFO _3 WUT SCITXD SCI TX Interrupt select logic SCITXBUF.7-0 TX FIFO registers PRODUCT PREVIEW SCIFFENA AutoBaud Detect logic SCIFFTX.14 SCIHBAUD. 15 - 8 Baud Rate MSbyte Register SCIRXD RXSHF Register SCIRXD RXWAKE LSPCLK SCIRXST.1 SCILBAUD. 7 - 0 Baud Rate LSbyte Register RXENA 8 SCICTL1.0 SCICTL2.1 Receive Data Buffer register SCIRXBUF.7-0 RXRDY 8 BRKDT RX FIFO _3 ----- RX FIFO_1 RX FIFO _0 SCIRXBUF.7-0 RX/BK INT ENA SCIRXST.6 RX FIFO Interrupts SCIRXST.5 RX Interrupt Logic RX FIFO registers SCIRXST.7 SCIRXST.4 - 2 RX Error FE OE PE RXINT To CPU RXFFOVF SCIFFRX.15 RX Error RX ERR INT ENA SCICTL1.6 SCI RX Interrupt select logic Figure 4-7. Serial Communications Interface (SCI) Module Block Diagram 56 Peripherals Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 4.5 Local Interconnect Network (LIN) The device contains one LIN controller. The LIN standard is based on the SCI (UART) serial data link format. The LIN module can be configured to work as a SCI as well. PRODUCT PREVIEW The LIN module has the following features: • Compatible to LIN 1.3 or 2.0 protocols • Two external pins: LINRX and LINTX • Multi-buffered receive and transmit units • Identification masks for message filtering • Automatic master header generation – Programmable sync break field – Sync field – Identifier field • Slave automatic synchronization – Sync break detection – Optional baudrate update – Synchronization validation • 231 programmable transmission rates with 7 fractional bits • Wakeup on LINRX dominant level from transceiver • Automatic wakeup support – Wakeup signal generation – Expiration times on wakeup signals • Automatic bus idle detection • Error detection – Bit error – Bus error – No-response error – Checksum error – Sync field error – Parity error • 2 Interrupt lines with priority encoding for: – Receive – Transmit – ID, error and status The registers in Table 4-9 configure and control the operation of the LIN module. Submit Documentation Feedback Peripherals 57 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Table 4-9. LIN-A Registers (1) PRODUCT PREVIEW (1) 58 NAME ADDRESS SIZE (x16) SCIGCR0 0x6C00 2 Global Control Register 0 DESCRIPTION SCIGCR1 0x6C02 2 Global Control Register 1 SCIGCR2 0x6C04 2 Global Control Register 2 SCISETINT 0x6C06 2 Interrupt Enable Register SCICLEARINT 0x6C08 2 Interrupt Disable Register SCISETINTLVL 0x6C0A 2 Set Interrupt Level Register SCICLEARINTLVL 0x6C0C 2 Clear Interrupt Level Register SCIFLR 0x6C0E 2 Flag Register SCIINTVECT0 0x6C10 2 Interrupt Vector Offset Register 0 SCIINTVECT1 0x6C12 2 Interrupt Vector Offset Register 1 SCIFORMAT 0x6C14 2 Length Control register BRSR 0x6C16 2 Baud Rate Selection Register SCIED 0x6C18 2 Emulation buffer register SCIRD 0x6C1A 2 Receiver data buffer register SCITD 0x6C1C 2 Transmit data buffer register Reserved 0x6C1E 4 RSVD SIPIO2 0x6C22 2 Pin control register 2 Reserved 0x6C24 10 RSVD LINCOMP 0x6C30 2 Compare register LINRD0 0x6C32 2 Receive data register 0 LINRD1 0x6C34 2 Receive data register 1 LINMASK 0x6C36 2 Acceptance mask register LINID 0x6C38 2 Register containing ID- byte, ID-SlaveTask byte, and ID received fields. LINTD0 0x6C3A 2 Transmit Data Register 0 LINTD1 0x6C3C 2 Transmit Data Register 1 MBRSR 0x6C3E 2 Baud Rate Selection Register Reserved 0x6C40 8 RSVD IODFTCTRL 0x6C48 2 IODFT for BLIN Some registers and some bits in other registers are EALLOW-protected. See the TMS320x2803x Piccolo Local Interconnect Network (LIN) Module Reference Guide (literature number SPRUGE2) for more details. Peripherals Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 Figure 4-8 shows the LIN module block diagram. READ DATA BUS WRITE DATA BUS ADDRESS BUS CHECKSUM CALCULATOR PRODUCT PREVIEW INTERFACE ID PARTY CHECKER BIT MONITOR TXRX ERROR DETECTOR (TED) TIMEOUT CONTROL COUNTER LINRX/ SCIRX COMPARE LINTX/ SCITX FSM MASK FILTER SYNCHRONIZER 8 RECEIVE BUFFERS 8 TRANSMIT BUFFERS Figure 4-8. LIN Block Diagram Submit Documentation Feedback Peripherals 59 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 4.6 Enhanced Controller Area Network (eCAN) Module PRODUCT PREVIEW The CAN module (eCAN-A) has the following features: • Fully compliant with CAN protocol, version 2.0B • Supports data rates up to 1 Mbps • Thirty-two mailboxes, each with the following properties: – Configurable as receive or transmit – Configurable with standard or extended identifier – Has a programmable receive mask – Supports data and remote frame – Composed of 0 to 8 bytes of data – Uses a 32-bit time stamp on receive and transmit message – Protects against reception of new message – Holds the dynamically programmable priority of transmit message – Employs a programmable interrupt scheme with two interrupt levels – Employs a programmable alarm on transmission or reception time-out • Low-power mode • Programmable wake-up on bus activity • Automatic reply to a remote request message • Automatic retransmission of a frame in case of loss of arbitration or error • 32-bit local network time counter synchronized by a specific message (communication in conjunction with mailbox 16) • Self-test mode – Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided, thereby eliminating the need for another node to provide the acknowledge bit. NOTE For a SYSCLKOUT of 60 MHz, the smallest bit rate possible is 9.375 kbps. The F2803x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and exceptions. 60 Peripherals Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 eCAN0INT Controls Address eCAN1INT Data Enhanced CAN Controller 32 Message Controller Mailbox RAM (512 Bytes) 32-Message Mailbox of 4 × 32-Bit Words Memory Management Unit 32 CPU Interface, Receive Control Unit, Timer Management Unit eCAN Memory (512 Bytes) Registers and Message Objects Control 32 PRODUCT PREVIEW 32 Receive Buffer eCAN Protocol Kernel Transmit Buffer Control Buffer Status Buffer SN65HVD23x 3.3-V CAN Transceiver CAN Bus Figure 4-9. eCAN Block Diagram and Interface Circuit Table 4-10. 3.3-V eCAN Transceivers PART NUMBER SUPPLY VOLTAGE LOW-POWER MODE SLOPE CONTROL VREF OTHER TA SN65HVD230 3.3 V Standby Adjustable Yes – -40°C to 85°C SN65HVD230Q 3.3 V Standby Adjustable Yes – -40°C to 125°C SN65HVD231 3.3 V Sleep Adjustable Yes – -40°C to 85°C SN65HVD231Q 3.3 V Sleep Adjustable Yes – -40°C to 125°C SN65HVD232 3.3 V None None None – -40°C to 85°C SN65HVD232Q 3.3 V None None None – -40°C to 125°C SN65HVD233 3.3 V Standby Adjustable None Diagnostic Loopback -40°C to 125°C SN65HVD234 3.3 V Standby and Sleep Adjustable None – -40°C to 125°C SN65HVD235 3.3 V Standby Adjustable None Autobaud Loopback -40°C to 125°C Submit Documentation Feedback Peripherals 61 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com eCAN-A Control and Status Registers Mailbox Enable − CANME Mailbox Direction − CANMD Transmission Request Set − CANTRS Transmission Request Reset − CANTRR Transmission Acknowledge − CANTA eCAN-A Memory (512 Bytes) 6000h Abort Acknowledge − CANAA Received Message Pending − CANRMP Control and Status Registers Received Message Lost − CANRML 603Fh 6040h 607Fh 6080h PRODUCT PREVIEW 60BFh 60C0h 60FFh Remote Frame Pending − CANRFP Local Acceptance Masks (LAM) (32 × 32-Bit RAM) Global Acceptance Mask − CANGAM Master Control − CANMC Message Object Time Stamps (MOTS) (32 × 32-Bit RAM) Bit-Timing Configuration − CANBTC Message Object Time-Out (MOTO) (32 × 32-Bit RAM) Transmit Error Counter − CANTEC Error and Status − CANES Receive Error Counter − CANREC Global Interrupt Flag 0 − CANGIF0 Global Interrupt Mask − CANGIM Global Interrupt Flag 1 − CANGIF1 eCAN-A Memory RAM (512 Bytes) 6100h−6107h Mailbox 0 6108h−610Fh Mailbox 1 6110h−6117h Mailbox 2 6118h−611Fh Mailbox 3 6120h−6127h Mailbox 4 Mailbox Interrupt Mask − CANMIM Mailbox Interrupt Level − CANMIL Overwrite Protection Control − CANOPC TX I/O Control − CANTIOC RX I/O Control − CANRIOC Time Stamp Counter − CANTSC Time-Out Control − CANTOC Time-Out Status − CANTOS 61E0h−61E7h Mailbox 28 61E8h−61EFh Mailbox 29 61F0h−61F7h Mailbox 30 61F8h−61FFh Mailbox 31 Reserved Message Mailbox (16 Bytes) 61E8h−61E9h Message Identifier − MSGID 61EAh−61EBh Message Control − MSGCTRL 61ECh−61EDh Message Data Low − MDL 61EEh−61EFh Message Data High − MDH Figure 4-10. eCAN-A Memory Map NOTE If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for this. 62 Peripherals Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 The CAN registers listed in Table 4-11 are used by the CPU to configure and control the CAN controller and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary. Table 4-11. CAN Register Map (1) (1) ECAN-A ADDRESS SIZE (x32) DESCRIPTION CANME 0x6000 1 Mailbox enable CANMD 0x6002 1 Mailbox direction CANTRS 0x6004 1 Transmit request set CANTRR 0x6006 1 Transmit request reset CANTA 0x6008 1 Transmission acknowledge CANAA 0x600A 1 Abort acknowledge CANRMP 0x600C 1 Receive message pending CANRML 0x600E 1 Receive message lost CANRFP 0x6010 1 Remote frame pending CANGAM 0x6012 1 Global acceptance mask CANMC 0x6014 1 Master control CANBTC 0x6016 1 Bit-timing configuration CANES 0x6018 1 Error and status CANTEC 0x601A 1 Transmit error counter CANREC 0x601C 1 Receive error counter CANGIF0 0x601E 1 Global interrupt flag 0 CANGIM 0x6020 1 Global interrupt mask CANGIF1 0x6022 1 Global interrupt flag 1 CANMIM 0x6024 1 Mailbox interrupt mask CANMIL 0x6026 1 Mailbox interrupt level CANOPC 0x6028 1 Overwrite protection control CANTIOC 0x602A 1 TX I/O control CANRIOC 0x602C 1 RX I/O control CANTSC 0x602E 1 Time stamp counter (Reserved in SCC mode) CANTOC 0x6030 1 Time-out control (Reserved in SCC mode) CANTOS 0x6032 1 Time-out status (Reserved in SCC mode) PRODUCT PREVIEW REGISTER NAME These registers are mapped to Peripheral Frame 1. Submit Documentation Feedback Peripherals 63 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 4.7 Inter-Integrated Circuit (I2C) The device contains one I2C Serial Port. Figure 4-11 shows how the I2C peripheral module interfaces within the device. PRODUCT PREVIEW The I2C module has the following features: • Compliance with the Philips Semiconductors I2C-bus specification (version 2.1): – Support for 1-bit to 8-bit format transfers – 7-bit and 10-bit addressing modes – General call – START byte mode – Support for multiple master-transmitters and slave-receivers – Support for multiple slave-transmitters and master-receivers – Combined master transmit/receive and receive/transmit mode – Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate) • One 4-word receive FIFO and one 4-word transmit FIFO • One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following conditions: – Transmit-data ready – Receive-data ready – Register-access ready – No-acknowledgment received – Arbitration lost – Stop condition detected – Addressed as slave • An additional interrupt that can be used by the CPU when in FIFO mode • Module enable/disable capability • Free data format mode 64 Peripherals Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 I2C module I2CXSR I2CDXR TX FIFO FIFO Interrupt to CPU/PIE SDA RX FIFO Peripheral bus I2CDRR Clock synchronizer SCL Control/status registers CPU PRODUCT PREVIEW I2CRSR Prescaler Noise filters Interrupt to CPU/PIE I2C INT Arbitrator A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are also at the SYSCLKOUT rate. B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off. Figure 4-11. I2C Peripheral Module Interfaces The registers in Table 4-12 configure and control the I2C port operation. Table 4-12. I2C-A Registers NAME ADDRESS EALLOW PROTECTED I2COAR 0x7900 No I2C own address register I2CIER 0x7901 No I2C interrupt enable register DESCRIPTION I2CSTR 0x7902 No I2C status register I2CCLKL 0x7903 No I2C clock low-time divider register I2CCLKH 0x7904 No I2C clock high-time divider register I2CCNT 0x7905 No I2C data count register I2CDRR 0x7906 No I2C data receive register I2CSAR 0x7907 No I2C slave address register I2CDXR 0x7908 No I2C data transmit register I2CMDR 0x7909 No I2C mode register I2CISRC 0x790A No I2C interrupt source register I2CPSC 0x790C No I2C prescaler register I2CFFTX 0x7920 No I2C FIFO transmit register I2CFFRX 0x7921 No I2C FIFO receive register I2CRSR – No I2C receive shift register (not accessible to the CPU) I2CXSR – No I2C transmit shift register (not accessible to the CPU) Submit Documentation Feedback Peripherals 65 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 4.8 Enhanced PWM Modules (ePWM1/2/3/4/5/6/7) The devices contain up to seven enhanced PWM Modules (ePWM). Figure 4-12 shows a block diagram of multiple ePWM modules. Figure 4-13 shows the signal interconnections with the ePWM. See the TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module Reference Guide (literature number SPRUGE9) for more details. Table 4-13 and Table 4-14 show the complete ePWM register set per module. PRODUCT PREVIEW 66 Peripherals Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 EPWMSYNCI EPWM1SYNCI EPWM1B EPWM1TZINT EPWM1 Module EPWM1INT EPWM2TZINT PIE TZ1 to TZ3 EQEP1ERR TZ4 EPWM2INT CLOCKFAIL TZ5 EPWMxTZINT EMUSTOP TZ6 EPWMxINT (A) EPWM1ENCLK TBCLKSYNC eCAPI EPWM1SYNCO EPWM1SYNCO EPWM2SYNCI TZ1 to TZ3 EPWM2B EPWM2 Module COMP TZ4 TZ5 TZ6 EQEP1ERR (A) EPWM1A H R P W M CLOCKFAIL EMUSTOP EPWM2ENCLK TBCLKSYNC EPWM2A EPWMxA G P I O Peripheral Bus EPWM2SYNCO ADC SOCA1 SOCB1 SOCA2 SOCB2 EPWMxSYNCI SOCAx EPWMx Module SOCBx PRODUCT PREVIEW COMPOUT1 COMPOUT2 M U X EPWMxB TZ1 to TZ3 TZ4 TZ5 TZ6 EQEP1ERR (A) EQEP1ERR CLOCKFAIL EMUSTOP eQEP1 EPWMxENCLK TBCLKSYNC System Control C28x CPU A. SOCA1 SOCA2 SPCAx Pulse Stretch (32 SYSCLKOUT Cycles, Active-Low Output) ADCSOCAO SOCB1 SOCB2 SPCBx Pulse Stretch (32 SYSCLKOUT Cycles, Active-Low Output) ADCSOCBO This signal exists only on devices with an eQEP1 module. Figure 4-12. ePWM Submit Documentation Feedback Peripherals 67 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Table 4-13. ePWM1–ePWM4 Control and Status Registers ePWM1 ePWM2 ePWM3 ePWM4 SIZE (x16) / #SHADOW TBCTL 0x6800 0x6840 0x6880 0x68C0 1/0 Time Base Control Register TBSTS 0x6801 0x6841 0x6881 0x68C1 1/0 Time Base Status Register TBPHSHR 0x6802 0x6842 0x6882 0x68C2 1/0 Time Base Phase HRPWM Register TBPHS 0x6803 0x6843 0x6883 0x68C3 1/0 Time Base Phase Register TBCTR 0x6804 0x6844 0x6884 0x68C4 1/0 Time Base Counter Register TBPRD 0x6805 0x6845 0x6885 0x68C5 1/1 Time Base Period Register Set TBPRDHR 0x6806 0x6846 0x6886 0x68C6 1/1 Time Base Period High Resolution Register (1) CMPCTL 0x6807 0x6847 0x6887 0x68C7 1/0 Counter Compare Control Register CMPAHR 0x6808 0x6848 0x6888 0x68C8 1/1 Time Base Compare A HRPWM Register NAME DESCRIPTION CMPA 0x6809 0x6849 0x6889 0x68C9 1/1 Counter Compare A Register Set CMPB 0x680A 0x684A 0x688A 0x68CA 1/1 Counter Compare B Register Set AQCTLA 0x680B 0x684B 0x688B 0x68CB 1/0 Action Qualifier Control Register For Output A AQCTLB 0x680C 0x684C 0x688C 0x68CC 1/0 Action Qualifier Control Register For Output B AQSFRC 0x680D 0x684D 0x688D 0x68CD 1/0 Action Qualifier Software Force Register AQCSFRC 0x680E 0x684E 0x688E 0x68CE 1/1 Action Qualifier Continuous S/W Force Register Set DBCTL 0x680F 0x684F 0x688F 0x68CF 1/1 Dead-Band Generator Control Register DBRED 0x6810 0x6850 0x6890 0x68D0 1/0 Dead-Band Generator Rising Edge Delay Count Register DBFED 0x6811 0x6851 0x6891 0x68D1 1/0 Dead-Band Generator Falling Edge Delay Count Register TZSEL 0x6812 0x6852 0x6892 0x68D2 1/0 Trip Zone Select Register (1) TZDCSEL 0x6813 0x6853 0x6893 0x98D3 1/0 Trip Zone Digital Compare Register TZCTL 0x6814 0x6854 0x6894 0x68D4 1/0 Trip Zone Control Register (1) TZEINT 0x6815 0x6855 0x6895 0x68D5 1/0 Trip Zone Enable Interrupt Register (1) TZFLG 0x6816 0x6856 0x6896 0x68D6 1/0 Trip Zone Flag Register TZCLR 0x6817 0x6857 0x6897 0x68D7 1/0 Trip Zone Clear Register (1) TZFRC 0x6818 0x6858 0x6898 0x68D8 1/0 Trip Zone Force Register (1) ETSEL 0x6819 0x6859 0x6899 0x68D9 1/0 Event Trigger Selection Register ETPS 0x681A 0x685A 0x689A 0x68DA 1/0 Event Trigger Prescale Register ETFLG 0x681B 0x685B 0x689B 0x68DB 1/0 Event Trigger Flag Register ETCLR 0x681C 0x685C 0x689C 0x68DC 1/0 Event Trigger Clear Register ETFRC 0x681D 0x685D 0x689D 0x68DD 1/0 Event Trigger Force Register PCCTL 0x681E 0x685E 0x689E 0x68DE 1/0 PWM Chopper Control Register HRCNFG 0x6820 0x6860 0x68A0 0x68E0 1/0 HRPWM Configuration Register (1) (1) 68 (1) Registers that are EALLOW protected. Peripherals Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 ePWM1 ePWM2 ePWM3 ePWM4 SIZE (x16) / #SHADOW HRPWR 0x6821 - - - 1/0 HRPWM Power Register HRMSTEP 0x6826 - - - 1/0 HRPWM MEP Step Register HRPCTL 0x6828 0x6868 0x68A8 0x68E8 1/0 High resolution Period Control Register (1) TBPRDHRM 0x682A 0x686A 0x68AA 0x68EA 1 / W (2) (2) NAME DESCRIPTION Time Base Period HRPWM Register Mirror TBPRDM 0x682B 0x686B 0x68AB 0x68EB 1/W CMPAHRM 0x682C 0x686C 0x68AC 0x68EC 1 / W (2) Time Base Period Register Mirror Compare A HRPWM Register Mirror CMPAM 0x682D 0x686D 0x68AD 0x68ED 1 / W (2) Compare A Register Mirror DCTRIPSEL 0x6830 0x6870 0x68B0 0x68F0 1/0 Digital Compare Trip Select Register (1) (1) DCACTL 0x6831 0x6871 0x68B1 0x68F1 1/0 Digital Compare A Control Register DCBCTL 0x6832 0x6872 0x68B2 0x68F2 1/0 Digital Compare B Control Register (1) DCFCTL 0x6833 0x6873 0x68B3 0x68F3 1/0 Digital Compare Filter Control Register (1) DCCAPCT 0x6834 0x6874 0x68B4 0x68F4 1/0 Digital Compare Capture Control Register (1) DCFOFFSET 0x6835 0x6875 0x68B5 0x68F5 1/1 Digital Compare Filter Offset Register DCFOFFSETCNT 0x6836 0x6876 0x68B6 0x68F6 1/0 Digital Compare Filter Offset Counter Register DCFWINDOW 0x6837 0x6877 0x68B7 0x68F7 1/0 Digital Compare Filter Window Register DCFWINDOWCNT 0x6838 0x6878 0x68B8 0x68F8 1/0 Digital Compare Filter Window Counter Register DCCAP 0x6839 0x6879 0x68B9 0x68F9 1/1 Digital Compare Counter Capture Register (2) W = Write to shadow register Submit Documentation Feedback Peripherals 69 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Table 4-14. ePWM5–ePWM7 Control and Status Registers ePWM5 ePWM6 ePWM7 SIZE (x16) / #SHADOW TBCTL 0x6900 0x6940 0x6980 1/0 Time Base Control Register TBSTS 0x6901 0x6941 0x6981 1/0 Time Base Status Register TBPHSHR 0x6902 0x6942 0x6982 1/0 Time Base Phase HRPWM Register TBPHS 0x6903 0x6943 0x6983 1/0 Time Base Phase Register TBCTR 0x6904 0x6944 0x6984 1/0 Time Base Counter Register TBPRD 0x6905 0x6945 0x6985 1/1 Time Base Period Register Set TBPRDHR 0x6906 0x6946 0x6986 1/1 Time Base Period High Resolution Register (1) CMPCTL 0x6907 0x6947 0x6987 1/0 Counter Compare Control Register CMPAHR 0x6908 0x6948 0x6988 1/1 Time Base Compare A HRPWM Register NAME DESCRIPTION CMPA 0x6909 0x6949 0x6989 1/1 Counter Compare A Register Set CMPB 0x690A 0x694A 0x698A 1/1 Counter Compare B Register Set AQCTLA 0x690B 0x694B 0x698B 1/0 Action Qualifier Control Register For Output A AQCTLB 0x690C 0x694C 0x698C 1/0 Action Qualifier Control Register For Output B AQSFRC 0x690D 0x694D 0x698D 1/0 Action Qualifier Software Force Register AQCSFRC 0x690E 0x694E 0x698E 1/1 Action Qualifier Continuous S/W Force Register Set DBCTL 0x690F 0x694F 0x698F 1/1 Dead-Band Generator Control Register DBRED 0x6910 0x6950 0x6990 1/0 Dead-Band Generator Rising Edge Delay Count Register DBFED 0x6911 0x6951 0x6991 1/0 Dead-Band Generator Falling Edge Delay Count Register TZSEL 0x6912 0x6952 0x6992 1/0 Trip Zone Select Register (1) TZDCSEL 0x6913 0x6953 0x6993 1/0 Trip Zone Digital Compare Register TZCTL 0x6914 0x6954 0x6994 1/0 Trip Zone Control Register (1) TZEINT 0x6915 0x6955 0x6995 1/0 Trip Zone Enable Interrupt Register (1) TZFLG 0x6916 0x6956 0x6996 1/0 Trip Zone Flag Register TZCLR 0x6917 0x6957 0x6997 1/0 Trip Zone Clear Register (1) TZFRC 0x6918 0x6958 0x6998 1/0 Trip Zone Force Register (1) ETSEL 0x6919 0x6959 0x6999 1/0 Event Trigger Selection Register ETPS 0x691A 0x695A 0x699A 1/0 Event Trigger Prescale Register ETFLG 0x691B 0x695B 0x699B 1/0 Event Trigger Flag Register ETCLR 0x691C 0x695C 0x699C 1/0 Event Trigger Clear Register ETFRC 0x691D 0x695D 0x699D 1/0 Event Trigger Force Register PCCTL 0x691E 0x695E 0x699E 1/0 PWM Chopper Control Register HRCNFG 0x6920 0x6960 0x69A0 1/0 HRPWM Configuration Register (1) (1) 70 (1) Registers that are EALLOW protected. Peripherals Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 NAME HRPWR HRMSTEP ePWM5 ePWM6 ePWM7 SIZE (x16) / #SHADOW - - - 1/0 HRPWM Power Register DESCRIPTION - - - 1/0 HRPWM MEP Step Register HRPCTL 0x6928 0x6968 0x69A8 1/0 High resolution Period Control Register (1) TBPRDHRM 0x692A 0x696A 0x69AA 1 / W (2) (2) Time Base Period HRPWM Register Mirror TBPRDM 0x692B 0x696B 0x69AB 1/W CMPAHRM 0x692C 0x696C 0x69AC 1 / W (2) Time Base Period Register Mirror Compare A HRPWM Register Mirror CMPAM 0x692D 0x696D 0x69AD 1 / W (2) Compare A Register Mirror DCTRIPSEL 0x6930 0x6970 0x69B0 1/0 Digital Compare Trip Select Register (1) (1) DCACTL 0x6931 0x6971 0x69B1 1/0 Digital Compare A Control Register DCBCTL 0x6932 0x6972 0x69B2 1/0 Digital Compare B Control Register (1) DCFCTL 0x6933 0x6973 0x69B3 1/0 Digital Compare Filter Control Register (1) DCCAPCT 0x6934 0x6974 0x69B4 1/0 Digital Compare Capture Control Register (1) DCFOFFSET 0x6935 0x6975 0x69B5 1/1 Digital Compare Filter Offset Register DCFOFFSETCNT 0x6936 0x6976 0x69B6 1/0 Digital Compare Filter Offset Counter Register DCFWINDOW 0x6937 0x6977 0x69B7 1/0 Digital Compare Filter Window Register DCFWINDOWCNT 0x6938 0x6978 0x69B8 1/0 Digital Compare Filter Window Counter Register DCCAP 0x6939 0x6979 0x69B9 1/1 Digital Compare Counter Capture Register (2) W = Write to shadow register Submit Documentation Feedback Peripherals 71 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Time-Base (TB) CTR=ZERO TBPRD Shadow (24) TBPRD Active (24) Sync In/Out Select Mux CTR=CMPB TBPRDHR (8) Disabled EPWMxSYNCO 8 CTR=PRD TBCTL[SYNCOSEL] TBCTL[CNTLDE] Counter Up/Down (16 Bit) TBCTL[SWFSYNC] (Software Forced Sync) CTR=ZERO TCBNT Active (16) CTR_Dir CTR=PRD CTR=ZERO CTR=PRD or ZERO CTR=CMPA TBPHSHR (8) 16 8 PRODUCT PREVIEW TBPHS Active (24) Phase Control CTR=CMPB CTR_Dir DCAEVT1.soc DCBEVT1.soc CTR=CMPA (A) EPWMxSYNCI DCAEVT1.sync DCBEVT1.sync EPWMxINT Event Trigger and Interrupt (ET) EPWMxSOCA EPWMxSOCB EPWMxSOCA ADC (A) EPWMxSOCB Action Qualifier (AQ) CMPAHR (8) 16 HiRes PWM (HRPWM) CMPA Active (24) CMPA Shadow (24) Dead Band (DB) CTR=CMPB 16 EPWMxA EPWMA PWM Chopper (PC) Trip Zone (TZ) EPWMxB EPWMB EPWMxTZINT CMPB Active (16) TZ1 to TZ3 CMPB Shadow (16) CTR=ZERO DCAEVT1.inter DCBEVT1.inter DCAEVT2.inter DCBEVT2.inter EMUSTOP CLOCKFAIL EQEP1ERR (B) DCAEVT1.force DCAEVT2.force DCBEVT1.force DCBEVT2.force (A) (A) (A) (A) A. These events are generated by the Type 1 ePWM digital compare (DC) submodule based on the levels of the COMPxOUT and TZ signals. B. This signal exists only on devices with an eQEP1 module. Figure 4-13. ePWM Sub-Modules Showing Critical Internal Signal Interconnections 72 Peripherals Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 4.9 High-Resolution PWM (HRPWM) This module combines multiple delay lines in a single module and a simplified calibration system by using a dedicated calibration delay line. For each ePWM module there is one HR delay line. PRODUCT PREVIEW The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are: • Significantly extends the time resolution capabilities of conventionally derived digital PWM • This capability can be utilized in both single edge (duty cycle and phase-shift control) as well as dual edge control for frequency/period modulation. • Finer time granularity control or edge positioning is controlled via extensions to the Compare A and Phase registers of the ePWM module. • HRPWM capabilities, when available on a particular device, are offered only on the A signal path of an ePWM module (i.e., on the EPWMxA output). EPWMxB output has conventional PWM capabilities. NOTE At SYSCLKOUT frequencies below 50 MHz and under worst-case process, voltage, and temperature (maximum voltage and minimum temperature) conditions, the MEP step delay may decrease to a point such that the maximum of 254 MEP steps may not cover 1 full SYSCLKOUT cycle. In other words, high-resolution edge control will not be available for the full range of a SYSCLKOUT cycle. If running SFO calibration software, the SFO function will return an error code of “2” when this occurs. See the TMS320x2802x, 2803x Piccolo High-Resolution Pulse Width Modulator (HRPWM) Reference Guide (literature number SPRUGE8) for more information on this error condition. Submit Documentation Feedback Peripherals 73 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 4.10 Enhanced Capture Module (eCAP1) SYNC The device contains an enhanced capture (eCAP) module. Figure 4-14 shows a functional block diagram of a module. SYNCIn SYNCOut CTRPHS (phase register−32 bit) TSCTR (counter−32 bit) APWM mode OVF RST CTR_OVF CTR [0−31] Delta−mode PRD [0−31] CMP [0−31] PWM compare logic 32 CTR=PRD CTR [0−31] CTR=CMP PRODUCT PREVIEW 32 32 CAP1 (APRD active) APRD shadow 32 32 LD LD1 MODE SELECT PRD [0−31] Polarity select 32 CMP [0−31] CAP2 (ACMP active) 32 LD LD2 32 CAP3 (APRD shadow) LD 32 CAP4 (ACMP shadow) LD Polarity select Event qualifier ACMP shadow eCAPx Event Pre-scale Polarity select LD3 LD4 Polarity select 4 Capture events 4 CEVT[1:4] to PIE Interrupt Trigger and Flag control CTR_OVF Continuous / Oneshot Capture Control CTR=PRD CTR=CMP Figure 4-14. eCAP Functional Block Diagram The eCAP module is clocked at the SYSCLKOUT rate. The clock enable bits (ECAP1 ENCLK) in the PCLKCR1 register turn off the eCAP module individually (for low power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off. 74 Peripherals Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 Table 4-15. eCAP Control and Status Registers eCAP1 SIZE (x16) 0x6A00 2 EALLOW PROTECTED Time-Stamp Counter DESCRIPTION CTRPHS 0x6A02 2 Counter Phase Offset Value Register CAP1 0x6A04 2 Capture 1 Register CAP2 0x6A06 2 Capture 2 Register CAP3 0x6A08 2 Capture 3 Register CAP4 0x6A0A 2 Capture 4 Register Reserved 0x6A0C- 0x6A12 8 Reserved ECCTL1 0x6A14 1 Capture Control Register 1 ECCTL2 0x6A15 1 Capture Control Register 2 ECEINT 0x6A16 1 Capture Interrupt Enable Register ECFLG 0x6A17 1 Capture Interrupt Flag Register ECCLR 0x6A18 1 Capture Interrupt Clear Register ECFRC 0x6A19 1 Capture Interrupt Force Register Reserved 0x6A1A- 0x6A1F 6 Reserved Submit Documentation Feedback PRODUCT PREVIEW NAME TSCTR Peripherals 75 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 4.11 Enhanced Quadrature Encoder Pulse (eQEP) The device contains one enhanced quadrature encoder pulse (eQEP) module. Table 4-16. eQEP Control and Status Registers eQEP1 ADDRESS eQEP1 SIZE(x16)/ #SHADOW QPOSCNT 0x6B00 2/0 eQEP Position Counter QPOSINIT 0x6B02 2/0 eQEP Initialization Position Count QPOSMAX 0x6B04 2/0 eQEP Maximum Position Count QPOSCMP 0x6B06 2/1 eQEP Position-compare QPOSILAT 0x6B08 2/0 eQEP Index Position Latch QPOSSLAT 0x6B0A 2/0 eQEP Strobe Position Latch QPOSLAT 0x6B0C 2/0 eQEP Position Latch QUTMR 0x6B0E 2/0 eQEP Unit Timer QUPRD 0x6B10 2/0 eQEP Unit Period Register QWDTMR 0x6B12 1/0 eQEP Watchdog Timer QWDPRD 0x6B13 1/0 eQEP Watchdog Period Register QDECCTL 0x6B14 1/0 eQEP Decoder Control Register QEPCTL 0x6B15 1/0 eQEP Control Register QCAPCTL 0x6B16 1/0 eQEP Capture Control Register QPOSCTL 0x6B17 1/0 eQEP Position-compare Control Register QEINT 0x6B18 1/0 eQEP Interrupt Enable Register QFLG 0x6B19 1/0 eQEP Interrupt Flag Register QCLR 0x6B1A 1/0 eQEP Interrupt Clear Register QFRC 0x6B1B 1/0 eQEP Interrupt Force Register QEPSTS 0x6B1C 1/0 eQEP Status Register QCTMR 0x6B1D 1/0 eQEP Capture Timer QCPRD 0x6B1E 1/0 eQEP Capture Period Register QCTMRLAT 0x6B1F 1/0 eQEP Capture Timer Latch QCPRDLAT 0x6B20 1/0 eQEP Capture Period Latch Reserved 0x6B210x6B3F 31/0 NAME PRODUCT PREVIEW 76 Peripherals REGISTER DESCRIPTION Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 Figure 4-15 shows the eQEP functional block diagram. System control registers To CPU EQEPxENCLK Data bus SYSCLKOUT QCPRD QCTMR QCAPCTL 16 16 Quadrature capture unit (QCAP) QCTMRLAT QCPRDLAT Registers used by multiple units QUTMR QWDTMR QUPRD QWDPRD 32 16 QEPCTL QEPSTS UTIME QFLG UTOUT QWDOG QDECCTL 16 WDTOUT PIE EQEPxAIN QCLK EQEPxINT 16 QI Position counter/ control unit (PCCU) QPOSLAT QS PHE QPOSSLAT EQEPxIIN Quadrature decoder (QDU) PCSOUT QPOSILAT EQEPxIOUT EQEPxIOE EQEPxSIN EQEPxSOUT EQEPxSOE 32 32 QPOSCNT QPOSINIT QPOSMAX QPOSCMP EQEPxA/XCLK EQEPxBIN QDIR EQEPxB/XDIR GPIO MUX EQEPxI EQEPxS 16 QEINT QFRC QCLR QPOSCTL Enhanced QEP (eQEP) peripheral Figure 4-15. eQEP Functional Block Diagram Submit Documentation Feedback Peripherals 77 PRODUCT PREVIEW 16 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 4.12 JTAG Port On the 2803x device, the JTAG port is reduced to 5 pins (TRST, TCK, TDI, TMS, TDO). TCK, TDI, TMS and TDO pins are also GPIO pins. The TRST signal selects either JTAG or GPIO operating mode for the pins in Figure 4-16. During emulation/debug, the GPIO function of these pins are not available. If the GPIO38/TCK/XCLKIN pin is used to provide an external clock, an alternate clock source should be used to clock the device during emulation/debug since this pin will be needed for the TCK function. NOTE In 2803x devices, the JTAG pins may also be used as GPIO pins. Care should be taken in the board design to ensure that the circuitry connected to these pins do not affect the emulation capabilities of the JTAG pin function. Any circuitry connected to these pins should not prevent the emulator from driving (or being driven by) the JTAG pins for successful debug. PRODUCT PREVIEW TRST = 0: JTAG Disabled (GPIO Mode) TRST = 1: JTAG Mode TRST TRST XCLKIN GPIO38_in TCK TCK/GPIO38 GPIO38_out C28x Core GPIO37_in TDO/GPIO37 1 0 TDO GPIO37_out GPIO36_in 1 TMS/GPIO36 GPIO36_out 1 TMS 0 GPIO35_in 1 TDI/GPIO35 GPIO35_out 1 TDI 0 Figure 4-16. JTAG/GPIO Multiplexing 78 Peripherals Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 4.13 GPIO MUX The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to providing individual pin bit-banging I/O capability. The device supports 22 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 4-17 shows the GPIO register mapping. Table 4-17. GPIO Registers NAME ADDRESS SIZE (x16) DESCRIPTION GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0 to 31) GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0 to 15) GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16-31) GPAMUX1 0x6F86 2 GPIO A MUX 1 Register (GPIO0 to 15) GPAMUX2 0x6F88 2 GPIO A MUX 2 Register (GPIO16 to 31) GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0 to 31) GPAPUD 0x6F8C 2 GPIO A Pull Up Disable Register (GPIO0 to 31) GPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32 to 44) GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32 to 44) GPBMUX1 0x6F96 2 GPIO B MUX 1 Register (GPIO32 to 44) GPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32 to 44) GPBPUD 0x6F9C 2 GPIO B Pull Up Disable Register (GPIO32 to 44) AIOMUX1 0x6FB6 2 Analog, I/O mux 1 register (AIO0 - AIO15) AIODIR 0x6FBA 2 Analog, I/O Direction Register (AIO0-AIO15) GPADAT 0x6FC0 2 GPIO A Data Register (GPIO0 to 31) GPASET 0x6FC2 2 GPIO A Data Set Register (GPIO0 to 31) GPACLEAR 0x6FC4 2 GPIO A Data Clear Register (GPIO0 to 31) GPATOGGLE 0x6FC6 2 GPIO A Data Toggle Register (GPIO0 to 31) GPBDAT 0x6FC8 2 GPIO B Data Register (GPIO32 to 44) GPBSET 0x6FCA 2 GPIO B Data Set Register (GPIO32 to 44) PRODUCT PREVIEW GPIO CONTROL REGISTERS (EALLOW PROTECTED) GPIO DATA REGISTERS (NOT EALLOW PROTECTED) GPBCLEAR 0x6FCC 2 GPIO B Data Clear Register (GPIO32 to 44) GPBTOGGLE 0x6FCE 2 GPIO B Data Toggle Register (GPIO32 to 44) AIODAT 0x6FD8 2 Analog I/O Data Register (AIO0 - AIO15) AIOSET 0x6FDA 2 Analog I/O Data Set Register (AIO0 - AIO15) AIOCLEAR 0x6FDC 2 Analog I/O Data Clear Register (AIO0 - AIO15) AIOTOGGLE 0x6FDE 2 Analog I/O Data Toggle Register (AIO0 - AIO15) GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED) GPIOXINT1SEL 0x6FE0 1 XINT1 GPIO Input Select Register (GPIO0 to 31) GPIOXINT2SEL 0x6FE1 1 XINT2 GPIO Input Select Register (GPIO0 to 31) GPIOXINT3SEL 0x6FE2 1 XINT3 GPIO Input Select Register (GPIO0 to 31) GPIOLPMSEL 0x6FE8 2 LPM GPIO Select Register (GPIO0 to 31) NOTE There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn/AIOMUXn and GPxQSELn registers occurs to when the action is valid. Submit Documentation Feedback Peripherals 79 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Table 4-18. GPIOA MUX (1) DEFAULT AT RESET PRIMARY I/O FUNCTION PERIPHERAL SELECTION 1 PERIPHERAL SELECTION 2 PERIPHERAL SELECTION 3 GPAMUX1 REGISTER BITS (GPAMUX1 BITS = 00) (GPAMUX1 BITS = 01) (GPAMUX1 BITS = 10) (GPAMUX1 bits = 11) 1-0 GPIO0 EPWM1A (O) Reserved Reserved 3-2 GPIO1 EPWM1B (O) Reserved COMP1OUT (O) 5-4 GPIO2 EPWM2A (O) Reserved Reserved 7-6 GPIO3 EPWM2B (O) SPISOMIA (I/O) COMP2OUT (O) PRODUCT PREVIEW 9-8 GPIO4 EPWM3A (O) Reserved Reserved 11-10 GPIO5 EPWM3B (O) SPISIMOA (I/O) ECAP1 (I/O) 13-12 GPIO6 EPWM4A (O) EPWMSYNCI (I) EPWMSYNCO (O) 15-14 GPIO7 EPWM4B (O) SCIRXDA (I) Reserved 17-16 GPIO8 EPWM5A (O) Reserved ADCSOCAO (O) 19-18 GPIO9 EPWM5B (O) LINTXA (O) Reserved 21-20 GPIO10 EPWM6A (O) Reserved ADCSOCBO (O) 23-22 GPIO11 EPWM6B (O) LINRXA (I) Reserved 25-24 GPIO12 TZ1 (I) SCITXDA (O) SPISIMOB (I/O) 27-26 GPIO13 (2) TZ2 (I) Reserved SPISOMIB (I/O) 29-28 GPIO14 (2) TZ3 (I) LINTXA (O) SPICLKB (I/O) 31-30 GPIO15 (2) TZ1 (I) LINRXA (I) SPISTEB (I/O) GPAMUX2 REGISTER BITS (GPAMUX2 BITS = 00) (GPAMUX2 BITS = 01) (GPAMUX2 BITS = 10) (GPAMUX2 BITS = 11) 1-0 GPIO16 SPISIMOA (I/O) Reserved TZ2 (I) 3-2 GPIO17 SPISOMIA (I/O) Reserved TZ3 (I) 5-4 GPIO18 SPICLKA (I/O) LINTXA (O) XCLKOUT (O) 7-6 GPIO19/XCLKIN SPISTEA (I/O) LINRXA (I) ECAP1 (I/O) 9-8 GPIO20 EQEP1A (I) Reserved COMP1OUT (O) 11-10 GPIO21 EQEP1B (I) Reserved COMP2OUT (O) 13-12 GPIO22 EQEP1S (I/O) Reserved LINTXA (O) 15-14 GPIO23 EQEP1I (I/O) Reserved LINRXA (I) 17-16 GPIO24 ECAP1 (I/O) Reserved SPISIMOB (I/O) 19-18 GPIO25 (2) Reserved Reserved SPISOMIB (I/O) 21-20 GPIO26 (2) Reserved Reserved SPICLKB (I/O) 23-22 GPIO27 (2) Reserved Reserved SPISTEB (I/O) 25-24 GPIO28 SCIRXDA (I) SDAA (I/OC) TZ2 (I) 27-26 GPIO29 SCITXDA (O) SCLA (I/OC) TZ3 (I) 29-28 GPIO30 CANRXA (I) Reserved Reserved 31-30 GPIO31 CANTXA (O) Reserved Reserved (1) (2) 80 The word reserved means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion. These pins are not available in the 64-pin package. Peripherals Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 Table 4-19. GPIOB MUX PERIPHERAL SELECTION 1 PERIPHERAL SELECTION 2 PERIPHERAL SELECTION 3 GPBMUX1 REGISTER BITS (GPBMUX1 BITS = 00) (GPBMUX1 BITS = 01) (GPBMUX1 BITS = 10) (GPBMUX1 BITS = 11) 1-0 GPIO32 SDAA (I/OC) EPWMSYNCI (I) ADCSOCAO (O) 3-2 GPIO33 SCLA (I/OC) EPWMSYNCO (O) ADCSOCBO (O) 5-4 GPIO34 COMP2OUT (O) Reserved COMP3OUT (O) 7-6 GPIO35 (TDI) Reserved Reserved Reserved 9-8 GPIO36 (TMS) Reserved Reserved Reserved 11-10 GPIO37 (TDO) Reserved Reserved Reserved 13-12 GPIO38/XCLKIN (TCK) Reserved Reserved Reserved 15-14 GPIO39 (1) Reserved Reserved Reserved 17-16 GPIO40 (1) EPWM7A (O) Reserved Reserved 19-18 GPIO41 (1) EPWM7B (O) Reserved Reserved 21-20 GPIO42 (1) Reserved Reserved COMP1OUT (O) 23-22 GPIO43 (1) Reserved Reserved COMP2OUT (O) 25-24 GPIO44 (1) Reserved Reserved Reserved 27-26 Reserved Reserved Reserved Reserved 29-28 Reserved Reserved Reserved Reserved 31-30 Reserved Reserved Reserved Reserved (1) PRODUCT PREVIEW DEFAULT AT RESET PRIMARY I/O FUNCTION These pins are not available in the 64-pin package. Table 4-20. Analog MUX DEFAULT AT RESET (1) AIOx AND PERIPHERAL SELECTION 1 PERIPHERAL SELECTION 2 AND PERIPHERAL SELECTION 3 AIOMUX1 REGISTER BITS AIOMUX1 BITS = 0,x AIOMUX1 BITS = 1,x 1-0 ADCINA0 (I) ADCINA0 (I) 3-2 ADCINA1 (I) ADCINA1 (I) 5-4 AIO2 (I/O) ADCINA2 (I), COMP1A (I) 7-6 ADCINA3 (I) ADCINA3 (I) 9-8 AIO4 (I/O) ADCINA4 (I), COMP2A (I) 11-10 ADCINA5 (1) (I) ADCINA5 (I) 13-12 AIO6 (I/O) ADCINA6 (I) 15-14 ADCINA7 (I) ADCINA7 (I) 17-16 ADCINB0 (I) ADCINB0 (I) 19-18 ADCINB1 (I) ADCINB1 (I) 21-20 AIO10 (I/O) ADCINB2 (I), COMP1B (I) 23-22 ADCINB3 (I) ADCINB3 (I) 25-24 AIO12 (I/O) ADCINB4 (I), COMP2B (I) 27-26 ADCINB5 (1) (I) ADCINB5 (I) 29-28 AIO14 (I/O) ADCINB6 (I) 31-30 ADCINB7 (I) ADCINB7 (I) These pins are not available in the 64-pin package. Submit Documentation Feedback Peripherals 81 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from four choices: • Synchronization To SYSCLKOUT Only (GPxQSEL1/2=0, 0): This is the default mode of all GPIO pins at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT). • Qualification Using Sampling Window (GPxQSEL1/2=0, 1 and 1, 0): In this mode the input signal, after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the input is allowed to change. • The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL samples are the same (all 0s or all 1s) as shown in Figure 4-18 (for 6 sample mode). • No Synchronization (GPxQSEL1/2=1,1): This mode is used for peripherals where synchronization is not required (synchronization is performed within the peripheral). PRODUCT PREVIEW Due to the multi-level multiplexing that is required on the device, there may be cases where a peripheral input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will default to either a 0 or 1 state, depending on the peripheral. 82 Peripherals Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 GPIOXINT1SEL GPIOLMPSEL GPIOXINT2SEL LPMCR0 GPIOXINT3SEL External Interrupt MUX Low P ower Modes Block Asynchronous path PIE GPxDAT (read) GPxPUD Input Qualification Internal Pullup 00 N/C 01 Peripheral 1 Input 10 Peripheral 2 Input 11 Peripheral 3 Input PRODUCT PREVIEW GPxQSEL1/2 GPxCTRL GPxTOGGLE Asynchronous path GPIOx pin GPxCLEAR GPxSET 00 01 GPxDAT (latch) Peripheral 1 Output 10 Peripheral 2 Output 11 Peripheral 3 Output High Impedance Output Control 00 0 = Input, 1 = Output XRS GPxDIR (latch) 01 Peripheral 1 Output Enable 10 Peripheral 2 Output Enable 11 Peripheral 3 Output Enable = Default at Reset GPxMUX1/2 Figure 4-17. GPIO Multiplexing Submit Documentation Feedback Peripherals 83 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 5 Device Support Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of MCUs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of 2803x-based applications: PRODUCT PREVIEW Software Development Tools • Code Composer Studio™ Integrated Development Environment (IDE) – C/C++ Compiler – Code generation tools – Assembler/Linker – Cycle Accurate Simulator • Application algorithms • Sample applications code Hardware Development Tools • Development and evaluation boards • JTAG-based emulators - XDS510™ Class, XDS100 • Flash programming tools • Power supply • Documentation and cables 5.1 Device and Development Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320™ MCU devices and support tools. Each TMS320™ MCU commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMX320F28032). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing TMDS Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. 84 Device Support Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, PN) and temperature range (for example, T). Figure 5-1 provides a legend for reading the complete device name for any family member. TMS 320 F 28032 PN T PREFIX TMX = experimental device TMP = prototype device TMS = qualified device TEMPERATURE RANGE T = −40°C to 105°C S = −40°C to 125°C TECHNOLOGY F = Flash PACKAGE TYPE 80-Pin PN Plastic Quad Flatpack 64-Pin PAG Plastic Small-outline Package PRODUCT PREVIEW DEVICE FAMILY 320 = TMS320 MCU Family DEVICE 28035 28034 28033 28032 Figure 5-1. Device Nomenclature Submit Documentation Feedback Device Support 85 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 5.2 Related Documentation Extensive documentation supports all of the TMS320™ MCU family generations of devices from product announcement through applications development. The types of documentation available include: data sheets and data manuals, with design specifications; and hardware and software applications. Table 5-1 shows the peripheral reference guides appropriate for use with the devices in this data manual. See the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) for more information on types of peripherals. Table 5-1. TMS320F2803x Peripheral Selection Guide PERIPHERAL TMS320x2803x Piccolo System Control and Interrupts LIT. NO. TYPE (1) 28032, 28033, 28034, 28035 SPRUGL8 – X (2) PRODUCT PREVIEW TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and Comparator SPRUGE5 3/0 TMS320x2802x, 2803x Piccolo Serial Communications Interface (SCI) SPRUGH1 0 X TMS320x2802x, 2803x Piccolo Serial Peripheral Interface (SPI) SPRUG71 1 X TMS320x2803x Piccolo Boot ROM SPRUGO0 – X TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module SPRUGE9 1 X TMS320x2802x, 2803x Piccolo Enhanced Capture (eCAP) Module SPRUFZ8 0 X TMS320x2802x, 2803x Piccolo Inter-Integrated Circuit (I2C) SPRUFZ9 0 X TMS320x2802x, 2803x Piccolo High-Resolution Pulse-Width Modulator (HRPWM) SPRUGE8 1 X TMS320x2803x Piccolo Control Law Accelerator (CLA) SPRUGE6 0 X TMS320x2803x Piccolo Local Interconnect Network (LIN) Module SPRUGE2 0 X TMS320x2803x Piccolo Enhanced Quadrature Encoder Pulse (eQEP) SPRUFK8 0 X TMS320x2803x Piccolo Enhanced Controller Area Network (eCAN) SPRUGL7 0 X (1) (2) X A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the peripheral reference guides. The ADC module is Type 3 and the comparator module is Type 0. The following documents can be downloaded from the TI website (www.ti.com): Data Manual SPRS584 TMS320F28032, TMS320F28033, TMS320F28034, TMS320F28035 Piccolo Microcontrollers Data Manual contains the pinout, signal descriptions, as well as electrical and timing specifications for the 2803x devices. SPRZ295 TMS320F28032, TMS320F28033, TMS320F28034, TMS320F28035 Piccolo MCU Silicon Errata describes known advisories on silicon and provides workarounds. CPU User's Guides SPRU430 TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). It also describes emulation features available on these DSPs. Peripheral Guides SPRUGL8 TMS320x2803x Piccolo System Control and Interrupts Reference Guide describes the various interrupts and system control features of the 2803x microcontrollers (MCUs). 86 SPRU566 TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral reference guides of the 28x digital signal processors (DSPs). SPRUGO0 TMS320x2803x Piccolo Boot ROM Reference Guide describes the purpose and features of the boot loader (factory-programmed boot-loading software) and provides examples of code. It also describes other contents of the device on-chip boot ROM and identifies where all of the information is located within that memory. Device Support Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 SPRUGE5 TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and Comparator Reference Guide describes how to configure and use the on-chip ADC module, which is a 12-bit pipelined ADC. SPRUGE9 TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module Reference Guide describes the main areas of the enhanced pulse width modulator that include digital motor control, switch mode power supply control, UPS (uninterruptible power supplies), and other forms of power conversion. SPRUGE8 TMS320x2802x, 2803x Piccolo High-Resolution Pulse Width Modulator (HRPWM) describes the operation of the high-resolution extension to the pulse width modulator (HRPWM). SPRUGH1 TMS320x2802x, 2803x Piccolo Serial Communications Interface (SCI) Reference Guide describes how to use the SCI. SPRUFZ8 TMS320x2802x, 2803x Piccolo Enhanced Capture (eCAP) Module Reference Guide describes the enhanced capture module. It includes the module description and registers. SPRUG71 TMS320x2802x, 2803x Piccolo Serial Peripheral Interface (SPI) Reference Guide describes the SPI - a high-speed synchronous serial input/output (I/O) port - that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed bit-transfer rate. SPRUFZ9 TMS320x2802x, 2803x Piccolo Inter-Integrated Circuit (I2C) Reference Guide describes the features and operation of the inter-integrated circuit (I2C) module. SPRUGE6 TMS320x2803x Piccolo Control Law Accelerator (CLA) Reference Guide describes the operation of the Control Law Accelerator (CLA). SPRUGE2 TMS320x2803x Piccolo Local Interconnect Network (LIN) Module Reference Guide describes the operation of the Local Interconnect Network (LIN) Module. SPRUFK8 TMS320x2803x Piccolo Enhanced Quadrature Encoder Pulse (eQEP) Reference Guide describes the operation of the Enhanced Quadrature Encoder Pulse (eQEP) . SPRUGL7 TMS320x2803x Piccolo Enhanced Controller Area Network (eCAN) Reference Guide describes the operation of the Enhanced Controller Area Network (eCAN). Tools Guides SPRU513 TMS320C28x Assembly Language Tools v5.0.0 User's Guide describes the assembly language tools (assembler and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x device. SPRU514 TMS320C28x Optimizing C/C++ Compiler v5.0.0 User's Guide describes the TMS320C28x™ C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly language source code for the TMS320C28x device. SPRU608 TMS320C28x Instruction Set Simulator Technical Overview describes the simulator, available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instruction set of the C28x™ core. Submit Documentation Feedback Device Support 87 PRODUCT PREVIEW www.ti.com TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 6 Electrical Specifications 6.1 Absolute Maximum Ratings (1) (2) Supply voltage range, VDDIO (I/O and Flash) with respect to VSS –0.3 V to 4.6 V Supply voltage range, VDD with respect to VSS –0.3 V to 2.5 V Analog voltage range, VDDA with respect to VSSA –0.3 V to 4.6 V Input voltage range, VIN (3.3 V) –0.3 V to 4.6 V Output voltage range, VO –0.3 V to 4.0 V Input clamp current, IIK (VIN < 0 or VIN > VDDIO) (3) ±20 mA Output clamp current, IOK (VO < 0 or VO > VDDIO) ±20 mA Junction temperature range, TJ (4) –40°C to 150°C Storage temperature range, Tstg (4) PRODUCT PREVIEW (1) (2) (3) (4) –65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS, unless otherwise noted. Continuous clamp current per pin is ± 2 mA. Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device life. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for TMS320LF24xx and TMS320F28xx Devices Application Report (literature number SPRA963). 6.2 Recommended Operating Conditions MIN NOM MAX UNIT Device supply voltage, I/O, VDDIO 2.97 3.3 3.63 V Device supply voltage CPU, VDD (When internal VREG is disabled and 1.8 V is supplied externally) 1.71 1.8 1.995 2.97 3.3 Supply ground, VSS 0 Analog supply voltage, VDDA Analog ground, VSSA V 3.63 0 2 60 High-level input voltage, VIH(3.3 V) 2 VDDIO Low-level input voltage, VIL (3.3 V) Low-level output sink current, VOL = VOL(MAX), IOL Junction temperature, TJ (2) (1) (2) 88 V V Device clock frequency (system clock) High-level output source current, VOH = VOH(MIN) , IOH V 0.8 MHz V V All GPIO pins –4 mA Group 2 (1) –8 mA All GPIO pins 4 mA Group 2 (1) 8 mA T version –40 105 S version –40 125 °C Group 2 pins are as follows: GPIO16, GPIO17, GPIO18, GPIO19, GPIO28, GPIO29, GPIO36, GPIO37 TA (Ambient temperature) is product- and application-dependent and can go up to the specified TJ max of the device. Electrical Specifications Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 6.3 Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER High-level output voltage VOL Low-level output voltage IIL Input current (low level) Input current (high level) IIH MIN IOH = IOHMAX TYP MAX 2.4 IOH = 50 µA V VDDIO – 0.2 IOL = IOLMAX 0.4 Pin with pullup enabled VDDIO = 3.3 V, VIN = 0 V Pin with pulldown enabled VDDIO = 3.3 V, VIN = 0 V ±2 Pin with pullup enabled VDDIO = 3.3 V, VIN = VDDIO ±2 Pin with pulldown enabled VDDIO = 3.3 V, VIN = VDDIO IOZ Output current, pullup or pulldown disabled CI Input capacitance UNIT All I/Os (including XRS) V –100 µA µA 100 ±2 VO = VDDIO or 0 V PRODUCT PREVIEW VOH TEST CONDITIONS µA 2 pF 6.4 Current Consumption Table 6-1. TMS320F2803x Current Consumption at 60-MHz SYSCLKOUT VREG ENABLED MODE TEST CONDITIONS IDDIO TYP (3) VREG DISABLED IDDA MAX TYP (3) IDDIO (1) IDD MAX TYP (3) MAX TYP (3) MAX IDDA (2) TYP Operational (Flash) The following peripheral clocks are enabled: • ePWM1/2/3/4/5/6/7 • eCAP1 • eQEP1 • SCI-A • SPI-A/B • ADC • I2C • COMP1/2/3 • CPU-TIMER0/1/2 All PWM pins are toggled at 60 kHz. All I/O pins are left unconnected. (4) (5) Code is running out of flash with 2 wait-states. XCLKOUT is turned off. 95 mA 13 mA 83 mA 15 mA 13 mA IDLE Flash is powered down. XCLKOUT is turned off. All peripheral clocks are turned off. 20 mA 100 µA 20 mA 200 µA 100 µA STANDBY Flash is powered down. Peripheral clocks are off. 5 mA 25 µA 4 mA 200 µA 25 µA (1) (2) (3) (4) (5) MAX IDDIO current is dependent on the electrical loading on the I/O pins. In order to realize the IDDA currents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register. The TYP numbers are applicable over room temperature and nominal voltage. The following is done in a loop: • Data is continuously transmitted out of SPI-A and SCI-A ports. • The hardware multiplier is exercised. • Watchdog is reset. • ADC is performing coninuous conversion. • COMP1/2 are continuously switching voltages. • GPIO17 is toggled. If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator. Submit Documentation Feedback Electrical Specifications 89 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Table 6-1. TMS320F2803x Current Consumption at 60-MHz SYSCLKOUT (continued) VREG ENABLED MODE TEST CONDITIONS IDDIO TYP HALT Flash is powered down. Peripheral clocks are off. Input clock is disabled. (3) 100 µA VREG DISABLED IDDA MAX TYP (3) 25 µA IDDIO (1) IDD MAX TYP (3) 50 µA MAX TYP (3) 50 µA MAX IDDA (2) TYP MAX 25 µA NOTE The peripheral - I/O multiplexing implemented in the device prevents all available peripherals from being used at the same time. This is because more than one peripheral function may share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a configuration is not useful. If this is done, the current drawn by the device will be more than the numbers specified in the current consumption tables. PRODUCT PREVIEW 90 Electrical Specifications Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com 6.4.1 SPRS584A – APRIL 2009 – REVISED MAY 2009 Reducing Current Consumption The 2803x devices incorporate a method to reduce the device current consumption. Since each peripheral unit has an individual clock-enable bit, significant reduction in current consumption can be achieved by turning off the clock to any peripheral module that is not used in a given application. Furthermore, any one of the three low-power modes could be taken advantage of to reduce the current consumption even further. Table 6-2 indicates the typical reduction in current consumption achieved by turning off the clocks. (1) (2) (3) PERIPHERAL MODULE (2) IDD CURRENT REDUCTION (mA) ADC 2 (3) I2C 3 ePWM 2 eCAP 2 eQEP 2 SCI 2 SPI 2 COMP/DAC 1 HRPWM 3 CPU-TIMER 1 Internal zero-pin oscillator 0.5 CAN 2.5 LIN 1.5 CLA 20 PRODUCT PREVIEW Table 6-2. Typical Current Consumption by Various Peripherals (at 60 MHz) (1) All peripheral clocks are disabled upon reset. Writing to/reading from peripheral registers is possible only after the peripheral clocks are turned on. For peripherals with multiple instances, the current quoted is per module. For example, the 2 mA value quoted for ePWM is for one ePWM module. This number represents the current drawn by the digital portion of the ADC module. Turning off the clock to the ADC module results in the elimination of the current drawn by the analog portion of the ADC (IDDA) as well. NOTE IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off. NOTE The baseline IDD current (current when the core is executing a dummy loop with no peripherals enabled) is 45 mA, typical. To arrive at the IDD current for a given application, the current-drawn by the peripherals (enabled by that application) must be added to the baseline IDD current. Following are other methods to reduce power consumption further: • The flash module may be powered down if code is run off SARAM. This results in a current reduction of 18 mA (typical) in the VDD rail and 13 mA (typical) in the VDDIO rail. • Savings in IDDIO may be realized by disabling the pullups on pins that assume an output function. Submit Documentation Feedback Electrical Specifications 91 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 6.4.2 www.ti.com Current Consumption Graphs (VREG Enabled) Operational Current vs Frequency 100 PRODUCT PREVIEW Operational Current (mA) 90 80 70 60 50 40 30 20 10 0 10 15 20 25 30 35 40 45 50 55 60 SYSCLKOUT (MHz) IDDIO (m A) IDDA Figure 6-1. Typical Operational Current Versus Frequency (F2802x) Operational Pow er vs Frequency Operational Power (mW) 450 400 350 300 250 200 10 15 20 25 30 35 40 45 50 55 60 SYSCLKOUT (MHz) Figure 6-2. Typical Operational Power Versus Frequency (F2802x) 92 Electrical Specifications Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 6.5 Thermal Design Considerations Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that exceed the recommended maximum power dissipation in the end product may require additional thermal enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal application reports IC Package Thermal Metrics (literature number SPRA953) and Reliability Data for TMS320LF24xx and TMS320F28xx Devices (literature number SPRA963) help to understand the thermal metrics and definitions. Figure 6-3 shows the connection between the MCU and JTAG header for a single-processor configuration. If the distance between the JTAG header and the MCU is greater than 6 inches, the emulation signals must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 6-3 shows the simpler, no-buffering situation. For the pullup/pulldown resistor values, see the pin description section. 6 inches or less VDDIO VDDIO 13 14 TRST TMS TDI TDO TCK 2 1 3 7 11 9 PD EMU0 EMU1 TRST GND TMS GND TDI GND TDO GND TCK GND 5 4 6 8 10 12 TCK_RET MCU JTAG Header A. See Figure 4-16 for JTAG/GPIO multiplexing. Figure 6-3. Emulator Connection Without Signal Buffering for the MCU NOTE The 2802x devices do not have EMU0/EMU1 pins. For designs that have a JTAG Header on-board, the EMU0/EMU1 pins on the header must be tied to VDDIO through a 4.7 kΩ (typical) resistor. Submit Documentation Feedback Electrical Specifications 93 PRODUCT PREVIEW 6.6 Emulator Connection Without Signal Buffering for the MCU TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 6.7 Timing Parameter Symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: PRODUCT PREVIEW 6.7.1 Lowercase subscripts and their meanings: Letters and symbols and their meanings: a access time H High c cycle time (period) L Low d delay time V Valid f fall time X Unknown, changing, or don't care level h hold time Z High impedance r rise time su setup time t transition time v valid time w pulse duration (width) General Notes on Timing Parameters All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, see the appropriate cycle description section of this document. 6.7.2 Test Load Circuit This test load circuit is used to measure all switching characteristics provided in this document. Tester Pin Electronics 42 Ω Data Sheet Timing Reference Point 3.5 nH Transmission Line Output Under Test Z0 = 50 Ω Α Device Pin(B) 4.0 pF 1.85 pF A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timing. Figure 6-4. 3.3-V Test Load Circuit 94 Electrical Specifications Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com 6.7.3 SPRS584A – APRIL 2009 – REVISED MAY 2009 Device Clock Table This section provides the timing requirements and switching characteristics for the various clock options available on the 2803x MCUs. Table 6-3 lists the cycle times of various clocks. Table 6-3. 2803x Clock Table and Nomenclature (60-MHz Devices) Internal zero-pin oscillator 1 (INTOSC1) Internal zero-pin oscillator 2 (INTOSC2) On-chip crystal oscillator (X1/X2 pins) XCLKIN SYSCLKOUT XCLKOUT LSPCLK (1) ADC clock (1) (2) tc(ZPOSC1), Cycle time Frequency tc(ZPOSC2), Cycle time Frequency tc(OSC), Cycle time Frequency tc(CI), Cycle time Frequency NOM MAX UNIT 100 ns 10 MHz 100 ns 10 MHz 50 200 ns 5 20 MHz 16.67 250 ns MHz 4 60 16.67 500 ns 2 60 MHz tc(XCO), Cycle time 50 2000 Frequency 0.5 20 MHz 60 MHz 60 MHz tc(SCO), Cycle time Frequency tc(LCO), Cycle time 16.67 15 (2) Frequency tc(ADCCLK), Cycle time Frequency 66.7 (2) PRODUCT PREVIEW MIN ns ns 16.67 ns Lower LSPCLK will reduce device power consumption. This is the default reset value if SYSCLKOUT = 60 MHz. Submit Documentation Feedback Electrical Specifications 95 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 6.8 Clock Requirements and Characteristics Table 6-4. Input Clock Frequency PARAMETER MIN TYP MAX UNIT Resonator (X1/X2) 5 20 Crystal (X1/X2) 5 20 MHz External oscillator/clock source (XCLKIN pin) 4 fx Input clock frequency fl Limp mode SYSCLKOUT frequency range (with /2 enabled) 60 1–5 MHz Table 6-5. XCLKIN Timing Requirements - PLL Enabled NO. PRODUCT PREVIEW MIN MAX UNIT 33.3 200 ns 6 ns 6 ns 55 % C8 tc(CI) Cycle time, XCLKIN C9 tf(CI) Fall time, XCLKIN C10 tr(CI) Rise time, XCLKIN C11 tw(CIL) Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) 45 C12 tw(CIH) Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) 45 55 % MIN MAX UNIT 16.67 250 ns Up to 20 MHz 6 ns 20 MHz to 60 MHz 2 Up to 20 MHz 6 20 MHz to 60 MHz 2 Table 6-6. XCLKIN Timing Requirements - PLL Disabled NO. C8 tc(CI) Cycle time, XCLKIN C9 tf(CI) Fall time, XCLKIN C10 tr(CI) Rise time, XCLKIN ns C11 tw(CIL) Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) 45 55 % C12 tw(CIH) Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) 45 55 % The possible configuration modes are shown in Table 3-17. Table 6-7. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (2) NO. (1) (2) (3) 96 PARAMETER MIN TYP MAX 50 UNIT C1 tc(XCO) Cycle time, XCLKOUT C3 tf(XCO) Fall time, XCLKOUT 2 ns ns C4 tr(XCO) Rise time, XCLKOUT 2 ns C5 tw(XCOL) Pulse duration, XCLKOUT low H–2 H+2 C6 tw(XCOH) Pulse duration, XCLKOUT high H–2 H+2 ns tp PLL lock time (3) ms 1 ns A load of 40 pF is assumed for these parameters. H = 0.5tc(XCO) The PLLLOCKPRD register must be updated based on the number of OSCCLK cycles. Electrical Specifications Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 C10 C9 C8 XCLKIN(A) C6 C3 C1 C4 C5 XCLKOUT(B) A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is intended to illustrate the timing parameters only and may differ based on actual configuration. B. XCLKOUT configured to reflect SYSCLKOUT. 6.9 Power Sequencing There is no power sequencing requirement. However, it is recommended that no voltage larger than a diode drop (0.7 V) should be applied to any pin prior to powering up the device. Voltages applied to pins on an unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable results. Submit Documentation Feedback Electrical Specifications 97 PRODUCT PREVIEW Figure 6-5. Clock Timing TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com VDDIO, VDDA (3.3 V) VDD (1.8 V) INTOSC1 tINTOSCST X1/X2 tOSCST XCLKOUT OSCCLK/8 (A) PRODUCT PREVIEW User-code dependent tw(RSL1) XRS Address/data valid, internal boot-ROM code execution phase Address/Data/ Control (Internal) td(EX) th(boot-mode)(B) Boot-Mode Pins User-code execution phase User-code dependent GPIO pins as input Peripheral/GPIO function Based on boot code Boot-ROM execution starts I/O Pins(C) GPIO pins as input (state depends on internal PU/PD) User-code dependent A. Upon power up, SYSCLKOUT is OSCCLK/2. Since the XCLKOUTDIV bits in the XCLK register come up with a reset state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT = OSCCLK/8 during this phase. B. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled. C. See Section 6.9 for requirements to ensure a high-impedance state for GPIO pins during power-up. D. Using the XRS pin is optional due to the on-chip power-on reset (POR) circuitry. Figure 6-6. Power-on Reset 98 Electrical Specifications Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 Table 6-8. Reset (XRS) Timing Requirements MIN th(boot-mode) Hold time for boot-mode pins tw(RSL2) Pulse duration, XRS low on warm reset NOM MAX UNIT TBD cycles 8tc(OSCCLK) cyclies Table 6-9. Reset (XRS) Switching Characteristics over operating free-air temperature range (unless otherwise noted) TEST CONDITIONS Pulse duration, XRS driven by device tw(WDRS) Pulse duration, reset pulse generated by watchdog td(EX) Delay time, address/data valid after XRS high tINTOSCST Start up time, internal zero-pin oscillator tOSCST (1) On-chip crystal, oscillator start-up time (1) MIN TYP MAX UNIT µs 600 512tc(OSCCLK) cycles 32tc(OSCCLK) cycles 1 3 µs 10 ms PRODUCT PREVIEW PARAMETER tw(RSL1) Dependent on crystal/resonator and board design. INTOSC1 X1/X2 OSCCLK/8 XCLKOUT User-Code Dependent OSCCLK * 5 tw(RSL2) XRS Address/Data/ Control (Internal) td(EX) User-Code Execution (Don’t Care) Boot-ROM Execution Starts Boot-Mode Pins Peripheral/GPIO Function User-Code Execution Phase GPIO Pins as Input th(boot-mode)(A) Peripheral/GPIO Function User-Code Execution Starts I/O Pins User-Code Dependent GPIO Pins as Input (State Depends on Internal PU/PD) User-Code Dependent A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled. Figure 6-7. Warm Reset Submit Documentation Feedback Electrical Specifications 99 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Figure 6-8 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the PLL lock-up is complete,SYSCLKOUT reflects the new operating frequency, OSCCLK x 4. OSCCLK Write to PLLCR SYSCLKOUT OSCCLK * 2 OSCCLK/2 PRODUCT PREVIEW (CPU frequency while PLL is stabilizing with the desired frequency. This period (PLL lock-up time tp) is 1 ms long.) (Current CPU Frequency) OSCCLK * 4 (Changed CPU frequency) Figure 6-8. Example of Effect of Writing Into PLLCR Register 6.10 General-Purpose Input/Output (GPIO) 6.10.1 GPIO - Output Timing Table 6-10. General-Purpose Output Switching Characteristics PARAMETER MIN MAX UNIT tr(GPO) Rise time, GPIO switching low to high All GPIOs 8 tf(GPO) Fall time, GPIO switching high to low All GPIOs 8 ns ns tfGPO Toggling frequency 20 MHz GPIO tf(GPO) tr(GPO) Figure 6-9. General-Purpose Output Timing 100 Electrical Specifications Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com 6.10.2 SPRS584A – APRIL 2009 – REVISED MAY 2009 GPIO - Input Timing (A) GPIO Signal GPxQSELn = 1,0 (6 samples) 1 1 0 0 0 0 0 0 0 1 0 tw(SP) 0 0 1 1 1 1 1 1 1 1 1 Sampling Period determined by GPxCTRL[QUALPRD](B) tw(IQSW) (SYSCLKOUT cycle * 2 * QUALPRD) * 5(C)) Sampling Window SYSCLKOUT PRODUCT PREVIEW QUALPRD = 1 (SYSCLKOUT/2) (D) Output From Qualifier A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value "n", the qualification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled). B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins. C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used. D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure 5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition. Figure 6-10. Sampling Mode Table 6-11. General-Purpose Input Timing Requirements MIN tw(SP) tw(IQSW) tw(GPI) (2) (1) (2) Sampling period UNIT 1tc(SCO) cycles QUALPRD ≠ 0 2tc(SCO) * QUALPRD cycles Input qualifier sampling window Pulse duration, GPIO low/high MAX QUALPRD = 0 tw(SP) * (n Synchronous mode With input qualifier (1) – 1) cycles 2tc(SCO) cycles tw(IQSW) + tw(SP) + 1tc(SCO) cycles "n" represents the number of qualification samples as defined by GPxQSELn register. For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal. Submit Documentation Feedback Electrical Specifications 101 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 6.10.3 Sampling Window Width for Input Signals The following section summarizes the sampling window width for input signals for various input qualifier configurations. Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT. Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0 Sampling frequency = SYSCLKOUT, if QUALPRD = 0 Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD ≠ 0 In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT. Sampling period = SYSCLKOUT cycle, if QUALPRD = 0 In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the signal. This is determined by the value written to GPxQSELn register. PRODUCT PREVIEW Case 1: Qualification using 3 samples Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 2, if QUALPRD ≠ 0 Sampling window width = (SYSCLKOUT cycle) x 2, if QUALPRD = 0 Case 2: Qualification using 6 samples Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 5, if QUALPRD ≠ 0 Sampling window width = (SYSCLKOUT cycle) x 5, if QUALPRD = 0 XCLKOUT GPIOxn tw(GPI) Figure 6-11. General-Purpose Input Timing 102 Electrical Specifications Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 6.10.4 Low-Power Mode Wakeup Timing Table 6-12 shows the timing requirements, Table 6-13 shows the switching characteristics, and Figure 6-12 shows the timing diagram for IDLE mode. Table 6-12. IDLE Mode Timing Requirements (1) MIN tw(WAKE-INT) (1) Pulse duration, external wake-up signal Without input qualifier NOM MAX 2tc(SCO) With input qualifier UNIT cycles 5tc(SCO) + tw(IQSW) For an explanation of the input qualifier parameters, see Table 6-11. Table 6-13. IDLE Mode Switching Characteristics (1) TEST CONDITIONS Delay time, external wake signal to program execution resume • td(WAKE-IDLE) • • MIN TYP MAX (2) Wake-up from Flash – Flash module in active state Without input qualifier Wake-up from Flash – Flash module in sleep state Without input qualifier Wake-up from SARAM Without input qualifier cycles 20tc(SCO) With input qualifier cycles 20tc(SCO) + tw(IQSW) 1050tc(SCO) With input qualifier cycles 1050tc(SCO) + tw(IQSW) 20tc(SCO) With input qualifier (1) (2) UNIT cycles 20tc(SCO) + tw(IQSW) For an explanation of the input qualifier parameters, see Table 6-11. This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered by the wake up) signal involves additional latency. td(WAKE−IDLE) Address/Data (internal) XCLKOUT tw(WAKE−INT) WAKE A. INT(A) WAKE INT can be any enabled interrupt, WDINT or XRS. Figure 6-12. IDLE Entry and Exit Timing Table 6-14. STANDBY Mode Timing Requirements tw(WAKE-INT) (1) Pulse duration, external wake-up signal TEST CONDITIONS MIN Without input qualification 3tc(OSCCLK) With input qualification (1) (2 + QUALSTDBY) * tc(OSCCLK) NOM MAX UNIT cycles QUALSTDBY is a 6-bit field in the LPMCR0 register. Submit Documentation Feedback Electrical Specifications 103 PRODUCT PREVIEW PARAMETER TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Table 6-15. STANDBY Mode Switching Characteristics PARAMETER td(IDLE-XCOL) TEST CONDITIONS Delay time, IDLE instruction executed to XCLKOUT low MIN TYP 32tc(SCO) MAX UNIT 45tc(SCO) cycles Delay time, external wake signal to program execution resume (1) • td(WAKE-STBY) • Without input qualifier Wake up from flash – Flash module in sleep state Without input qualifier 100tc(SCO) With input qualifier 100tc(SCO) + tw(WAKE-INT) Wake up from SARAM cycles 1125tc(SCO) With input qualifier 1125tc(SCO) + tw(WAKE-INT) Without input qualifier • PRODUCT PREVIEW (1) Wake up from flash – Flash module in active state cycles 100tc(SCO) With input qualifier 100tc(SCO) + tw(WAKE-INT) cycles cycles This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered by the wake up signal) involves additional latency. (A) (C) (B) Device Status STANDBY (E) (D) (F) STANDBY Normal Execution Flushing Pipeline Wake-up Signal tw(WAKE-INT) td(WAKE-STBY) X1/X2 or XCLKIN XCLKOUT td(IDLE−XCOL) A. IDLE instruction is executed to put the device into STANDBY mode. B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles before being turned off. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly. C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. D. The external wake-up signal is driven active. E. After a latency period, the STANDBY mode is exited. F. Normal execution resumes. The device will respond to the interrupt (if enabled). Figure 6-13. STANDBY Entry and Exit Timing Diagram Table 6-16. HALT Mode Timing Requirements MIN NOM MAX UNIT tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal toscst + 2tc(OSCCLK) cycles tw(WAKE-XRS) Pulse duration, XRS wakeup signal toscst + 8tc(OSCCLK) cycles 104 Electrical Specifications Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 Table 6-17. HALT Mode Switching Characteristics PARAMETER MIN Delay time, IDLE instruction executed to XCLKOUT low tp PLL lock-up time td(WAKE-HALT) Delay time, PLL lock to program execution resume • Wake up from flash – Flash module in sleep state • TYP 32tc(SCO) MAX UNIT 45tc(SCO) cycles 1 1125tc(SCO) cycles 35tc(SCO) cycles Wake up from SARAM (A) (C) Device Status (D) HALT Flushing Pipeline (G) (E) (B) ms (F) HALT PLL Lock-up Time Wake-up Latency PRODUCT PREVIEW td(IDLE-XCOL) Normal Execution GPIOn td(WAKE−HALT) tw(WAKE-GPIO) tp X1/X2 or XCLKIN Oscillator Start-up Time XCLKOUT td(IDLE−XCOL) A. IDLE instruction is executed to put the device into HALT mode. B. The PLL block responds to the HALT signal. SYSCLKOUT is held for approximately 32 cycles before the oscillator is turned off and the CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly. C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power. D. When the GPIOn pin is driven low, the oscillator is turned on and the oscillator wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal during the PLL lock sequence. Since the falling edge of the GPIO pin asynchronously begins the wakeup procedure, care should be taken to maintain a low noise environment prior to entering and during HALT mode. E. When GPIOn is deactivated, it initiates the PLL lock sequence, which takes 131,072 OSCCLK (X1/X2 or X1 or XCLKIN) cycles. F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT mode is now exited. G. Normal operation resumes. Figure 6-14. HALT Wake-Up Using GPIOn Submit Documentation Feedback Electrical Specifications 105 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 6.11 Enhanced Control Peripherals 6.11.1 Enhanced Pulse Width Modulator (ePWM) Timing PWM refers to PWM outputs on ePWM1–7. Table 6-18 shows the PWM timing requirements and Table 6-19, switching characteristics. Table 6-18. ePWM Timing Requirements (1) TEST CONDITIONS tw(SYCIN) Sync input pulse width MIN UNIT Asynchronous 2tc(SCO) cycles Synchronous 2tc(SCO) cycles 1tc(SCO) + tw(IQSW) cycles With input qualifier (1) MAX For an explanation of the input qualifier parameters, see Table 6-11. PRODUCT PREVIEW Table 6-19. ePWM Switching Characteristics PARAMETER tw(PWM) Pulse duration, PWMx output high/low tw(SYNCOUT) Sync output pulse width td(PWM)tza Delay time, trip input active to PWM forced high Delay time, trip input active to PWM forced low td(TZ-PWM)HZ Delay time, trip input active to PWM Hi-Z TEST CONDITIONS MIN MAX 20 UNIT ns 8tc(SCO) cycles no pin load 25 ns 20 ns 6.11.2 Trip-Zone Input Timing XCLKOUT(A) tw(TZ) TZ td(TZ-PWM)HZ PWM(B) A. TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6 B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software. Figure 6-15. PWM Hi-Z Characteristics Table 6-20. Trip-Zone input Timing Requirements (1) MIN tw(TZ) Pulse duration, TZx input low Asynchronous Synchronous With input qualifier (1) MAX UNIT 1tc(SCO) cycles 2tc(SCO) cycles 1tc(SCO) + tw(IQSW) cycles For an explanation of the input qualifier parameters, see Table 6-11. Table 6-21 shows the high-resolution PWM switching characteristics. 106 Electrical Specifications Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 Table 6-21. High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz) MIN Micro Edge Positioning (MEP) step size (1) (1) (2) TYP MAX UNIT 150 310 ps (2) Maximum MEP step size is based on worst-case process, maximum temperature and maximum voltage. MEP step size will increase with low voltage and high temperature and decrease with voltage and cold temperature. Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per SYSCLKOUT period dynamically while the HRPWM is in operation. Between 40 to 50 MHz SYSCLKOUT under worst case process, voltage, and temperature (maximum voltage and minimum temperature) conditions, the MEP step delay may decrease to a point such that the maximum of 254 MEP steps may not cover 1 full SYSCLKOUT cycle. In other words, high-resolution edge control will not be available for the full range of a SYSCLKOUT cycle. If running SFO calibration software, the SFO function will return an error code of “2” when this occurs. See the TMS320x2802x, 2803x Piccolo High-Resolution Pulse Width Modulator (HRPWM) Reference Guide (literature number SPRUGE8) for more information on this error condition. Table 6-22 shows the eCAP timing requirement and Table 6-23 shows the eCAP switching characteristics. Table 6-22. Enhanced Capture (eCAP) Timing Requirement (1) TEST CONDITIONS tw(CAP) Capture input pulse width MIN UNIT 2tc(SCO) cycles Synchronous 2tc(SCO) cycles 1tc(SCO) + tw(IQSW) cycles With input qualifier (1) MAX Asynchronous For an explanation of the input qualifier parameters, see Table 6-11. Table 6-23. eCAP Switching Characteristics PARAMETER tw(APWM) TEST CONDITIONS MIN Pulse duration, APWMx output high/low MAX UNIT 20 ns 6.11.4 Enhanced Quadrature Encoder Pulse (eQEP) Timing Table 6-24 shows the eQEP timing requirement and Table 6-25 shows the eQEP switching characteristics. Table 6-24. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements (1) TEST CONDITIONS tw(QEPP) QEP input period tw(INDEXH) QEP Index Input High time With input qualifier tw(INDEXL) QEP Index Input Low time tw(STROBH) QEP Strobe High time QEP Strobe Input Low time cycles 2tc(SCO) cycles 2tc(SCO) +tw(IQSW) cycles 2tc(SCO) cycles 2tc(SCO) + tw(IQSW) cycles 2tc(SCO) cycles 2tc(SCO) + tw(IQSW) cycles 2tc(SCO) cycles 2tc(SCO) +tw(IQSW) cycles Asynchronous/synchronous With input qualifier (1) 2(1tc(SCO) + tw(IQSW)) Asynchronous/synchronous With input qualifier UNIT cycles Asynchronous/synchronous With input qualifier MAX 2tc(SCO) Asynchronous/synchronous With input qualifier tw(STROBL) MIN Asynchronous/synchronous For an explanation of the input qualifier parameters, see Table 6-11. Table 6-25. eQEP Switching Characteristics PARAMETER TEST CONDITIONS MIN MAX UNIT td(CNTR)xin Delay time, external clock to counter increment 4tc(SCO) cycles td(PCS-OUT)QEP Delay time, QEP input edge to position compare sync output 6tc(SCO) cycles Submit Documentation Feedback Electrical Specifications 107 PRODUCT PREVIEW 6.11.3 Enhanced Capture (eCAP) Timing TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 6.11.5 ADC Start-of-Conversion Timing Table 6-26. External ADC Start-of-Conversion Switching Characteristics PARAMETER tw(ADCSOCL) MIN Pulse duration, ADCSOCxO low MAX 32tc(HCO) UNIT cycles tw(ADCSOCL) ADCSOCAO or ADCSOCBO Figure 6-16. ADCSOCAO or ADCSOCBO Timing 6.11.6 External Interrupt Timing PRODUCT PREVIEW tw(INT) XINT1, XINT2, XINT3 td(INT) Address bus (internal) Interrupt Vector Figure 6-17. External Interrupt Timing Table 6-27. External Interrupt Timing Requirements (1) TEST CONDITIONS tw(INT) (2) (1) (2) Pulse duration, INT input low/high MIN MAX UNIT Synchronous 1tc(SCO) cycles With qualifier 1tc(SCO) + tw(IQSW) cycles For an explanation of the input qualifier parameters, see Table 6-11. This timing is applicable to any GPIO pin configured for ADCSOC functionality. Table 6-28. External Interrupt Switching Characteristics (1) PARAMETER td(INT) (1) 108 Delay time, INT low/high to interrupt-vector fetch MIN MAX UNIT tw(IQSW) + 12tc(SCO) cycles For an explanation of the input qualifier parameters, see Table 6-11. Electrical Specifications Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 6.11.7 I2C Electrical Specification and Timing Table 6-29. I2C Timing MIN I2C clock module frequency is between 7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately MAX UNIT 400 kHz SCL clock frequency vil Low level input voltage Vih High level input voltage Vhys Input hysteresis Vol Low level output voltage 3 mA sink current tLOW Low period of SCL clock I2C clock module frequency is between 7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately 1.3 µs tHIGH High period of SCL clock I2C clock module frequency is between 7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately 0.6 µs lI Input current with an input voltage between 0.1 VDDIO and 0.9 VDDIO MAX 0.3 VDDIO 0.7 VDDIO V 0.05 VDDIO 0 –10 V V 0.4 10 V µA 6.11.8 Serial Peripheral Interface (SPI) Master Mode Timing Table 6-30 lists the master mode timing (clock phase = 0) and Table 6-31 lists the timing (clock phase = 1). Figure 6-18 and Figure 6-19 show the timing waveforms. Submit Documentation Feedback Electrical Specifications 109 PRODUCT PREVIEW TEST CONDITIONS fSCL TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Table 6-30. SPI Master Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5) SPI WHEN (SPIBRR + 1) IS EVEN OR SPIBRR = 0 OR 2 NO. SPI WHEN (SPIBRR + 1) IS ODD AND SPIBRR > 3 UNIT MIN MAX MIN MAX 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns ns 1 tc(SPC)M Cycle time, SPICLK 2 tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) td(SPCH-SIMO)M Delay time, SPICLK high to SPISIMO valid (clock polarity = 0) 10 10 td(SPCL-SIMO)M Delay time, SPICLK low to SPISIMO valid (clock polarity = 1) 10 10 tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M + 0.5tc(LCO) – 10 tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) 0.5tc(SPC)M – 10 0.5tc(SPC)M + 0.5tc(LCO) – 10 tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low (clock polarity = 0) 35 35 tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high (clock polarity = 1) 35 35 tv(SPCL-SOMI)M Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0) 0.25tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LCO) – 10 tv(SPCH-SOMI)M Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1) 0.25tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LCO) – 10 3 4 5 8 9 (1) (2) (3) (4) (5) 110 ns ns ns ns ns The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared. tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1) tc(LCO) = LSPCLK cycle time Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 20-MHz MAX, master mode receive 10-MHz MAX Slave mode transmit 10-MAX, slave mode receive 10-MHz MAX. The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6). Electrical Specifications Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 6 7 Master out data Is valid SPISIMO Data Valid 10 PRODUCT PREVIEW 11 Master in data must be valid SPISOMI SPISTE(A) A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and nonFIFO modes. Figure 6-18. SPI Master Mode External Timing (Clock Phase = 0) Submit Documentation Feedback Electrical Specifications 111 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com Table 6-31. SPI Master Mode External Timing (Clock Phase = 1) (1) (2) (3) (4) (5) SPI WHEN (SPIBRR + 1) IS EVEN OR SPIBRR = 0 OR 2 NO. SPI WHEN (SPIBRR + 1) IS ODD AND SPIBRR > 3 UNIT MIN MAX MIN MAX 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns ns 1 tc(SPC)M Cycle time, SPICLK 2 tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc (LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) tw(SPCL))M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc (LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) tsu(SIMO-SPCH)M Setup time, SPISIMO data valid before SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 tsu(SIMO-SPCL)M Setup time, SPISIMO data valid before SPICLK low (clock polarity = 1) 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high (clock polarity = 0) 35 35 tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low (clock polarity = 1) 35 35 tv(SPCH-SOMI)M Valid time, SPISOMI data valid after SPICLK high (clock polarity = 0) 0.25tc(SPC)M – 10 0.5tc(SPC)M – 10 tv(SPCL-SOMI)M Valid time, SPISOMI data valid after SPICLK low (clock polarity = 1) 0.25tc(SPC)M – 10 0.5tc(SPC)M – 10 3 6 7 10 11 (1) (2) (3) (4) (5) 112 ns ns ns ns ns The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set. tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 20 MHz MAX, master mode receive 10 MHz MAX Slave mode transmit 10 MHz MAX, slave mode receive 10 MHz MAX. tc(LCO) = LSPCLK cycle time The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). Electrical Specifications Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 6 7 Master out data Is valid SPISIMO Data Valid 11 Master in data must be valid SPISOMI SPISTE(A) A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and nonFIFO modes. Figure 6-19. SPI Master Mode External Timing (Clock Phase = 1) 6.11.9 SPI Slave Mode Timing Table 6-32 lists the slave mode external timing (clock phase = 0) and Table 6-33 (clock phase = 1). Figure 6-20 and Figure 6-21 show the timing waveforms. Table 6-32. SPI Slave Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5) NO. MIN MAX 12 tc(SPC)S Cycle time, SPICLK 13 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S td(SPCH-SOMI)S Delay time, SPICLK high to SPISOMI valid (clock polarity = 0) td(SPCL-SOMI)S Delay time, SPICLK low to SPISOMI valid (clock polarity = 1) tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0) 0.75tc(SPC)S tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1) 0.75tc(SPC)S tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 0) tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 1) tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10 14 15 16 19 20 (1) (2) (3) (4) (5) 4tc(LCO) UNIT ns 35 ns ns ns 35 35 ns ns 35 ns The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared. tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 20-MHz MAX, master mode receive 10-MHz MAX Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX. tc(LCO) = LSPCLK cycle time The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). Submit Documentation Feedback Electrical Specifications 113 PRODUCT PREVIEW 10 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 12 SPICLK (clock polarity = 0) 13 14 SPICLK (clock polarity = 1) 15 16 SPISOMI data Is valid SPISOMI PRODUCT PREVIEW 19 20 SPISIMO data must be valid SPISIMO SPISTE(A) A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) (minimum) before the valid SPI clock edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit. Figure 6-20. SPI Slave Mode External Timing (Clock Phase = 0) Table 6-33. SPI Slave Mode External Timing (Clock Phase = 1) (1) (2) (3) (4) NO. MIN MAX 12 tc(SPC)S Cycle time, SPICLK 13 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S tsu(SOMI-SPCH)S Setup time, SPISOMI before SPICLK high (clock polarity = 0) 0.125tc(SPC)S tsu(SOMI-SPCL)S Setup time, SPISOMI before SPICLK low (clock polarity = 1) 0.125tc(SPC)S tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0) 0.75tc(SPC)S tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1) 0.75tc(SPC)S tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 0) 35 tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 1) 35 tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 14 17 18 21 22 (1) (2) (3) (4) 114 8tc(LCO) UNIT ns ns ns ns ns ns ns The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared. tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 20-MHz MAX, master mode receive 10-MHz MAX Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX. The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). Electrical Specifications Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 12 SPICLK (clock polarity = 0) 13 14 SPICLK (clock polarity = 1) 17 18 SPISOMI data is valid SPISOMI Data Valid PRODUCT PREVIEW 21 22 SPISIMO data must be valid SPISIMO SPISTE(A) A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit. Figure 6-21. SPI Slave Mode External Timing (Clock Phase = 1) 6.11.9.1 On-chip Comparator/DAC Table 6-34. Electrical Characteristics of the Comparator/DAC CHARACTERISTIC MIN TYP MAX UNITS Comparator Comparator Input Range VSSA – VDDA V Comparator response time to PWM Trip Zone (Async) 30 ns Input Offset ±5 mV 35 mV Input Hysteresis DAC DAC Output Range DAC resolution DAC settling time DAC Gain DAC Offset No Missing Codes INL Submit Documentation Feedback VSSA – VDDA V 10 bits 2 us –1.5 % 10 mV Yes ±3 LSB Electrical Specifications 115 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 6.11.10 On-Chip Analog-to-Digital Converter Table 6-35. ADC Electrical Characteristics (over recommended operating conditions) PARAMETER MIN TYP MAX UNIT DC SPECIFICATIONS Resolution 12 ADC clock 60-MHz device Bits 0.001 60 MHz ACCURACY INL (Integral nonlinearity) 60-MHz clock (4.62 MSPS) ±2 LSB ±1 LSB ±10 LSB Overall gain error with internal reference ±10 LSB Overall gain error with external reference DNL (Differential nonlinearity) Offset error (1) PRODUCT PREVIEW ±10 LSB Channel-to-channel offset variation ±4 LSB Channel-to-channel gain variation ±4 LSB ANALOG INPUT Analog input voltage (2) with internal reference 0 3.3 V Analog input voltage (2) with external reference VREFLO VREFHI V 0.66 V 2.64 VDDA V 1.98 VDDA VREFLO input voltage (3) VSSA VREFHI input voltage with VREFLO = VSSA V Temperature coefficient 50 Input capacitance 10 pF Input leakage current ±5 µA (1) (2) (3) PPM/°C 1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and VREFHI - VREFLO for external reference. Voltages above VDDA + 0.3 V or below VSS - 0.3 V applied to an analog input pin may temporarily affect the conversion of another pin. To avoid this, the analog inputs should be kept within these limits. VREFLO is always connected to VSSA on the 64-pin PAG device. 6.11.10.1 Internal Temperature Sensor Table 6-36. Temperature Sensor Coefficient PARAMETER (1) TΔ (1) (2) (3) Degrees C of temperature movement per measured ADC LSB change of the temperature sensor MIN TYP 0.18 MAX UNIT °C/LSB (2) (3) Temperature Coefficient given in terms of ADC LSB using the internal reference of the ADC. ADC temperature coeffieicient is accounted for in this specification Output of the temperature sensor (in terms of LSBs) is sign-consistent with the direction of the temperature movement. Increasing temperatures will give increasing ADC values relative to an initial value; decreasing temperatures will give decreasing ADC values relative to an initial value. 6.11.10.2 ADC Power-Up Control Bit Timing Table 6-37. ADC Power-Up Delays PARAMETER (1) td(PWD) (1) 116 Delay time for the ADC to be stable after power up MIN TYP MAX 1 UNIT ms Timings maintain compatibility to the ADC module. The 2802x ADC supports driving all 3 bits at the same time td(PWD) ms before first conversion. Electrical Specifications Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 ADCPWDN/ ADCBGPWD/ ADCREFPWD/ ADCENABLE td(PWD) Request for ADC Conversion Figure 6-22. ADC Conversion Timing 6.11.10.2.1 ADC Sequential and Simultaneous Timings 0 2 9 15 22 24 37 ADCCLK ADCCTL 1.INTPULSEPOS PRODUCT PREVIEW ADCSOCFLG 1.SOC0 ADCSOCFLG 1.SOC1 ADCSOCFLG 1.SOC2 S/H Window Pulse to Core SOC0 ADCRESULT 0 SOC1 2 ADCCLKs SOC2 Result 0 Latched ADCRESULT 1 EOC0 Pulse EOC1 Pulse ADCINTFLG .ADCINTx Minimum 7 ADCCLKs Conversion 0 13 ADC Clocks 6 ADCCLKs Minimum 7 ADCCLKs 1 ADCCLK Conversion 1 13 ADC Clocks Figure 6-23. Timing Example For Sequential Mode / Late Interrupt Pulse Submit Documentation Feedback Electrical Specifications 117 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 0 2 9 15 22 24 37 ADCCLK ADCCTL1.INTPULSEPOS ADCSOCFLG 1.SOC0 ADCSOCFLG 1.SOC1 ADCSOCFLG 1.SOC2 S/H Window Pulse to Core SOC0 SOC1 SOC2 Result 0 Latched ADCRESULT 0 ADCRESULT 1 PRODUCT PREVIEW EOC0 Pulse EOC1 Pulse EOC2 Pulse ADCINTFLG .ADCINTx Minimum 7 ADCCLKs Conversion 0 13 ADC Clocks 6 ADCCLKs Minimum 7 ADCCLKs 2 ADCCLKs Conversion 1 13 ADC Clocks Figure 6-24. Timing Example For Sequential Mode / Early Interrupt Pulse 118 Electrical Specifications Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 0 2 9 15 22 24 37 50 ADCCLK ADCCTL1.INTPULSEPOS ADCSOCFLG 1.SOC0 ADCSOCFLG 1.SOC1 ADCSOCFLG 1.SOC2 SOC0 (A/B) SOC2 (A/B) 2 ADCCLKs ADCRESULT 0 Result 0 (A) Latched ADCRESULT 1 Result 0 (B) Latched PRODUCT PREVIEW S/H Window Pulse to Core ADCRESULT 2 EOC0 Pulse 1 ADCCLK EOC1 Pulse EOC2 Pulse ADCINTFLG .ADCINTx Minimum 7 ADCCLKs Conversion 0 (A) 13 ADC Clocks 19 ADCCLKs Conversion 0 (B) 13 ADC Clocks Minimum 7 ADCCLKs 2 ADCCLKs Conversion 1 (A) 13 ADC Clocks Figure 6-25. Timing Example For Simultaneous Mode / Late Interrupt Pulse Submit Documentation Feedback Electrical Specifications 119 TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 0 2 www.ti.com 9 15 22 24 37 50 ADCCLK ADCCTL1.INTPULSEPOS ADCSOCFLG 1.SOC0 ADCSOCFLG 1.SOC1 ADCSOCFLG 1.SOC2 S/H Window Pulse to Core SOC0 (A/B) SOC2 (A/B) 2 ADCCLKs ADCRESULT 0 Result 0 (A) Latched ADCRESULT 1 Result 0 (B) Latched PRODUCT PREVIEW ADCRESULT 2 EOC0 Pulse EOC1 Pulse EOC2 Pulse ADCINTFLG .ADCINTx Minimum 7 ADCCLKs Conversion 0 (A) 13 ADC Clocks 19 ADCCLKs Conversion 0 (B) 13 ADC Clocks Minimum 7 ADCCLKs 2 ADCCLKs Conversion 1 (A) 13 ADC Clocks Figure 6-26. Timing Example For Simultaneous Mode/Early Interrupt Pulse 120 Electrical Specifications Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 6.12 Detailed Descriptions Integral Nonlinearity Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point is defined as level one-half LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line between these two points. Differential Nonlinearity An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes. The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the deviation of the actual transition from that point. Gain Error The first code transition should occur at an analog value one-half LSB above negative full scale. The last transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Signal-to-Noise Ratio + Distortion (SINAD) SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Effective Number of Bits (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following (SINAD * 1.76) N+ 6.02 formula, it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. Spurious Free Dynamic Range (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. Submit Documentation Feedback Electrical Specifications 121 PRODUCT PREVIEW Zero Offset TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers SPRS584A – APRIL 2009 – REVISED MAY 2009 www.ti.com 7 Revision History This data sheet revision history highlights the technical changes made to the SPRS584 device-specific data sheet to make it an SPRS584A revision. Scope: Added Section 6.11.5, ADC Start-of-Conversion Timing. Added Section 6.11.10.1, Internal Temperature Sensor. See table below. LOCATION Section 1.1 PRODUCT PREVIEW Table 2-1 Hardware Features: • Added "Temperature Sensor" row to "12-Bit ADC" FEATURE Figure 3-2 28034/28035 Memory Map: • Updated memory map from 0x3D 7C80 to 0x3D 8000 Figure 3-3 28032/28033 Memory Map: • Updated memory map from 0x3D 7C80 to 0x3D 8000 Table 3-9 Device Emulation Registers: • PARTID: Changed ADDRESS RANGE from 0x3D 7FFF to 0x3D 7E80 • Added footnote Section 5.1 Device and Development Support Tool Nomenclature: • Changed example of temperature range from "S" to "T" Figure 5-1 Device Nomenclature: • Changed example of temperature range from "S" to "T" Section 6.11 Enhanced Control Peripherals: • Added Section 6.11.5, ADC Start-of-Conversion Timing Table 6-35 Section 6.11.10.1 122 ADDITIONS, DELETIONS, AND MODIFICATIONS Features: • Added "On-Chip Temperature Sensor" feature Revision History ADC Electrical Characteristics (over recommended operating conditions): • VREFLO input voltage: – Changed MIN value from 0 V to VSSA – Changed MAX value from 0.6 V to 0.66 V • VREFHI input voltage: – Added MIN value of 2.64 V – Added MAX value of VDDA Added "Internal Temperature Sensor" section Submit Documentation Feedback TMS320F28032, TMS320F28033 TMS320F28034, TMS320F28035 Piccolo Microcontrollers www.ti.com SPRS584A – APRIL 2009 – REVISED MAY 2009 8 Mechanicals PRODUCT PREVIEW The mechanical package diagram(s) that follow the tables reflect the most current released mechanical data available for the designated device(s). Submit Documentation Feedback Mechanicals 123 PACKAGE OPTION ADDENDUM www.ti.com 6-May-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TMX320F28035PAGT ACTIVE TQFP PAG 64 1 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TMX320F28035PNT ACTIVE LQFP PN 80 1 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996 PN (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 41 60 61 40 80 21 0,13 NOM 1 20 Gage Plane 9,50 TYP 12,20 SQ 11,80 14,20 SQ 13,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040135 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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