bq24210 SLUSA76A – DECEMBER 2010 – REVISED MAY 2011 www.ti.com 800mA, Single-Input, Single Cell Li-Ion Battery Solar Charger Check for Samples: bq24210 FEATURES APPLICATIONS • • • • • • 1 • • • • • • • • • • • • Input Voltage Dynamic Power Management Feature (VBUS_DPM) Selectable Battery Tracking Mode to Maximize the Charge Rate from Solar Panel Using DPM Feature Load Mode to Support Loads Connected at VBUS Pin 20V Input Rating, with Over-Voltage Protection (OVP) 1% Battery Voltage Regulation Accuracy Up to 800mA Charge Current with 10% Charge Current Accuracy Thermal Regulation Protection for Output Current Control Low Battery Leakage Current BAT Short-Circuit Protection NTC Input Monitoring Built-In Safety Timer With Reset Control Status Indication – Charging/Power Present Available in Small 2mm × 3mm SON-10 Package Smart Phones PDAs MP3 Players Low-Power Handheld Devices Auxiliary Solar Chargers DESCRIPTION The bq24210 is a highly integrated Li-ion linear charger targeted at space-limited portable applications. The high input voltage range with input over-voltage protection supports low-cost unregulated adapters. The input voltage regulation loop with programmable input voltage regulation threshold make it suitable for charging from alternative power sources, such as solar panel or inductive charging pad. The IC has a single power output that charges the battery. A system load can be placed in parallel with the battery as long as the average system load does not keep the battery from charging fully during the 10 hour safety timer. The battery is charged in three phases: conditioning, constant current and constant voltage. In all charge phases, an internal control loop monitors the IC junction temperature and reduces the charge current if an internal temperature threshold is exceeded. bq24210 VIN Q2 BAT 10 Q1 1 System Load VBUS CHG 8 1mF ` PG 1mF 6 VTSB 4 7 EN RT1 TS 5 Host VDPM 9 ISET 2 TEMP PACK + VSS 3 PACK - 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2011, Texas Instruments Incorporated bq24210 SLUSA76A – DECEMBER 2010 – REVISED MAY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The charger power stage and charge current sense functions are fully integrated. The charger function has high accuracy current and voltage regulation loops, charge status display, and charge termination function. The charge current value is programmable via an external resistor. Furthermore, the IC has a Load Mode that connects the battery to VBUS pin with current limiting function to prevent over load. To use Load Mode, the charging source would be removed from the VBUS pin. Then a load can be placed on VBUS pin and it will be near the VBAT pin voltage. PIN CONFIGURATION Figure 1. DQC PACKAGE Top View 1 VBUS BAT 10 2 ISET VDPM 9 3 VSS CHG 8 4 VTSB EN 7 5 TS PG 6 PIN FUNCTIONS PIN NAME NO. VBUS 1 I/O I/O DESCRIPTION For Charging Mode, input for charging source, connect to external DC supply (ie, Solar Panel, Inductive charging PAD, or Wall Adapter) For Load Mode, output for current limited battery voltage. Expected range of bypass capacitors 1μF to 10μF, connected from VBUS to VSS. BAT 10 I/O VDPM 9 I Battery Connection. System Load may be connected. Expected range of bypass capacitors 1μF to 10μF, connected from BAT to VSS. Programs the input voltage regulation threshold. Expected range of programming resistor is 1kΩ to 10 kΩ, connected from VDPM to VSS. When VDPM is floating, the VIN DPM loop operates in battery tracking mode, and the VIN DPM threshold is BAT+100mV (BAT>3.6V) or 3.7V (BAT≤3.6V) in this case. VIN DPM threshold should be programmed higher than battery voltage to ensure proper operation. ISET 2 I Programs the Fast-charge current setting. External resistor from ISET to VSS defines fast charge current value. PG 6 O Power Present indication. LOW (FET ON) When input voltage is in normal range (VBUS>BAT and VBUS>UVLO), High impedance (open drain FET OFF) in other cases. TS 5 I Temperature sense pin, connected to NTC Thermistor in the battery pack. Pulling High puts part in Limited Power charging mode. Must not be left floating. VSS 3 – Ground terminal CHG 8 O Charge Status indication, Low (FET ON) indicates charging, and High impedance (open drain FET OFF) in other cases EN 7 I Chip enable control. Low to enable Charge or Load Mode, and High to enable Suspend mode. VTSB 4 O TS bias reference voltage pin, regulated output. No external capacitor is required from VTSB to VSS. Only enabled during charge. Thermal PAD and Package – – There is an internal electrical connection between the exposed thermal pad and the VSS pin of the device. The thermal pad must be connected to the same potential as the VSS pin on the printed circuit board. Do not use the thermal pad as the primary ground input for the device. VSS pin must be connected to ground at all times. 2 Copyright © 2010–2011, Texas Instruments Incorporated bq24210 SLUSA76A – DECEMBER 2010 – REVISED MAY 2011 www.ti.com TYPICAL APPLICATION CIRCUIT: bq24210 bq24210 7V Charging Source 20 V BAT 1 10 System VBUS 1mF ` PG 7 EN CHG 8 PG 6 VTSB 4 1 mF RT1 Tied to PG pin for auto-enabling charging operations and disabling of Load Mode PACK+ TS VDPM 9 ISET VSS 2 3 5 TEMP PACK- Open for Battery Tracking Mode Figure 2. Typical System Schematic Copyright © 2010–2011, Texas Instruments Incorporated 3 bq24210 SLUSA76A – DECEMBER 2010 – REVISED MAY 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating temperature range (unless otherwise noted) VALUE Input Voltage VBUS (with respect to VSS) –0.3 to 20 BAT (with respect to VSS) –0.3 to 7 VDPM, VTSB, ISET, TS, EN, CHG, PG (with respect to VSS) –0.3 to 7 UNIT V Input Current VBUS 1.25 Output Current (Continuous) BAT 1.25 A Output Sink Current CHG, PG 15 mA Junction temperature, TJ –40 to 150 °C Storage temperature, TSTG –65 to 150 °C (1) A Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. THERMAL INFORMATION THERMAL METRIC (1) bq24210 SON-10 PIN θJA Junction-to-ambient thermal resistance 60.7 θJCtop Junction-to-case (top) thermal resistance 53.1 θJB Junction-to-board thermal resistance 22.2 ψJT Junction-to-top characterization parameter 0.8 ψJB Junction-to-board characterization parameter 22.1 θJCbot Junction-to-case (bottom) thermal resistance 4.7 (1) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. RECOMMENDED OPERATING CONDITIONS VBUS MIN MAX Voltage range 3.5 18 Operating voltage range, Restricted by UVLO and OVP 3.5 7.0 UNITS V IBUS Input current, VBUS pin 0.8 IBAT Current, BAT pin 0.8 A TJ Junction Temperature 125 °C RVDPM Programs input voltage regulation Thresholds 1k 10k Ω RISET Fast-charge current programming resistor 675 10.8K Ω VTS Voltage across NTC Thermistor for charging CBAT By-pass capacitor on BAT pin 1 10 µF CVBUS By-pass capacitor on VBUS pin 1 10 µF CVTSB By-pass capacitor on VTSB pin 0.1 µF 4 0 Submit Documentation Feedback 12 A 57 %VTSB Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :bq24210 bq24210 SLUSA76A – DECEMBER 2010 – REVISED MAY 2011 www.ti.com ELECTRICAL CHARACTERISTICS Over junction temperature range 0°C ≤ TJ ≤ 125°C, VBUS=5V, Charge mode (EN = Low) (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT VUVLO Under-voltage lock-out Exit VBUS: 0V → 4V 3.15 3.3 3.45 V VHYS_UVLO Hysteresis on VUVLO Falling VBUS: 4V→0V,VUVLO_FALL = VUVLO–VHYS-UVLO 175 227 280 mV VBUS-DT Input Power Good detection threshold VBUS above BAT (Input power good if VBUS > BAT + VBUS-DT); BAT = 3.6V, VBUS: 3.5V → 4V 150 200 250 mV VHYS-VBUSDT Hysteresis on VBUS-DT Falling BAT = 3.6V, VBUS: 4V → 3.5V 250 mV tDGL(PG_PWR) Deglitch time on exiting sleep Time measured from VBUS: 0V → 5V 1μs rise-time to PG = Low, BAT=3.6V 90 µs tDGL(PG_NO-PWR) Deglitch time on VHYS-VBUSDT power down. Same as entering sleep. Time measured from VBUS: 5V → 3.2V 1μs fall-time to PG = Open Circuit 29 ms VOVP Input over-voltage protection threshold VBUS: 5V → 8V VHYS-OVP Hysteresis on OVP VBUS: 11V → 5V 200 mV tBLK(OVP) Input over-voltage blanking time VBUS: 5V → 12V 113 μs tDGL(PG_OVP) Deglitch time exiting OVP Time measured from VBUS: 12V → 5V 1μs fall-time to PG = Low 5 ms VBUS-DPM Input voltage regulation threshold. Restricts lout at VBUS-DPM 7.3 7.5 7.7 V Programmable, the programming resistor at VDPM pin RVDPM = 1kΩ 3.55 3.65 3.75 Programmable, the programming resistor at VDPM pin RVDPM = 10kΩ 4.8 5 5.1 0.135 0.15 0.165 V/KΩ 3.41 3.5 3.59 V KVBUS_DPM Term Factor BAT > VLOWV, VBUS = 5V, RVDPM = 1k to 10kΩ; RVDPM = KVBUS_DPM × (VBUS_DPM–VBUS_DPM_1) VBUS_DPM_1 Initial voltage for VBUS_DPM threshold setting BAT > VLOWV, VBUS = 5V, RVDPM = 1k to 10kΩ VBUS_DPM_0 VBUS_DPM threshold when VDPM is shorted to VSS BAT > VLOWV, VBUS = 5V, RVDPM < 500Ω IVBUS_DPM Current for programming VBUS_DPM V 3.65 V μA 75 BAT ≤ 3.6V 3.65 3.7 3.75 BAT > 3.6V BAT +0.07 BAT +0.10 BAT +0.145 VTRK Battery voltage tracking threshold for VBUS DPM loop VDPM pin Float (open circuit, RTS > 500kΩ), BAT rising VTRK_HYS Hysteresis for VTRK BAT falling 60 mV VBUS_CHG Input voltage to enable CHG pin, VBUS-VBUS_DPM or VBUS-VTRK EN=LOW, VBUS rising above VIN DPM threshold 80 mV VBUS_CHG_HYS Hysteresis for VBUS_CHG EN=LOW, VBUS falling 160 mV tDGL_CHG Deglitch time for CHG pin status change 5 mS V ISET SHORT CIRCUIT TEST RISET_MAX Highest Resistor value considered a fault (short). Monitored for Iout>90mA Riset: 600 Ω → 250 Ω, Iout latches off. Cycle power to Reset. Fault range >1.10A tDGL-SHORT Deglitch time transition from ISET Short to Iout Disable Clear fault by cycling IN or CHGEN IOUT_CL Maximum OUT current limit regulation (Clamp) 200 250 300 1 0.95 Ω ms 1.4 A mA BATTERY SHORT PROTECTION IBAT(SC) Source current out BAT pin during short-circuit detection BAT(SC) BAT pin short-circuit detection threshold/ Pre-Charge Threshold BAT:3V → 0.5V, no deglitch BAT(SC-HYS) BAT pin Short Hysteresis Recovery → BAT(SC) + BAT(SC-HYS); Rising, no Deglitch 13 17 21 0.75 0.8 0.85 77 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :bq24210 V mV 5 bq24210 SLUSA76A – DECEMBER 2010 – REVISED MAY 2011 www.ti.com ELECTRICAL CHARACTERISTICS Over junction temperature range 0°C ≤ TJ ≤ 125°C, VBUS = 5V, Charge mode (EN = Low) (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT QUIESCENT CURRENT IOUT(DONE) BAT pin current, charging terminated EN=Low, VBUS = 6V, Terminated 9 μA IOUT(STDBY) Suspend current into BAT pin EN=High, VBUS =0V, BAT = 4.2 V 5 μA IBUS(STDBY) Suspend current into VBUS pin EN=High, VBUS ≤ 6V 100 175 μA ICC Active supply current, VBUS pin No load on VTSB pin, EN=Low, VBUS = 6V, no load on BAT pin, BAT > VO(REG), IC enabled 0.8 1.2 mA ICC_REV Active supply current, BAT pin in Load Mode EN = Low, BAT = 4V, no load on VBUS pin 50 80 µA BATTERY CHARGER FAST-CHARGE VO(REG) Battery regulation voltage VBUS = 5.5V, IOUT = 25 mA, (VTS_0C<VTS<VTS_45C) 4.16 4.20 4.23 VO_HT(REG) Battery hot regulation Voltage VBUS = 5.5V, IOUT = 25 mA, (VTS_45C<VTS<VTS_60C) 4.02 4.06 4.1 IOUT Programmed output "fast charge" current range VO(REG) > BAT > VLOWV, VBUS = 5V, RISET = 469 to 7.5kΩ VDO(IN-OUT) Drop-Out, VBUS – BAT Adjust VBUS down until IOUT = 0.5A, BAT = 4.15 V, RISET = 675, TJ <100°C. IOUT Output "fast charge" formula VO(REG) > BAT > VLOWV, VBUS = 5V KISET Fast charge current factor 50 250 V 800 mA 400 mV KISET/RISET A RISET = KISET /IOUT; 250 mA ≤ IOUT < 800 mA 373 390 407 RISET = KISET /IOUT; 50mA ≤ ICHG < 250 mA 375 395 416 RISET = KISET /IOUT; 10 < ICHG < 50 mA 320 400 490 2.4 2.5 2.6 AΩ PRE-CHARGE – INTERNALLY SET VLOWV Pre-charge to fast-charge transition threshold tDGL1(LOWV) Deglitch time on pre-charge to fast-charge transition 100 μs tDGL2(LOWV) Deglitch time on fast-charge to pre-charge transition 32 ms IPRE-CHG Pre-charge current, Internally set BAT < VLOWV, ICHG ≥ 250 mA V 18 20 22 % IOUT 8 10 12 % ICHG TERMINATION – INTERNALLY SET ITERM Termination current, Internally set tDGL(TERM) Deglitch time, termination detected ICHG ≥ 250 mA 29 ms RECHARGE OR REFRESH Recharge detection threshold- normal temp VTS_0C<VTS<VTS_45C, BAT: 4.2V → VRCH VO(REG) –0.120 VO(REG) –0.095 VO(REG) –0.070 V Recharge detection threshold-hot temp VTS_45C<VTS<VTS_60C, BAT: 4.15V → VRCH VO(REG) –0.130 VO(REG) –0.105 VO(REG) –0.80 V tDGL1(RCH) Deglitch time, recharge threshold detected VTS_0C<VTS<VTS_45C, BAT: 4.25V → 3.5V in 1µS ; tDGL(RCH) is time to ISET ramp 29 ms tDGL2(RCH) Deglitch time, recharge threshold in BAT_Detect mode VTS_0C<VTS<VTS_45C, BAT: 3.5V inserted; tDGL(RCH) is time to ISET ramp 3.6 ms VRCH BATTERY DETECTION ROUTINE VREG_BD BAT Reduced regulation during battery detect VTS_0C<VTS<VTS_45C, Battery present VO(REG) –0.45 VO(REG) –0.4 VO(REG) –0.35 VBD_SINK Sink current during VREG_BD VTS_0C<VTS<VTS_45C, Battery present 5 7 9 Regulation time at VREG or VREG_BD VTS_0C<VTS<VTS_45C, Battery present VBD_HI High battery detection threshold VTS_0C<VTS<VTS_45C, Battery present VO(REG) –0.158 VO(REG) –0.108 VO(REG) –0.058 V VBD_LO Low battery detection threshold VTS_0C<VTS<VTS_45C, Battery present VREG_BD +0.05 VREG_BD +0.1 VREG_BD +0.15 V 1700 1940 2250 s 34000 38800 45000 s tDGL1(HI/LOW_RE G) 25 V mA ms BATTERY CHARGING TIMERS AND FAULT TIMERS tPRECHG Pre-charge safety timer value Restarts when entering Pre-charge; Always enabled when in pre-charge. VTS<VSM(TS) tMAXCH Charge safety timer value Clears fault or resets at UVLO, EN disable, BAT Short, exiting LOWV and Refresh 6 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :bq24210 bq24210 SLUSA76A – DECEMBER 2010 – REVISED MAY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over junction temperature range 0°C ≤ TJ ≤ 125°C, VBUS = 5V, Charge mode (EN = Low) (unless otherwise noted) PARAMETER tMAXTERM Termination timer in Limited Power Charge mode TEST CONDITIONS Limited Power Charge mode, terminate charge when VIN DPM active, normal termination conditions met and this termer expires MIN TYP MAX UNIT 6800 7760 9000 s 2 2.2 2.4 V BATTERY-PACK NTC MONITOR VTSB TS Bias Voltage IVTSB (Min) Maximum current from TS-bias pin (short circuit protection) CVTSB Optional capacitance for ESD CTS Optional capacitance for ESD IVTSB < 1 mA Hysteresis on 0C comparator V10C V10C-Hyst Hysteresis on 10C comparator V45C V45C-Hyst Hysteresis on 45C comparator V60C V60C-Hyst Hysteresis on 60C comparator µF 1 %VTSB 46 %VTSB 1 %VTSB 18.6 %VTSB 1 %VTSB 12 %VTSB 1 %VTSB Cold to Normal operation: VTS: 50% → 30% VTSB 12 30 tDGL(TS) Deglitch for TS thresholds: 10/45/60C Battery charging VLP(TS) Limited Power Charge mode threshold Enter VTS: 0.4VTSB → 0.9VTSB; VHYS-LP(TS) Hysteresis exiting Limited Power Charge mode VTS: 1.7V → 0.5V; Deglitch enter Limited Power Charge mode between states µF %VTSB 50 Deglitch for TS thresholds: 10C Deglitch exit Limited Power Charge mode between states 0.1 57 Normal to cold operation: VTS: 30% → 50% VTSB tDGL(TS_10C) tDGL(LDO) mA 0.22 V0C V0C-Hyst 1 75 80 ms ms 85 %VTSB 5 57 ms 8 µs Battery charging THERMAL REGULATION TJ(REG) Temperature regulation limit 125 °C TJ(OFF) Thermal shutdown temperature 155 °C TJ(OFF-HYS) Thermal shutdown hysteresis 20 °C LOGIC LEVELS ON EN VIL Logic LOW input voltage Sink 8 µA VIH Logic HIGH input voltage Source 8 µA IIL Sink current required for LO IIH Source current required for HI 0.4 V 2 10.5 µA 0.8 2 µA 1.4 V LOGIC LEVELS ON CHG AND PG VOL Output LOW voltage ISINK = 5 mA ILEAK Leakage current into IC Vchg = 5 V, VPG = 5 V 0.4 V 1 µA 3.0 3.2 V 200 320 mV –50 0 mV LOAD MODE (EN=LOW) BAT_REV_ST Minimum voltage for Load Mode 2.8 VDO(BAT-VBUS) Drop-Out, V(BAT) – V(VBUS) Adjust VBUS down until I(VBUS) = 0.1A, BAT = 4.15V, TJ <100°C. VBUS-LM Load mode exiting threshold (VBUS above BAT) BAT = 3.6V, VBUS: rising 3V → 4V VHYS-VBUSLM Hysteresis on VBUS-LM falling BAT = 3.6 V, VBUS: 4V → 3V tDGL(LM_Exit) Deglitch time on exiting load mode tDGL(LM-Enter) Deglitch time on VHYS-VBUSLM same as entering load mode ILM_MIN The minimum load current to keep IC in load mode During load mode 0.3 1.8 3.1 mA IREV_LIMIT Initial current limit in load mode for blanking time tREV_LIMIT_BLK BAT = 3.6V 130 170 215 mA –100 150 mV 100 mS 5 µs Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :bq24210 7 bq24210 SLUSA76A – DECEMBER 2010 – REVISED MAY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over junction temperature range 0°C ≤ TJ ≤ 125°C, VBUS = 5V, Charge mode (EN = Low) (unless otherwise noted) PARAMETER tREV_LIMIT_BLK Blanking time for initial current limit IREV_LIMIT_BK Reverse load mode current limit after the initial blanking time tREV_LIMIT_REC Delay time to set load current limit back to IREV_LIMIT 8 TEST CONDITIONS MIN TYP MAX 200 40 Reverse current drops from 100% to 30% of IREV_LIMIT_BK Submit Documentation Feedback 55 200 UNIT ms 70 mA ms Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :bq24210 bq24210 SLUSA76A – DECEMBER 2010 – REVISED MAY 2011 www.ti.com SIMPLIFIED FUNCTION BLOCK DIAGRAM Q1 Q2 VBUS VBAT BAT VBUS + IIN IIN IREV_ LIMIT + Charge Pump VIN_SET + IIN(REG) VOUT(REG) 125 C TJ VBAT + VIN_DPM + Charge Pump VIN_SET VREF VIN_DPM Setting VDPM ISET VOVP OVP Comparator V BUS + VREF EN VTSB IIN _ LIMIT Setting CHARGE CONTROL VTSB Load Mode Comparator V BUS _ LM + VBAT VBUS Sleep Comparator VBUS _ DT VBAT + VBUS PG Power Good Output STATUS OUTPUT Timer Disable CHG TS Input TS VSS Figure 3. Functional Block Diagram Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :bq24210 9 bq24210 SLUSA76A – DECEMBER 2010 – REVISED MAY 2011 www.ti.com DETAILED FUNCTIONAL DESCRIPTION OVERVIEW The bq24210 is a highly integrated 2x3 mm2 single cell Li-Ion charger with bi-directional power flow capability. Depending on the status of control pins and source conditions, the IC can operate in several modes: Sleep, Charge, Load, and Suspend mode. At power up (VBUS or BAT ramps up, or EN pin changes status), the IC performs the operation mode detection automatically. Depending on the VBUS and BAT levels, the IC enters sleep, charge, load, or suspend mode. In charge mode, the charger has three phases of charging: Pre-charge to recondition a full discharged battery, fast-charge constant current to supply the buck charge safely and voltage regulation to safely reach full capacity, as shown in Figure 4. The charge operating mode is very flexible, allowing programming of the fast-charge current, and input voltage regulation threshold. The programmable input voltage regulation threshold makes the IC compatible with many alternative power sources, such as solar panel or inductive charging pad. In Load Mode, the IC connects the battery voltage to the input pin (VBUS pin) through the back to back FET (Q1 and Q2) to power the load connected at VBUS pin. The load current is limited to provide over load protection. In sleep mode, Q2 is OFF and the IC standby current is reduced to ICC_REV. In suspend mode, the IC turns off both Q1 and Q2, and no charging or reverse conduction is allowed. PRECHARGE CC FASTCHARGE CV TAPER VO (REG) Fast Charge IOUT Battery Current Battery Voltage V LOWV CHG = Hi -Z IPRECHG ITERM Figure 4. Charge Profile OPERATION MODE DETECTION AND TRANSITION On power up (VBUS or BAT ramps up, or EN pin changes status), the IC performs operation mode detection to identify the operation mode based on the VBUS voltage, battery voltage, load current, and control pin status. Two comparators are needed for the detection, Load Mode comparator and Sleep Mode comparator. When VBUS falls below the lower limit of the Load Mode comparator, the IC goes to Load Mode; when VBUS is above the upper limit of the Sleep comparator, the IC goes to Charge Mode, as shown in Figure 5. 10 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :bq24210 bq24210 SLUSA76A – DECEMBER 2010 – REVISED MAY 2011 www.ti.com Power UP or EN Pin Change Status EN=Low? No Suspend Mode EN =High Any State Yes Charge Mode Yes VBUS³VBAT +VBUS_DT No Load Mode Yes VBUS£VBAT +VBUS_LM VHYS_VBUSLM ? No Sleep Mode Figure 5. Operation Mode Detection Flow Chart During Load Mode, when VBUS is above upper limit of Load Mode and the load current is below the minimum load current (ILM_MIN), the IC stays in Load Mode for a deglitch time of 100mS and then goes to sleep mode. If VBUS is above the upper limit of the Sleep comparator during this period, after 45µs deglitch time, the IC stops Load Mode and goes into the Charge Mode. The maximum current to the battery is limited by the FET RDSon during this transition. VBAT +199 mV VBAT +350 mV VBUS V BAT -200 mV Charge Current 100 mA IBUS -100 mA <100 mS Load Mode Charge Mode Figure 6. Sleep Comparator Operation Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :bq24210 11 bq24210 SLUSA76A – DECEMBER 2010 – REVISED MAY 2011 www.ti.com During Charge Mode, if VBUS falls to the lower limit of Sleep comparator, the IC goes to Sleep Mode after a deglitch time of 32 mS. If VBUS falls faster than 32 ms to below the lower limit of Load Mode comparator, the IC goes to Load Mode after a deglitch time of 32ms, as shown in Figure 7. SUSPEND EN= High No deglitch EN= Low No deglitch EN= High No deglitch EN= High No deglitch SLEEP VBUS >VBAT +VBUS_DT 45mS deglitch VBUS <VBAT +VBUS _LM -VHYS_ VBUSLM 5uS deglitch VBUS <VBAT +VVBUS_DT -VHYS _VBUSDT 32 mS deglitch VBAT +VVBUS_DT >VBUS >VBAT +VBUS _LM IBUS <ILM _MIN 100 mS deglitch VBUS <VBAT +VBUS _LM 32 mS deglitch LOAD CHARGE VBUS >VBAT +VVBUS_DT 45 mS deglitch Figure 7. Operation Mode Transition Diagram In Load Mode, if the load is higher than ILM_MIN, or the voltage at VBUS pin is lower than upper limit of Load Mode comparator, Load Mode is continuous. If the load is smaller than ILM_MIN in Load Mode, and VBUS is higher than the upper limit, then the IC goes to Sleep Mode after deglitch time of 100mS. In Sleep Mode, once VBUS drops lower than the lower limits of the Load Mode comparator, the IC goes to Load Mode again. In this case, the above process repeats, and IC keeps changing operations mode (between Sleep Mode and Load Mode). The mode change frequency is less than 10Hz, and VBUS has a ripple of 150mV. V BAT -20 mV VBUS VBAT -150 mV V BAT -200 mV -10 mA IBUS -100 mA 100 mS Sleep Mode Sleep Mode Figure 8. Load Mode Operation 12 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :bq24210 bq24210 SLUSA76A – DECEMBER 2010 – REVISED MAY 2011 www.ti.com CHARGE MODE Power-Down or Under-Voltage Lockout (UVLO) The IC is in power down mode if the VBUS and BAT pin voltages are both less than UVLO. The part is considered "dead" and all the pins are high impedance. Once the VBUS voltage rises above the UVLO threshold the IC enters Sleep Mode or an active mode depending on control pin status and the BAT pin (battery) voltage. Power-Up The IC is alive after the VBUS or BAT voltage ramps above UVLO (see Sleep Mode), the IC resets all logic and timers, and starts to perform many of the continuous monitoring routines. Typically the input voltage quickly rises through the UVLO and sleep states where the IC declares power good, starts the safety timer, enables the CHG pin, and starts the normal charge routine. Sleep Mode If the VBUS pin voltage is below the BAT voltage and above the UVLO threshold, the charge current is disabled, the safety timer counting pauses (not reset) and the PG and CHG pins are high impedance. As the input voltage rises and the charger exits Sleep Mode, the PG pin goes low, the safety timer continues to count, charge is enabled, and the CHG pin remains high impedance until current flows out the BAT pin. New Charge Cycle A new charge cycle is started when a good power source is applied, when performing a charge disable/enable (EN), when exiting Limited Power Charge Mode (LPCM), when detecting a battery insertion, or when the BAT voltage dropping below the VRCH threshold. The CHG pin is active low only during the first charge cycle, therefore exiting LPCM or dropping below VRCH will not turn on the CHG pin FET, if the CHG pin is already high impedance. Overvoltage-Protection (OVP) – Continuously Monitored If the input source applies an overvoltage, the pass FET, if previously on, turns off after a deglitch, tBLK(OVP). The timer ends and the CHG and PG pins go to a high impedance state. Once the overvoltage returns to a normal voltage and after a deglitch time of tDGL(PG_OVP) , the PG pin goes low, timer continues, charge continues, and the CHG pin goes low after a 25ms deglitch. Power Good Indication (PG) After a source is applied to VBUS and the voltage rises above the UVLO and sleep thresholds (VBUS>BAT+VBUS-DT) and VIN DPM threshold (VBUS_DPM or VTRK), but is less than OVP (VBUS<VOVP), then the PG FET turns on and provides a low impedance path to ground. The EN pin state does not affect this functionality. CHG Pin Indication The charge pin has an internal open drain FET which is on (pulls down to VSS) during the first charge only (unless TS pin is tied to VTSB pin) and is turned off once the battery reaches voltage regulation and the charge current tapers to the internally set termination threshold. The charge pin is high impedance in Sleep Mode and OVP (if PG is high impedance) and return to its previous state once the condition is removed. Cycling input power, toggling EN pin, or releasing or entering pre-charge mode causes the CHG pin to go low if power is good and a discharged battery is attached. This is considered the start of a first charge cycle. CHG and PG LED Pull-Up Source For host monitoring, a pull-up resistor is used between the STATUS pin and the VCC of the host. For a visual indication a resistor in series with an LED is connected between the STATUS pin and a power source. If the CHG or PG source is capable of exceeding 7V, a 6.2V zener should be used to clamp the voltage. If the source is the BAT pin, note that as the battery changes voltage, the brightness of the LEDs vary. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :bq24210 13 bq24210 SLUSA76A – DECEMBER 2010 – REVISED MAY 2011 www.ti.com CHARGING STATE CHG FET/LED (VTS< VLP(TS)) CHG FET/LED (VTS> VLP(TS)) 1st Charge ON ON OFF OFF Refresh Charge ON OVP Sleep OFF TEMP Fault ON for 1st Charge ON Charge when BAT< BAT(SC) OFF ON INPUT POWER GOOD STATE PG FET/LED Normal Input (BAT+VBUS_DT<VBUS<VOVP) and (VBUSDPM<VBUS<VOVP) ON UVLO OFF Sleep Mode OVP mode PG is independent of chip disable Input Voltage Based Dynamic Power Management (VBUS-DPM) The VBUS-DPM feature is used to detect an input source voltage that is folding reaching its current limit due to excessive load and causing the voltage to reduce.. When the input voltage drops to the VBUS-DPM threshold the internal pass FET reduces the current until there is no further drop in voltage at the input. This prevents a source with voltage less than VBUS-DPM to power the BAT pin. This unique feature makes the IC work well with current limited power sources, such as solar panels or inductive changing pads. This is also an added safety feature that helps protect the source from excessive loads. BAT The charger’s BAT pin provides current to the battery and to the system, if present. This IC can be used to charge the battery plus power the system or charge just the battery assuming the loads do not exceed the available current. The BAT pin is a current limited source and is inherently protected against shorts. If the system load ever exceeds the output programmed current threshold, the output voltage will drop unless there is sufficient capacitance or a charged battery present to supplement the excessive load. VDPM An external resistor is used to program the VBUS_DPM. The programming resistor, RVDPM is dictated by the following equation: RVDPM = (VBUS_DPM – VBUS_DPM_1)/KVBUS_DPM Where: VBUS_DPM is the desired input voltage regulation voltage threshold; VBUS_DPM_1 is the built in offset threshold, typically 3.5V KVBUS_DPM is a gain factor found in the electrical specification. If VDPM pin is shorted to VSS, the VBUS_DPM is set to typically 3.65V. If the VDPM pin is floated (open circuit), the IC operates in Battery Tracking Mode. In this case, VBUS DPM threshold is internally set as VTRK, which is typically BAT+100mV (BAT>3.65V) or 3.75V (BAT≤3.4V). 14 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :bq24210 bq24210 SLUSA76A – DECEMBER 2010 – REVISED MAY 2011 www.ti.com TRACKING vs BAT TRACKING vs TEMPERATURE 4.3 4.2 0.15 IBAT = 18.5mA V(BAT) = 3.8V, IBAT = 18.5mA 4.1 0.14 4.0 3.9 0.13 3.8 Delta - V BAT - V 3.7 3.6 3.5 3.4 0.12 0.11 3.3 0.10 3.2 3.1 0.09 3.0 2.9 2.8 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 4.6 0.08 -50 VBUS - Tracking - V 0 50 100 TA - Free-Air Temperature - °C Figure 9. Figure 10. ISET An external resistor is used to program the output current (50 to 800mA) and can be used as a current monitor. RISET = KISET ÷ IOUT Where: IOUT is the desired fast charge current in amps; KISET is a gain factor found in the electrical specification, typically 395 AΩ The ISET resistor is short protected and will detect a resistance lower than RISET_MAX. The detection requires at least 80mA of output current. If a short is detected, then the IC will latch off and can only be reset by cycling the power. The BAT current is internally clamped to a maximum current IOUT_CL which is independent of the ISET short detection circuitry. Pre-Charge and Termination The termination and pre-charge current are internally set at 10% and 20% of fast charge current I(BAT), respectively. The pre-charge-to-fast-charge, Vlowv threshold is set to 2.5V. TS The TS pin is designed to be compatible with the JEITA temperature standard for Li-Ion batteries. There are four thresholds, 60°C, 45°C, 10°C, and 0°C. Normal operation occurs between 10°C and 45°C. If between 0°C and 10°C, the charge current level is cut in half and if between 45°C and 60°C, the regulation voltage is reduced to 4.1Vmax. The voltage based TS sensing is used due to the flexibility to be compatible with different NTCs. VTSB is used as the voltage reference for TS sensing, and two external TS voltage divider (RT1 and RTH) are used to set the targeted temperature threshold. Above 60°C or below 0°C the charge is disabled. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :bq24210 15 bq24210 SLUSA76A – DECEMBER 2010 – REVISED MAY 2011 www.ti.com Figure 11. Charge JEITA Profile VTSB VTSB LIMITED POWER CHARGE MODE CHARGE SUSPENDED V60C V60C REGULATION VOLTAGE REDUCTION 100mV V45C V45C TEMPERATURE RANGE DURING A CHARGE CYCLE V10C V10C 50% REDUCTION CHARGE CURRENT V0C V0C CHARGE SUSPENDED GND GND Figure 12. TS Pin, Thermister Sense Thresholds Assuming a 103AT NTC thermister on the battery pack as shown in Figure 2, the value RT1 can be determined by using the following equation (select the most critical temperature for the best precision): 1 RT1 = ´ RTH(45C) - RTH(45C) VV45C (1) 16 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :bq24210 bq24210 SLUSA76A – DECEMBER 2010 – REVISED MAY 2011 www.ti.com VTSB RT1 bq24210 TS RTH 103 AT Figure 13. TS Resistor Network The TS pin has another additional feature. When the TS pin is driven high (VTS> VLP(TS)), the IC operates in Limited Power Charge mode. Limited Power Charge Mode – TS Pin High When the TS pin goes high to the Limited Power Charge Mode (LPCM) threshold (VLP(TS)), the part enters Limited Power Charge mode. This mode is used normally for solar charging applications or other high impedance input sources that desire to modify the termination routine and other timers. When entering the Limited Power Charging mode, the pre-charge timer and 10 hour safety timer is held in reset, and the termination routine is modified. A battery detect routine is run to see if the battery was removed or not. If the battery was removed then the CHG pin will go to its high impedance state if not already there. If a battery is detected, the normal charge process begins. If the normal termination conditions are met (Icharge<ITERM, BAT>VRCH) and VBUS_DPM loop is not active, the charging process terminates, and the CHG pin goes to its high impedance state if not already there. When the regular timers are disabled there still is a 2 hour timer if the part is stuck in DPM above 4.1 V but outside of termination conditions at which point charging will terminate and re-start if the voltage falls below 4.1V. When coming out of the Limited Power Charging mode, the battery detect routine is run and if a battery is detected, then a new charge cycle begins and the CHG LED turns on. Limited Power Charge mode is not necessary for all solar charging. A solar panel charging in normal mode without TS pulled high would keep the normal termination timers active and would allow the TS temperature monitoring functions to be used. If Limited Power Charging mode is not desired upon removal of the battery with a thermister, apply a voltage equal to 30% VTSB on TS pin using two external resistors to set a voltage divider and disable the TS monitor function. Timers The pre-charge timer is set to 30 minutes. The pre-charge current is internally set to 20% of the fast charge current. The fast charge timer is fixed at 10 hours and can be increased real time by going into thermal regulation or VBUS_DPM. While in thermal regulation or VBUS_DPM, the timer clock slows by a factor of 2, resulting in a clock than counts half as fast which will increase the total time. If either the 30 minute or ten hour timer times out, the charging is terminated and the CHG pin goes high impedance if not already in that state. The timer is reset by disabling the IC, cycling power, or going into and out of LPCM. Termination Once the BAT pin goes above VRCH (reaches voltage regulation), and the current tapers down to the termination threshold, the CHG pin goes high impedance, and a battery detect route is run to determine if the battery was removed or the battery is full. If the battery is present, the charge current will terminate. If the battery was removed along with the thermister, then the TS pin is driven high and the charger enters LPCM. If the battery was removed and the TS pin is held in the active region, then the battery detect routine will continue until a battery is inserted. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :bq24210 17 bq24210 SLUSA76A – DECEMBER 2010 – REVISED MAY 2011 www.ti.com Battery Detect Routine The battery detect routine checks for a missing battery while keeping the BAT pin at a useable voltage. Whenever the battery is missing, the CHG pin is high impedance. The battery detect routine is run when entering and exiting LPCM to verify if battery is present, or run all the time if battery is missing. On power-up, if battery voltage is greater than VRCH threshold, a battery detect routine is run to determine if a battery is present. Start Battery Detection Start 25ms Timer Timer Expired? No Yes VBAT>VO(REG) 100mV? Yes Battery Present Turn Off Sink Current Return to Flow No SET VBAT Regulation to VREG -400mV Enable Sink Current Reset &Start 25ms Timer Timer Expired? No Yes VBAT>VO( REG)300mV? Yes Battery Present Turn Off Sink Current Return to Flow No Battery Absent CHG FET Off Turn Off Sink Current Return to Flow Figure 14. Battery Detection Flow Chart 18 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :bq24210 bq24210 SLUSA76A – DECEMBER 2010 – REVISED MAY 2011 www.ti.com Refresh Threshold After termination, if the BAT pin voltage drops to VRCH (100mV below regulation) then a new charge is initiated, but the CHG pin remains at a high impedance (off). Starting a Charge on a Full Battery The termination threshold is raised by 14%, for the first minute of a charge cycle so if a full battery is removed and reinserted or a new charge cycle is initiated, that the new charge terminates (less than 1 minute). Batteries that have relaxed many hours may take several minutes to taper to the termination threshold and terminate charge. Load Mode Load Mode is used when the charging source is removed and an external accessory needs power from the battery. To start the Load Mode, the minimum BAT pin voltage is BAT_REV_ST. When Load Mode is active, the oscillator and charge pump will operate at reduced speed to reduce quiescent current prolonging battery life. During Load Mode, reverse current is monitored, and once it rises to an internally set threshold, IREV_LIMIT, the load current regulation loop will limit the load current to the threshold for a blanking time of tREV_LIMIT_BLK. If the over load condition continues after the blanking time of tREV_LIMIT_BLK, the load current limit threshold will be reduced to IREV_LIMIT_BK (about 50mA) and Load Mode continues, until the VBUS drops below UVLO or other failure occurs. If the load current drops below IREV_LIMIT_BK, the load current limit will be set back to IREV_LIMIT after a delay of tREV_LIMIT_REC, as shown in Figure 15. - 50 mA Load Current Limit (I REV_LIMIT ) -150 mA -150 mA Load Current (IBUS) -100 mA -150 mA -50 mA 200 mS -30 mA 200 mS Figure 15. Load Current Limiting Suspend Mode When EN pin is pulled to HIGH level, the IC operates in Suspend Mode, with Q1 and Q2 OFF and very low leakage current into and between VBUS and BAT pins. The PG pin continues to operate to indicate a good power source even while in suspend mode. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :bq24210 19 bq24210 SLUSA76A – DECEMBER 2010 – REVISED MAY 2011 www.ti.com REVISION HISTORY Changes from Original (December 2010) to Revision A Page • Changed from Product Preview to Production Data ............................................................................................................. 1 • Added sentence to last paragraph of Description (continued) .............................................................................................. 2 • Changed VBUS description in PIN FUNCTIONS table ........................................................................................................ 2 • Changed Figure 2 ................................................................................................................................................................. 3 • Added values to the Thermal Information table .................................................................................................................... 4 • Changed titles in Figure 9 and Figure 10 ........................................................................................................................... 15 • Changed paragraph under Load Mode section .................................................................................................................. 19 20 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s) :bq24210 PACKAGE OPTION ADDENDUM www.ti.com 20-May-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) BQ24210DQCR ACTIVE WSON DQC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24210DQCT ACTIVE WSON DQC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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