TI SN74ABTH162260

SN54ABTH162260, SN74ABTH162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS
SCBS240D – JUNE 1992 – REVISED MAY 1997
D
D
D
D
D
D
D
D
D
D
D
SN54ABTH162260 . . . WD PACKAGE
SN74ABTH162260 . . . DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
B-Port Outputs Have Equivalent 25-Ω
Series Resistors, So No External Resistors
Are Required
State-of-the-Art EPIC-ΙΙB  BiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce)
< 1 V at VCC = 5 V, TA = 25°C
High-Impedance State During Power Up
and Power Down
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center
Spacings
OEA
LE1B
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
LE2B
SEL
description
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
OE2B
LEA2B
2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4
LEA1B
OE1B
The ’ABTH162260 are 12-bit to 24-bit multiplexed D-type latches used in applications where two separate data
paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include
multiplexing and/or demultiplexing of address and data information in microprocessor or bus-interface
applications. These devices are also useful in memory-interleaving applications.
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are available for address and/or data transfer. The
output-enable (OE1B, OE2B, and OEA) inputs control the bus-transceiver functions. The OE1B and OE2B
control signals also allow bank control in the A-to-B direction.
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B,
LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the
latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains
latched until the latch-enable input is returned high.
The B-port outputs, which are designed to sink up to 12 mA, include equivalent 25-Ω series resistors to reduce
overshoot and undershoot.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright  1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ABTH162260, SN74ABTH162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS
SCBS240D – JUNE 1992 – REVISED MAY 1997
description (continued)
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABTH162260 is characterized for operation over the full military temperature range of –55°C to
125°C. The SN74ABTH162260 is characterized for operation from –40°C to 85°C.
Function Tables
B TO A (OEB = H)
INPUTS
1B
2B
SEL
LE1B
LE2B
OEA
OUTPUT
A
H
X
H
H
X
L
H
L
X
H
H
X
L
L
X
X
H
L
X
L
X
H
L
X
H
L
A0
H
X
L
L
X
H
L
L
X
X
L
X
L
L
X
X
X
X
X
H
A0
Z
A TO B (OEA = H)
OUTPUTS
INPUTS
2
A
LEA1B
LEA2B
OE1B
OE2B
1B
2B
H
H
H
L
L
H
H
L
H
H
L
L
L
L
H
H
L
L
L
H
L
H
L
L
L
L
2B0
2B0
H
L
H
L
L
L
H
L
L
1B0
1B0
H
L
L
X
L
L
L
L
X
X
X
H
H
1B0
Z
2B0
Z
X
X
X
L
H
Active
Z
X
X
X
H
L
Z
Active
X
X
X
L
L
Active
Active
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ABTH162260, SN74ABTH162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS
SCBS240D – JUNE 1992 – REVISED MAY 1997
logic diagram (positive logic)
LE1B
LE2B
LEA1B
LEA2B
OE2B
OE1B
OEA
SEL
2
27
30
55
56
29
1
28
C1
A1
8
G1
1
23
1D
1B1
1
C1
1D
6
2B1
C1
1D
C1
1D
To 11 Other Channels
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ABTH162260, SN74ABTH162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS
SCBS240D – JUNE 1992 – REVISED MAY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABTH162260 (A port) . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABTH162260 (A port) . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABTH162260
MIN
MAX
4.5
5.5
4.5
5.5
Supply voltage
VIL
VI
Low-level input voltage
IOH
High-level output current
IOL
Low level output current
Low-level
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
TA
Power-up ramp rate
200
Operating free-air temperature
–55
2
2
0.8
Input voltage
0
VCC
–24
0.8
0
VCC
–32
48
64
B port
12
12
Outputs enabled
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
10
10
–40
V
V
V
mA
mA
ns/V
µs/V
200
125
UNIT
V
A port
NOTE 3: Unused control inputs must be held high or low to prevent them from floating.
4
MAX
VCC
VIH
High-level input voltage
SN74ABTH162260
MIN
85
°C
SN54ABTH162260, SN74ABTH162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS
SCBS240D – JUNE 1992 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = –3 mA
VCC = 5 V,
VCC = 4
4.5
5V
VOL
A port
VCC = 4.5 V
B port
MIN
TA = 25°C
TYP†
MAX
II(hold)
I(h ld)
MIN
–1.2
MAX
SN74ABTH162260
MIN
–1.2
MAX
–1.2
2.5
2.5
2.5
IOH = –3 mA
IOH = –24 mA
3
3
3
2
2
IOH = –32 mA
IOL = 48 mA
2*
IOL = 64 mA
IOL = 12 mA
VCC = 0 to 5.5 V,
VI = VCC or GND
A or B ports
VCC = 2.1 V to 5.5 V,
VI = VCC or GND
A or B ports
VCC = 4
4.5
5V
V
V
0.55
0.55*
0.55
0.8
0.8
V
0.8
100
Control
inputs
UNIT
2
0.55
Vhys
II
SN54ABTH162260
mV
±1
±1
±1
±20
±20
±20
µA
VI = 0.8 V
VI = 2 V
100
µA
–100
IOZPU‡
VCC = 0 to 2.1 V,
VO = 0.5 V to 2.7 V, OE = X
±50
±50
±50
µA
IOZPD‡
VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V, OE = X
±50
±50
±50
µA
IOZH§
VCC = 2.1 V to 5.5 V,
VO = 2.7 V, OE ≥ 2 V
10
10
10
µA
IOZL§
VCC = 2.1 V to 5.5 V,
VO = 0.5 V, OE ≥ 2 V
–10
–10
–10
µA
±100
µA
50
µA
–225
mA
Ioff
ICEX
IO¶
Outputs high
VCC = 0,
VCC = 5.5 V,
VI or VO ≤ 4.5 V
VO = 5.5 V
VCC = 5.5 V,
VO = 2.5 V
±100
50
–50
–100
Outputs high
ICC
Outputs low
Outputs
disabled
VCC = 5.5 V, IO = 0,
VI = VCC or GND
∆ICC#
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
Ci
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
Co
–225
50
–50
–225
–50
1.5
1.5
1.5
63
63
63
1
1
1
1
1.5
1
mA
mA
3
pF
11.5
pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
† All typical values are at VCC = 5 V.
‡ This parameter is characterized but not tested.
§ The parameters IOZH and IOZL include the input leakage current.
¶ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
# This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN54ABTH162260, SN74ABTH162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS
SCBS240D – JUNE 1992 – REVISED MAY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°C
MIN
SN54ABTH162260
MAX
MIN
MAX
SN74ABTH162260
MIN
UNIT
MAX
tw
tsu
Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high
3.3
3.3
3.3
ns
Setup time, data before LE1B, LE2B, LEA1B, or LEA2B↓
1.5
1.5
1.5
ns
th
Hold time, data after LE1B, LE2B, LEA1B, or LEA2B↓
1
1
1
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
B
tPLH
tPHL
B
A
tPLH
tPHL
LE
A
tPLH
tPHL
LE
B
tPLH
tPHL
SEL (1B)
A
tPLH
tPHL
SEL (2B)
A
tPZH
tPZL
OE
A
tPZH
tPZL
OE
B
tPHZ
tPLZ
OE
A
tPHZ
tPLZ
OE
B
PARAMETER
VCC = 5 V,
TA = 25°C
SN54ABTH162260
MIN
TYP
MAX
MIN
MAX
MIN
MAX
1.4
3.6
5.2
1.4
6.3
1.4
6.1
2.7
4.8
6.4
2.7
7.4
2.7
7.1
1.6
3.6
5.2
1.6
6.4
1.6
6
1.7
3.8
5.5
1.7
6.5
1.7
6.2
1.8
3.9
5.3
1.8
6.6
1.8
6.3
2.3
4.1
5.4
2.3
6.1
2.3
5.8
1.6
3.7
5.4
1.6
6.4
1.6
6.1
2.8
4.9
6.4
2.8
7.5
2.8
7.1
1.5
3.6
5
1.5
5.9
1.5
5.6
1.8
3.5
4.8
1.8
5.2
1.8
5
1.2
3.6
5.1
1.2
6.5
1.2
6.3
1.7
4
5.5
1.7
6.5
1.7
6.2
1.1
3.5
5.2
1.1
6.5
1.1
6.3
2.1
4.2
5.7
2.1
6.6
2.1
6.5
1
3.4
4.9
1
6.4
1
6.3
2.9
5.5
6.8
2.9
8.3
2.9
8.2
2.5
4.5
5.9
2.5
6.9
2.5
6.7
1.8
3.4
4.8
1.8
5.6
1.8
5.2
2.1
4.4
5.7
2.1
7.7
2.1
7.5
1.7
3.9
5.4
1.7
6.3
1.7
6.2
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
SN74ABTH162260
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SN54ABTH162260, SN74ABTH162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES
WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS
SCBS240D – JUNE 1992 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
7V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
LOAD CIRCUIT
3V
Timing Input
1.5 V
0V
tw
tsu
3V
1.5 V
Input
th
3V
1.5 V
Data Input
1.5 V
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
Input
1.5 V
0V
1.5 V
1.5 V
VOL
tPLH
tPHL
VOH
Output
1.5 V
1.5 V
VOL
1.5 V
0V
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
VOH
Output
1.5 V
tPZL
tPHL
tPLH
3V
Output
Control
1.5 V
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
tPZH
3.5 V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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7
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Copyright  1998, Texas Instruments Incorporated