CIRRUS CS4361_08

Confidential Draft
2/12/08
CS4361
20-Pin, 24-Bit, 192 kHz, 6-Channel D/A Converter
Features
Description
 Multi-Bit Delta-Sigma Modulator
The CS4361 is a complete 6-channel digital-to-analog
output system including interpolation, multi-bit D/A conversion, and output analog filtering in a small 20-pin
package. The CS4361 supports all major audio data interface formats.
 24-Bit Conversion
 Automatically Detects Sample Rates Up To
192 kHz
The CS4361 is based on a fourth-order, multi-bit, deltasigma modulator with a linear analog low-pass filter.
This device also includes auto-speed mode detection
using both sample rate and master clock ratio as a
method of auto-selecting sampling rates between 2 kHz
and 216 kHz.
 103 dB Dynamic Range
 -94 dB THD+N
 Low Clock-Jitter Sensitivity
The CS4361 contains on-chip digital de-emphasis, operates from a single +5 V power supply with separate
built-in level shifter for the digital interface, and requires
minimal support circuitry. These features are ideal for
DVD players and recorders, digital televisions, home
theater and set-top box products, and automotive audio
systems.
 +5 V Core Power
 +1.8 V to +5 V Interface Power
 Filtered Line-Level Outputs
 On-Chip Digital De-emphasis
The CS4361 is available in a 20-pin TSSOP Commercial grade package (-40 to 85° C). The CDB4361 is also
available for device evaluation and implementation suggestions. Please refer to “Ordering Information” on
page 23 for complete ordering information.
 Popguard® Technology
 Mute Output Control
 Small 20-pin TSSOP Package
Serial Audio Port & Control
Supply (1.8 V to 5 V)
Analog & Digital Core
Supply (5 V)
Mode Control
PCM Serial
Audio Input
Level Translator
Digital
De-emphasis
Auto-Speed
Detecting PCM
Serial Interface
6
Digital
Filters
Internal Voltage
Reference
Multi-bit ∆Σ
Modulators
External Mute
Control
+5 Volt-tolerant Reset
http://www.cirrus.com
Switch-Cap
DAC and
Analog Filters
Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
6
Single-Ended
Outputs
(Six Channels
Mute Control
February '08
DS672F1
Confidential Draft
2/12/08
CS4361
TABLE OF CONTENTS
1. PIN DESCRIPTIONS .............................................................................................................................. 4
2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 5
RECOMMENDED OPERATING CONDITIONS .................................................................................... 5
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 5
DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CZZ) ............................................................. 6
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................................ 7
DIGITAL INPUT CHARACTERISTICS .................................................................................................. 8
POWER & THERMAL CHARACTERISTICS ......................................................................................... 8
SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE ...................................................... 9
3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 11
4. APPLICATIONS ................................................................................................................................... 12
4.1 Master Clock .................................................................................................................................. 12
4.2 Serial Clock .................................................................................................................................... 12
4.2.1 External Serial Clock Mode ................................................................................................... 12
4.2.2 Internal Serial Clock Mode .................................................................................................... 12
4.3 De-Emphasis ................................................................................................................................. 14
4.4 Mode Select ................................................................................................................................... 14
4.5 Initialization and Power-Down ........................................................................................................ 15
4.6 Output Transient Control ................................................................................................................ 16
4.6.1 Power-Up .............................................................................................................................. 16
4.6.2 Power-Down .......................................................................................................................... 16
4.7 Grounding and Power Supply Decoupling ..................................................................................... 16
4.8 Analog Output and Filtering ........................................................................................................... 16
4.9 Mute Control .................................................................................................................................. 17
5. PERFORMANCE PLOTS ..................................................................................................................... 18
6. PARAMETER DEFINITIONS ................................................................................................................ 21
7. PACKAGE INFORMATION .................................................................................................................. 22
8. ORDERING INFORMATION ................................................................................................................ 23
9. REVISION HISTORY ............................................................................................................................ 24
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CS4361
LIST OF FIGURES
Figure 1.Equivalent Output Test Load ........................................................................................................ 8
Figure 2.Maximum Loading ......................................................................................................................... 8
Figure 3.External Serial Mode Input Timing .............................................................................................. 10
Figure 4.Internal Serial Mode Input Timing ............................................................................................... 10
Figure 5. Internal Serial Clock Generation ................................................................................................ 10
Figure 6.Recommended Connection Diagram .......................................................................................... 11
Figure 7.CS4361 Data Format (I²S) .......................................................................................................... 13
Figure 8.CS4361 Data Format (Left-Justified) .......................................................................................... 13
Figure 9.CS4361 Data Format (Right-Justified 24) ................................................................................... 13
Figure 10.CS4361 Data Format (Right-Justified 16) ................................................................................. 14
Figure 11.De-Emphasis Curve (Fs = 44.1kHz) ......................................................................................... 14
Figure 12.CS4361 Initialization and Power-Down Sequence ................................................................... 15
Figure 13.Suggested Active-Low Mute Circuit .......................................................................................... 17
Figure 14.Single-Speed Stopband Rejection ............................................................................................ 18
Figure 15.Single-Speed Transition Band .................................................................................................. 18
Figure 16.Single-Speed Transition Band .................................................................................................. 18
Figure 17.Single-Speed Passband Ripple ................................................................................................ 18
Figure 18.Double-Speed Stopband Rejection ........................................................................................... 19
Figure 19.Double-Speed Transition Band ................................................................................................. 19
Figure 20.Double-Speed Transition Band ................................................................................................. 19
Figure 21.Double-Speed Passband Ripple ............................................................................................... 19
Figure 22.Quad-Speed Stopband Rejection ............................................................................................. 20
Figure 23.Quad-Speed Transition Band ................................................................................................... 20
Figure 24.Quad-Speed Transition Band ................................................................................................... 20
Figure 25.Quad-Speed Passband Ripple ................................................................................................. 20
LIST OF TABLES
Table 1. Common Clock Frequencies ...................................................................................................... 12
Table 2. Mode Pin Settings ...................................................................................................................... 14
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CS4361
1. PIN DESCRIPTIONS
VL
1
20
MUTEC
SDIN1
2
19
AOUT1
SDIN2
3
18
AOUT2
SDIN3
4
17
AOUT3
DEM/SCLK
5
16
AOUT4
6
7
8
9
10
15
14
13
12
VA
11
VQ
LRCK
MCLK
RST
MODE
FILT+
Pin Name
#
GND
AOUT5
AOUT6
Pin Description
SDIN1
SDIN2
SDIN3
2
3
4
Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
DEM/SCLK
5
De-emphasis/External Serial Clock Input (Input) - used for de-emphasis filter control or external serial
clock input.
LRCK
6
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial
audio data line.
MCLK
7
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
VQ
11
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
FILT+
10
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling
circuits.
AOUT1
AOUT2
AOUT3
AOUT4
AOUT5
AOUT6
19
18
17
16
13
12
Analog Output (Output) - The full scale analog output level is specified in the Analog Characteristics
specification table.
GND
14
Ground (Input) - ground reference.
VA
15
Analog Power (Input) - Positive power for the analog and core digital sections.
VL
1
Interface Power (Input) - Positive power for the digital interface level shifters.
RST
8
Reset (Input) - Applies reset to the internal circuitry when low.
MUTEC
20
Mute Control (Output) - Control signal for optional external muting circuitry.
MODE
9
Mode Control (Input) - Selects operational modes (see Table 2).
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CS4361
2. CHARACTERISTICS AND SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
AGND = 0 V; all voltages with respect to ground.
Parameters
DC Power Supply
Specified Temperature Range
Commercial (-CZZ)
Symbol
VA
VL
TA
Min
4.75
1.7
-40
Nom
5.0
3.3
-
Max
5.25
5.25
+85
Units
V
V
°C
ABSOLUTE MAXIMUM RATINGS
AGND = 0 V; all voltages with respect to ground.
Parameters
DC Power Supply
Input Current, Any Pin Except Supplies
Digital Input Voltage (pin 8, RST)
Digital Input Voltage (all other digital pins)
Ambient Operating Temperature (power applied)
Storage Temperature
Symbol
VA
VL
Iin
Min
-0.3
-0.3
-
Max
6.0
VA
±10
Units
V
V
mA
VIND
VIND
Top
Tstg
-0.3
-0.3
-55
-65
VA+0.4
VL+0.4
125
150
V
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
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CS4361
DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CZZ)
Test Conditions (unless otherwise specified). VA = 5.0 V, VL = 3.3 V, and TA = 25° C. Full-scale input sine wave.
Measurement Bandwidth is 10 Hz to 20 kHz. See (Note 1). Specifications apply to all channels unless otherwise
indicated.
Parameter
Min
Typ
Max
Unit
99
96
90
87
103
100
96
93
-
dB
dB
dB
dB
-
-93
-90
-94
-80
-40
-92
-89
-93
-73
-33
-86
-83
-87
-76
-36
-85
-82
-86
-67
-27
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Min
Typ
Max
-
100
-
Dynamic Performance
Dynamic Range
18 to 24-Bit
16-Bit
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
A-weighted
unweighted
A-weighted
unweighted
Ch. 1-2, 0 dB
Ch. 3-4, 0 dB
Ch. 5-6, 0 dB
-20 dB
-60 dB
Ch. 1-2, 0 dB
Ch. 3-4, 0 dB
Ch. 5-6, 0 dB
-20 dB
-60 dB
DAC Analog Characteristics - All Modes
Parameter
Symbol
Interchannel Isolation (1 kHz)
dB
DC Accuracy
Interchannel Gain Mismatch
-
0.1
0.25
dB
Gain Drift
-
100
-
ppm/°C
Analog Output
Full Scale Output Voltage
0.60•VA
0.65•VA
0.70•VA
Vpp
VQ
-
0.5•VA
-
VDC
IOUTmax
-
10
-
µA
IQmax
-
100
-
µA
Min AC-Load Resistance (see Figure 2)
RL
-
3
-
kΩ
Max Load Capacitance (see Figure 2)
CL
-
100
-
pF
ZOUT
-
100
-
Ω
Quiescent Voltage
Max DC Current draw from an AOUT pin
Max Current draw from VQ
Output Impedance
Notes:
1. One-half LSB of triangular PDF dither added to data.
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CS4361
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. (See Note 5)
Parameter
Symbol
Min
Typ
Max
Unit
0
0
-
.4780
.4996
Fs
Fs
-.01
-
+.08
dB
.5465
-
-
Fs
Single-Speed Mode
Passband (Note 2)
to -0.05 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
(Note 3)
50
-
-
dB
-
10/Fs
-
s
Fs = 44.1 kHz
-
-
+.05/-.25
dB
to -0.1 dB corner
to -3 dB corner
0
0
-
.4650
.4982
Fs
Fs
-.05
-
+.2
dB
.5770
-
-
Fs
55
-
-
dB
-
5/Fs
-
s
0
0
-
0.397
0.476
Fs
Fs
0
-
+0.00004
dB
Group Delay
De-emphasis Error (Note 4)
tgd
Double-Speed Mode
Passband (Note 2)
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
(Note 3)
Group Delay
tgd
Quad-Speed Mode
Passband (Note 2)
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
(Note 3)
Group Delay
tgd
0.7
-
-
Fs
51
-
-
dB
-
2.5/Fs
-
s
2. Response is clock-dependent and will scale with Fs.
3. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.
For Quad-Speed Mode, the measurement bandwidth is 0.7 Fs to 1 Fs.
4. De-emphasis is available only in Single-Speed Mode.
5. Amplitude vs. Frequency plots of this data are available in “Performance Plots” on page 18.
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CS4361
DIGITAL INPUT CHARACTERISTICS
Parameters
High-Level Input Voltage -all input Pins except RST
Low-Level Input Voltage -all input Pins except RST
High-Level Input Voltage -RST pin (Note 6)
Low-Level Input Voltage -RST pin
Input Leakage Current
Input Capacitance
Symbol
VIH
VIL
VIH
VIL
Iin
(% of VL)
(% of VL)
(% of VL)
(% of VL)
(Note 7)
Min
70%
90%
-
Typ
8
Max
30%
10%
±10
-
Units
V
V
V
V
µA
pF
6. RST pin has an input threshold relative to VL, but is VA tolerant.
7. Iin for LRCK is ±20 µA max.
POWER & THERMAL CHARACTERISTICS
Parameters
5 V Nom
Symbol
Min
Typ
Max
-
66
0.1
300
26
331
1.63
72
60
40
90
1
455
-
Units
Power Supplies
Power Supply Current
(Note 8)
IA
IL
IA
IL
normal operation
power-down state (Note 9)
Power Dissipation
normal operation
power-down state (Note 9)
θJA
(1 kHz) PSRR
(60 Hz)
Package Thermal Resistance
Power Supply Rejection Ratio (Note 10)
mA
mA
µA
µA
mW
mW
°C/Watt
dB
dB
8. Current consumption increases with increasing FS and increasing MCLK. Typ and Max values are
based on highest FS and highest MCLK. Current variance between speed modes is small.
9. Power-Down Mode is defined when all clock and data lines are held static.
10. Valid with the recommended capacitor values on VQ and FILT+ as shown in the typical connection diagram in Section 4.
3.3 µF
V
o ut
AO U Tx
R
L
C
L
AG N D
Capacitive Load -- C L (pF)
125
100
75
25
2.5
3
Figure 1. Equivalent Output Test Load
8
Safe Operating
Region
50
5
10
15
Resistive Load -- RL (kΩ )
Figure 2. Maximum Loading
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CS4361
SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE
Parameters
Symbol
Min
Typ
Max
Units
MCLK Frequency
0.512
-
50
MHz
MCLK Duty Cycle
45
-
55
%
216
54
134
67
34
108
216
216
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
Input Sample Rate
(Note 11)
All MCLK/LRCK ratios combined
256x, 384x, 1024x
256x, 384x
512x, 768x
1152x
128x, 192x
64x, 96x
128x, 192x
Fs
2
2
84
42
30
50
100
168
External SCLK Mode
LRCK Duty Cycle (External SCLK only)
45
50
55
%
SCLK Pulse Width Low
tsclkl
20
-
-
ns
SCLK Pulse Width High
tsclkh
20
-
-
ns
45
50
55
%
SCLK Duty Cycle
SCLK rising to LRCK edge delay
tslrd
20
-
-
ns
SCLK rising to LRCK edge setup time
tslrs
20
-
-
ns
SDIN valid to SCLK rising setup time
tsdlrs
20
-
-
ns
SCLK rising to SDIN hold time
tsdh
20
-
-
ns
-
50
-
%
-
-
ns
-
µs
-
-
ns
-
-
ns
-
-
ns
Internal SCLK Mode
LRCK Duty Cycle (Internal SCLK only)
(Note 12)
SCLK Period
(Note 13)
SCLK rising to LRCK edge
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
MCLK / LRCK =1152, 1024, 512, 256, 128, or 64
SCLK rising to SDIN hold time
MCLK / LRCK = 768, 384, 192, or 96
tsclkw
10 9
---------------SCLK
tsclkr
-
tsdlrs
10 9
---------------------- + 10
( 512 )Fs
tsdh
tsdh
tsclkw
-----------------2
10 9
---------------------- + 15
( 512 )Fs
10 9
---------------------- + 15
( 384 )Fs
11. Not all sample rates are supported for all clock ratios. See table “Common Clock Frequencies” on
page 12 for supported ratios and frequencies.
12. In Internal SCLK Mode, the duty cycle must be 50% ± 1/2 MCLK period.
13. The SCLK / LRCK ratio may be either 32, 48, 64, or 72. This ratio depends on data format and
MCLK/LRCK ratio. (See Figures 7-10)
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CS4361
LRCK
t sclkh
t slrs
t slrd
t sclkl
SCLK
t sdh
t sdlrs
SDATA
Figure 3. External Serial Mode Input Timing
LR C K
t s clkr
S D A TA
t sclkw
t sdlrs
t sdh
*IN TE R N AL S C L K
Figure 4. Internal Serial Mode Input Timing
* The SCLK pulses shown are internal to the CS4361.
LRCK
MCLK
1
N
2
*INTERNAL SCLK
SDATA
Figure 5. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS4361.
N equals MCLK divided by SCLK
10
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CS4361
3. TYPICAL CONNECTION DIAGRAM
+1.8 V to +5 V
+5 V
+
15
1
3
Audio
Data
Processor
4
5
6
1 µF
VA
VL
2
0.1 µF
Note*
SDIN1
AOUT1
AOUT2
AOUT3
AOUT4
AOUT5
AOUT6
SDIN2
SDIN3
DEM/SCLK
LRCK
MUTEC
19
18
17
16
13
12
3.3 µF
470Ω
Audio Output
+
C
10 kΩ
Optional
Muting
Circuit
Rext
20
CS4361
Rext + 470
For best 20 kHz response
4πFs(Rext 470)
Note* = This circuitry is intended for applications where the CS4361 connects
directly to an unbalanced output of the design. For internal routing
applications please see the DAC analog output characteristics for loading
limitations.
C=
External Clock
µControler
7
8
MCLK
RST
FILT+
10
+
33 µF
VL I2S
LRCK
MCLK
RJ24
MODE
GND
14
GND LJ
VQ
11
+
RJ16
9
0.1 µF
*3.3 µF
or
*10 µF
*Popguard ramp can be adjusted by selecting
this capacitor value to be 3.3 µF to give 250 ms
ramp time or 10 µF to give a 420 ms ramp time.
Figure 6. Recommended Connection Diagram
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CS4361
4. APPLICATIONS
The CS4361 accepts data at standard audio sample rates including 48, 44.1 and 32 kHz in SSM, 96, 88.2 and
64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via the serial data input pin (SDIN). The
Left/Right Clock (LRCK) determines which channel is currently being input on SDIN, and the optional Serial Clock
(SCLK) clocks audio data into the input data buffer.
4.1
Master Clock
MCLK/LRCK must be an integer ratio as shown in Table 1. The LRCK frequency is equal to Fs, the frequency at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio and speed
mode is detected automatically during the initialization sequence by counting the number of MCLK transitions during a single LRCK period and by detecting the absolute speed of MCLK. Internal dividers are set
to generate the proper clocks. Table 1 illustrates several standard audio sample rates and the required
MCLK and LRCK frequencies. Please note there is no required phase relationship, but MCLK, LRCK, and
SCLK must be synchronous.
LRCK
(kHz)
32
44.1
48
64
88.2
96
128
176.4
192
Mode
64x
8.1920
11.2896
12.2880
96x
128x
8.1920
11.2896
12.2880
12.2880
16.9344 22.5792
18.4320 24.5760
QSM
192x
12.2880
16.9344
18.4320
33.8680
36.8640
MCLK (MHz)
256x
384x
8.1920 12.2880
11.2896 16.9344
12.2880 18.4320
22.5792 33.8680
24.5760 36.8640
32.7680 49.1520
DSM
512x
22.5792
24.5760
32.7680
-
768x
1024x
32.7680
33.8680 45.1580
36.8640 49.1520
49.1520
SSM
1152x
36.8640
-
Table 1. Common Clock Frequencies
4.2
Serial Clock
The serial clock controls the shifting of data into the input data buffers. The CS4361 supports both external
and internal serial clock generation modes. Refer to Figures 7-10 for data formats.
4.2.1
External Serial Clock Mode
The CS4361 will enter the External Serial Clock Mode when 16 low-to-high transitions are detected on
the DEM/SCLK pin during any phase of the LRCK period. When this mode is enabled, the Internal Serial
Clock Mode and de-emphasis filter cannot be accessed. The CS4361 will switch to Internal Serial Clock
Mode if no low-to-high transitions are detected on the DEM/SCLK pin for two consecutive frames of
LRCK. Refer to Figure 12.
4.2.2
Internal Serial Clock Mode
In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK and
LRCK. The SCLK/LRCK frequency ratio is either 32, 48, 64, or 72 depending upon data format. Operation
in this mode is identical to operation with an external serial clock synchronized with LRCK. This mode allows access to the digital de-emphasis function. Refer to Figures 7 - 12 for details.
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CS4361
Left C ha nn el
LR C K
R ig h t C ha n ne l
SCLK
SDATA
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4 -5
MSB -1 -2 -3 -4
Internal SCLK Mode
+5 +4 +3 +2 +1 LSB
External SCLK Mode
I²S, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
I²S, 16-Bit data and INT SCLK = 32 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
I²S, Up to 24-Bit data and INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
I²S, Up to 24-Bit data and INT SCLK = 72 Fs if
MCLK/LRCK = 1152
Figure 7. CS4361 Data Format (I²S)
Left C ha nn el
LR C K
R ig h t C ha n ne l
SCLK
SDATA
+5 +4 +3 +2 +1 LS B
M SB -1 -2 -3 -4 -5
M SB -1 -2 -3 -4
Internal SCLK Mode
+5 +4 +3 +2 +1 LS B
External SCLK Mode
Left-Justified, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Left-Justified, up to 24-Bit Data
INT SCLK = 64 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
Figure 8. CS4361 Data Format (Left-Justified)
LR C K
R ig ht C h an nel
Left C ha nn el
SCLK
SDATA
0
23 22 21 20 19 18
7
32 clocks
Internal SCLK Mode
Right-Justified, 24-Bit Data
INT SCLK = 64 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
6
5
4
3
2
1
0
23 22 21 20 19 18
7
6
5
4
3
2
1
0
External SCLK Mode
Right-Justified, 24-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 48 Cycles per LRCK Period
Figure 9. CS4361 Data Format (Right-Justified 24)
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LR CK
CS4361
R ig ht C h a n ne l
L e ft C h a nn e l
SCLK
SDATA
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
Internal32SCLK
Mode
clocks
9
8
7
6
5
4
3
2
1
0
External SCLK Mode
Right-Justified, 16-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 32 Cycles per LRCK Period
Right-Justified, 16-Bit Data
INT SCLK = 32 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
Figure 10. CS4361 Data Format (Right-Justified 16)
4.3
De-Emphasis
The CS4361 includes on-chip digital de-emphasis. Figure 11 shows the de-emphasis curve for Fs equal to
44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. The de-emphasis filter is active (inactive) if the DEM/SCLK pin is low (high) for five consecutive
falling edges of LRCK. This function is available only in the internal Serial Clock Mode when LRCK < 50 kHz.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 11. De-Emphasis Curve (Fs = 44.1kHz)
4.4
Mode Select
Mode selection is determined by the Mode Select pin. The value of this pin is locked 1024 LRCK cycles after
RST is released. This pin requires a specific connection to supply, ground, MCLK, or LRCK as outlined in
Table 2.
Mode pin is:
Tied to VL
Tied to GND
Tied to LRCK
Tied to MCLK
Mode
I²S
Left-Justified
Right-Justified - 24 bit
Right-Justified - 16bit
Table 2. Mode Pin Settings
14
Figure
7
8
9
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4.5
CS4361
Initialization and Power-Down
The initialization and power-down sequence flow chart is shown in Figure 12. The CS4361 enters the power-down state upon initial power-up. The interpolation filters and delta-sigma modulators are reset, and the
internal voltage reference, multi-bit digital-to-analog converters, and switched-capacitor low-pass filters are
powered down. The device will remain in the Power-Down Mode until RST is released and MCLK and LRCK
are present. Once MCLK and LRCK are detected, MCLK occurrences are counted over one LRCK period
to determine the MCLK/LRCK frequency ratio. Power is then applied to the internal voltage reference. Finally, power is applied to the D/A converters and switched-capacitor filters, and the analog outputs will ramp to
the quiescent voltage, VQ.
USER: Apply Power
VQ and outputs
ramp down
Power-Down State
VQ and outputs
ramp down
VQ and outputs low
USER: Apply MCLK, release RST
USER: Apply RST
or remove MCLK
USER: Apply RST
or remove MCLK
VQ and outputs ramp up
USER: Remove
LRCK
USER: Remove
LRCK
Wait State
USER: Apply LRCK and MCLK
USER: change
MCLK/LRCK ratio
MCLK/LRCK Ratio Detection
USER: change
MCLK/LRCK ratio
USER: No SCLK
USER: Applied SCLK
SCLK mode = internal
SCLK mode = external
Normal Operation
De-emphasis
available
Normal Operation
De-emphasis
not available
Analog Output
is Generated
Analog Output
is Generated
Figure 12. CS4361 Initialization and Power-Down Sequence
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4.6
CS4361
Output Transient Control
The CS4361 uses Popguard technology to minimize the effects of output transients during power-up and
power-down. When implemented with external DC-blocking capacitors connected in series with the audio
outputs, this feature eliminates the audio transients commonly produced by single-ended, single-supply
converters. To make the best use of this feature, it is necessary to understand its operation.
4.6.1
Power-Up
When the device is initially powered up, the audio outputs, AOUT1-6, are clamped to VQ, which is initially
low. After RST is released and MCLK is applied, the outputs begin to ramp with VQ towards the nominal
quiescent voltage. This ramp takes approximately 200 ms to complete. The gradual voltage ramping allows time for the external DC-blocking capacitors to charge to VQ, effectively blocking the quiescent DC
voltage. Audio output begins approximately 2000 sample periods after valid LRCK and SDIN are supplied
(and SCLK, if used).
4.6.2
Power-Down
To prevent audio transients at power-down, the DC-blocking capacitors must fully discharge before turning off the power. In order to do this, either stop MCLK or hold RST low for a period of about 250 ms before
removing power. During this time, voltage on VQ and the audio outputs discharge gradually to GND. If
power is removed before this 250 ms time period has passed, a transient will occur when the VA supply
drops below that of VQ. There is no minimum time for a power cycle; power may be reapplied at any time.
When changing clock ratio or sample rate, it is recommended that zero data (or near zero data) be present
on SDIN for at least 10 LRCK samples before the change is made. During the clocking change, the DAC
outputs will always be in a zero data state. If non-zero audio is present at the time of switching, a slight
click or pop may be heard as the DAC output automatically goes to its zero data state.
4.7
Grounding and Power Supply Decoupling
As with any high-resolution converter, the CS4361 requires careful attention to power supply and grounding
arrangements to optimize performance. Figure 6 shows the recommended power arrangement, with VA
connected to a clean +5 V supply. For best performance, decoupling and filter capacitors should be located
as close to the device package as possible, with the smallest capacitors placed closest.
4.8
Analog Output and Filtering
The analog filter present in the CS4361 is a switched-capacitor filter followed by a continuous-time, lowpass filter. Its response, combined with that of the digital interpolator, is given in Figures 14 - 21. The recommended external analog circuitry is shown in the “Typical Connection Diagram” on page 11.
The analog outputs are named AOUT1-6. The SDIN1 feeds AOUT1 as the ‘Left’ marked data and AOUT2
as the ‘Right’ marked data. The SDIN2 feeds AOUT3 as the ‘Left’ marked data and AOUT4 as the ‘Right’
marked data. The SDIN3 feeds AOUT5 as the ‘Left’ marked data and AOUT6 as the ‘Right’ marked data.
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4.9
CS4361
Mute Control
The MUTEC pin is intended to be used as control for an external mute circuit in order to add off-chip mute
capability.
This pin becomes active under the following conditions:
1. During power-up initialization
2. Upon reset
3. If the MCLK to LRCK ratio is incorrect
4. Upon receipt of 512 consecutive samples of zero
5. During power-down
The MUTEC pin will only go active on static zero data only if all 6 channels satisfy the 512 sample requirement. If any channel receives non-zero data, the mute pin will return low (inactive).
Use of the mute control function is not mandatory but is recommended for designs requiring the absolute
minimum in extraneous clicks and pops. Also, use of the mute control function can enable the system designer to achieve idle channel noise and signal-to-noise ratios that are only limited by the external mute circuit. The MUTEC pin is an active-high CMOS driver. See Figure 13 below for a suggested active-high mute
circuit.
AC
Couple
470 Ω
A udio
O ut
AO UT
6
10 kΩ
Filter
Cap
47 kΩ
C S 4361
+V A
MMU N 2111LT1
2 kΩ
MU TE C
6
10 kΩ
(Low R on)
MMU N 2211LT1
-V
(if a va ila ble )
Figure 13. Suggested Active-Low Mute Circuit
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CS4361
5. PERFORMANCE PLOTS
18
Figure 14. Single-Speed Stopband Rejection
Figure 15. Single-Speed Transition Band
Figure 16. Single-Speed Transition Band
Figure 17. Single-Speed Passband Ripple
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Figure 18. Double-Speed Stopband Rejection
Figure 20. Double-Speed Transition Band
CS4361
Figure 19. Double-Speed Transition Band
Figure 21. Double-Speed Passband Ripple
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0
CS4361
0
-10
-10
-20
-30
-20
Amplitude (dB)
Amplitude (dB)
-40
-50
-60
-30
-40
-70
-50
-80
-60
-90
-100
0
0.1
0.2
0.3
0.4
0.5
0.6
Frequency(normalized to Fs)
0.7
0.8
0.9
1
0.35
Figure 22. Quad-Speed Stopband Rejection
0.4
0.45
0.5
0.55
0.6
Frequency(normalized to Fs)
0.65
0.7
0.75
Figure 23. Quad-Speed Transition Band
0
0.2
-5
0.15
-10
0.1
0.05
-20
Amplitude (dB)
Amplitude (dB)
-15
-25
-30
0
-0.05
-35
-0.1
-40
-0.15
-45
-0.2
-50
0.4
0.45
0.5
0.55
0.6
Frequency(normalized to Fs)
0.65
Figure 24. Quad-Speed Transition Band
20
0.7
0.05
0.1
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
Figure 25. Quad-Speed Passband Ripple
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CS4361
6. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made
with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full
scale. This technique ensures that the distortion components are below the noise level and do not effect the
measurement. This measurement technique has been accepted by the Audio Engineering Society, AES171991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
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CS4361
7. PACKAGE INFORMATION
20L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11
A2
E
A
∝
e
b2
SIDE VIEW
A1
END VIEW
L
SEATING
PLANE
1 2 3
TOP VIEW
DIM
MIN
INCHES
NOM
A
A1
A2
b
D
E
E1
e
L
µ
-0.002
0.03346
0.00748
0.252
0.248
0.169
-0.020
0°
-0.004
0.0354
0.0096
0.256
0.2519
0.1732
-0.024
4°
MAX
0.043
0.006
0.037
0.012
0.259
0.256
0.177
0.026
0.028
8°
MIN
MILLIMETERS
NOM
NOTE
MAX
-0.05
0.85
0.19
6.40
6.30
4.30
-0.50
0°
--0.90
0.245
6.50
6.40
4.40
-0.60
4°
1.10
0.15
0.95
0.30
6.60
6.50
4.50
0.65
0.70
8°
2,3
1
1
JEDEC #: MO-153
Controlling Dimension is Millimeters.
Notes:
1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
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CS4361
8. ORDERING INFORMATION
Product
CS4361
CDB4361
Description
Package Pb-Free
20-pin, 24-bit,
20-Plastic
192 kHz, 6-channel
TSSOP
D/A Converter
CS4361 Evaluation Board
Grade
Temp Range
Container
Order #
Yes
Commercial
-40 to 85° C
Tube
CS4361-CZZ
-
-
-
-
CDB4361
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CS4361
9. REVISION HISTORY
Release
Changes
A1
Initial Release.
A2
Correction to PDF file size.
F1
Removed VA = 3.3 V operation.
Updated Typ and Max THD+N and Dynamic Range specs in “DAC Analog Characteristics - Commercial (CZZ)” on page 6.
Corrected “Output Transient Control” on page 16 and “CS4361 Initialization and Power-Down Sequence”
on page 15 to show ramp down when MCLK is removed.
Corrected MUTEC description “512 LRCK cycles” in “Mute Control” on page 17.
Removed -DZZ ordering option.
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY
INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be
trademarks or service marks of their respective owners.
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