CS5466
Low-cost Power/Energy IC with Pulse Output
Features
Description
z Single-chip
Power Measurement Solution
z Energy Data Linearity:
±0.1% of Reading, over 1000:1 Dynamic Range
z On-chip
functions: Measures Power and
Performs Energy-to-pulse Conversions
z Meets Accuracy Spec for IEC, ANSI, & JIS.
z High-pass Filter Option
z Four Input Ranges for Current Channel
z On-chip, 2.5 V Reference
z Pulse Outputs for Stepper Motor or
Mechanical Counter
z On-chip Energy Direction Indicator
z Ground-referenced Input Signals with Single
Supply
z High-frequency Output for Calibration
z On-chip, Power-on Reset (POR)
z Power Supply Configurations:
VA+ = +5 V; AGND = 0 V; VD+ = +3.3 V to 5 V
The CS5466 is a low-cost power meter solution incorporating dual delta-sigma (∆Σ) analog-to-digital converters
(ADCs), an energy-to-frequency converter, and energy
pulse outputs on a single chip. The CS5466 is designed
to accurately measure and calculate energy for single
phase, 2- or 3-wire power metering applications with
minimal external components.
The low-frequency pulse outputs, E1 and E2, provide
pulses at a frequency which is proprtional to the active
power and can be used to drive a stepper motor or a mechanical counter. Energy direction output, NEG,
indicates when pulse outputs E1 and E2 represent negative active power. The high-frequency pulse output
FOUT is designed to assist in system calibration.
The CS5466 has configuration pins which allow for direct
configuration of pulse output frequency, current channel
input range, and high-pass filter enable option.
The CS5466 also has a power-on reset function which
holds the part in reset until the supply reaches an operable level.
ORDERING INFORMATION
See page 16.
I
VA+
IIN+
IIN-
PGA
RESET
4th Order ∆Σ
Modulator
Digital
Filter
VD+
HPF
Option
FOUT
Energy-toFrequency
Conversion
E1
E2
NEG
VREFIN
HPF
x1
FREQ0
Config
VIN+
VIN-
VREFOUT
http://www.cirrus.com
x10
2nd Order ∆Σ
Modulator
Digital
Filter
HPF
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
FREQ2
IGAIN0
Option
2.5V On-Chip
Reference
FREQ1
IGAIN1
Clock
Generator
CPUCLK
XOUT
XIN
AUG ‘05
DS659F1
CS5466
TABLE OF CONTENTS
1. OVERVIEW ............................................................................................................................... 3
2. PIN DESCRIPTION ................................................................................................................... 4
3. CHARACTERISTICS & SPECIFICATIONS ............................................................................. 5
RECOMMENDED OPERATING CONDITIONS ....................................................................... 5
ANALOG CHARACTERISTICS ................................................................................................ 5
VOLTAGE REFERENCE ......................................................................................................... 6
DIGITAL CHARACTERISTICS ................................................................................................. 7
SWITCHING CHARACTERISTICS .......................................................................................... 8
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 9
4. THEORY OF OPERATION ..................................................................................................... 10
4.1 Digital Filters .................................................................................................................... 10
4.2 Active Power Computation ............................................................................................... 10
5. FUNCTIONAL DESCRIPTION ............................................................................................... 11
5.1 Analog Inputs ................................................................................................................... 11
5.1.1 Voltage Channel .................................................................................................. 11
5.1.2 Current Channel .................................................................................................. 11
5.2 High-pass Filter ................................................................................................................ 11
5.3 Energy Pulse Outputs ...................................................................................................... 11
5.3.1 Pulse Output Format. .......................................................................................... 11
5.3.2 Selecting Frequency of E1 and E2 ...................................................................... 11
5.3.3 Selecting Frequency of FOUT ............................................................................. 12
5.3.4 Absolute Max Frequency on E1 and E2 .............................................................. 12
5.3.5 E1 and E2 Frequency Calculation ....................................................................... 13
5.4 Energy Direction Indicator ............................................................................................... 13
5.5 Power-on Reset ............................................................................................................... 13
5.6 Oscillator Characteristics ................................................................................................. 13
5.7 Basic Application Circuit .................................................................................................. 14
6. PACKAGE DIMENSIONS ....................................................................................................... 15
7. REVISION HISTORY................................................................................................................ 16
LIST OF FIGURES
Figure 1. Timing Diagram for E1, E2 and FOUT (Not to Scale) ...................................................... 8
Figure 2. Data Flow ....................................................................................................................... 10
Figure 3. Oscillator Connection ..................................................................................................... 13
Figure 4. Typical Connection Diagram .......................................................................................... 14
LIST OF TABLES
Table 1. Current Channel PGA Setting ......................................................................................... 11
Table 2. Maximum Frequency for E1, E2, and FOUT ................................................................... 12
Table 3. Absolute Max Frequency on E1 and E2.......................................................................... 12
2
DS659F1
CS5466
1. OVERVIEW
The CS5466 is a CMOS monolithic power measurement device with an energy computation engine. The CS5466
combines a programmable gain amplifier, two ∆Σ ADCs, and energy-to-frequency conversion circuitry on a single
chip.
The CS5466 is designed for energy measurement applications and is optimized to interface to a shunt or current
transformer for current measurement, and to a resistive divider or transformer for voltage measurement. The current
channel has a programmable gain amplifier (PGA) which provides four full-scale input options. With a single +5 V
supply on VA+/AGND, both of the CS5466’s input channels accommodate common-mode plus signal levels between (AGND - 0.25 V) and VA+.
The CS5466 has three pulse output pins: E1, E2, and FOUT. E1 and E2 can be used to directly drive a mechanical
counter or stepper motor, or interface to a microcontroller. The FOUT pin conveys active (real) power at a pulse frequency many times higher than that of the E1 or E2 pulse frequency, allowing for high-speed calibration.
DS659F1
3
CS5466
2.
PIN DESCRIPTION
Crystal Out
CPU Clock Output
Positive Power Supply
Digital Ground
Gain Select 0
Negative Energy Indicator
Gain Select 1
High-pass Filter Enable
Differential Voltage Input
Differential Voltage Input
Voltage Reference Output
Voltage Reference Input
XOUT
CPUCLK
VD+
DGND
IGAIN0
NEG
IGAIN1
HPF
VIN+
VINVREFOUT
VREFIN
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
XIN
FREQ0
E1
E2
FREQ1
RESET
FOUT
FREQ2
IIN+
IINVA+
AGND
Crystal In
Frequency Select 0
Energy Output 1
Energy Output 2
Frequency Select 1
Reset
High-frequency Output
Frequency Select 2
Differential Current Input
Differential Current Input
Positive Analog Supply
Analog Ground
Clock Generator
Crystal Out
Crystal In
CPU Clock Output
1, 24
2
XOUT, XIN - A single stage amplifier inside the chip is connected to these pins and can be used
with a crystal to provide the system clock for the device. Alternatively, an external clock can be
supplied to the XIN pin to provide the system clock for the device.
CPUCLK - Output of on-chip oscillator which can drive one standard CMOS load.
Control Pins
Gain Select
Frequency Select
5, 7
IGAIN1, IGAIN0 - Used to select the current channel input gain range.
17, 20, 23 FREQ2,FREQ1,FREQ0 - Used to select max pulse output frequency for E1, E2, and FOUT.
High Pass Filter Enable
8
Reset
19
HPF - High disables the HPF. Low activates HPF on Voltage channel. Connecting HPF pin to
FOUT pin activates HPF on Current channel.
RESET - Low activates Reset.
Energy Pulse Outputs
Energy Output
22, 21
E1, E2 - Active low alternating pulses with an output frequency that is proportional to the active
(real) power.
High Freq Output
18
FOUT - Outputs energy pulses at a frequency higher than E1 and E2 outputs. Used for calibration purposes.
Neg Energy Indicator
6
NEG - High indicates negative energy.
Analog Inputs/Outputs
Differential Voltage Inputs
9, 10
VIN+, VIN- - Differential analog input pins for voltage channel.
Voltage Reference
Output
11
VREFOUT - The on-chip voltage reference output pin. The voltage reference has a nominal
magnitude of 2.5 V and is referenced to the AGND pin on the converter.
Voltage Reference Input
12
VREFIN - Voltage input to this pin establishes the voltage reference for the on-chip modulators.
Differential Current Inputs
16, 15
IIN+, IIN- - Differential analog input pins for current channel.
Power Supply Connections
Positive Digital Supply
3
VD+ - The positive digital supply.
Digital Ground
4
DGND - Digital Ground.
Analog Ground
13
AGND - Analog Ground.
Positive Analog Supply
14
VA+ - The positive analog supply.
4
DS659F1
CS5466
3. CHARACTERISTICS & SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
Positive Digital Power Supply
VD+
3.135
5.0
5.25
V
Positive Analog Power Supply
VA+
4.75
5.0
5.25
V
VREFIN
-
2.5
-
V
TA
-40
-
+85
°C
Voltage Reference
Specified Temperature Range
ANALOG CHARACTERISTICS
•
•
•
Min / Max characteristics and specifications are guaranteed over all operating ponditions.
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
•
MCLK = 4.096 MHz
Parameter
Symbol
Min
Typ
Max
Unit
(Gain = 10)
(Gain = 50)
(Gain = 100)
(Gain = 150)
IIN
-
±250
±50
±25
±16.7
-
mV
mV
mV
mV
Input Capacitance
(All Gain Ranges)
CinI
-
25
-
pF
Effective Input Impedance
(All Gain Ranges)
ZinI
30
-
-
kΩ
Analog Inputs (Current Channel)
Differential Input Range
[(IIN+)-(IIN-)]
Analog Inputs (Voltage Channel)
Differential Input Range
[(VIN+)-(VIN-)]
VIN
-
-
±250
mV
Input Capacitance
CinV
-
0.2
-
pF
Effective Input Impedance
ZinV
2
-
-
MΩ
Accuracy (Energy Outputs)
Active Energy Linearity
(Note 1)
All Gain ranges
Input Range 0.1% - 100%
-
-
±0.1
-
%
Full-scale Error
(Note 2)
-
-
4.0
-
%FS
Offset Error
(Note 2)
-
-
0.06
-
%FS
Notes: 1. Applies when the HPF option is enabled
2.
DS659F1
Applies before system calibration. Specified as a percentage of full scale (FS).
5
CS5466
ANALOG CHARACTERISTICS (Continued)
Parameter
Symbol
Min
Typ
Max
Unit
IA+
ID+ (VA+ = VD+ = 5 V)
ID+ (VA+ = 5 V, VD+ = 3.3 V)
-
-
1.3
2.9
1.7
-
mA
mA
mA
(VA+ = VD+ = 5 V)
(VA+ = 5 V, VD+ = 3.3 V)
-
-
21
11.6
25
-
mW
mW
PSRR
45
56
55
75
-
dB
dB
Power Supplies
Power Supply Currents
Power Consumption
(Note 3)
Power Supply Rejection Ratio
(50, 60 Hz)
(Note 4)
Voltage Channel (Gain = 10)
Current Channel (All Gains)
Notes: 3. All outputs unloaded. All inputs CMOS level.
4.
Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV zero-to-peak sine wave (frequency =
60 Hz) is imposed onto the +5 V supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input
channels are shorted to VA-. Then the CS5466 is put into an internal test mode and digital output data is collected
for the channel under test. The zero-peak value of the digital sinusoidal output signal is determined, and this value
is converted into the zero-peak value of the sinusoidal voltage that would need to be applied at the channel’s inputs,
in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is then (in dB):
⎧ 0.150V ⎫
PSRR = 20 ⋅ log ⎨ ------------------ ⎬
⎩ V eq ⎭
VOLTAGE REFERENCE
Parameter
Symbol
Min
Typ
Max
Unit
Reference Output
Output Voltage
REFOUT
+2.4
+2.5
+2.6
V
VREFOUT Temperature Coefficient
(Note 5)
TCVREF
-
25
60
ppm/°C
Load Regulation
(Note 6)
∆VR
-
6
10
mV
Reference Input
Input Voltage Range
VREFIN
-
+2.5
-
V
Input Capacitance
-
-
4
-
pF
Input CVF Current
-
-
70
-
nA
Notes: 5. The voltage at VREFOUT is measured across the temperature range. From these measurements the following
formula is used to calculate the VREFOUT Temperature Coefficient:.
AVG
MIN)
(
6
MAX
(T
AMAX
1
- TAMIN
(
6.
- VREFOUT
( (VREFOUT
VREFOUT
( 1.0 x 10
6
(
TCVREF =
Specified at maximum recommended output current of 1 µA, source or sink.
DS659F1
CS5466
DIGITAL CHARACTERISTICS
•
•
•
•
(Note 7)
Min / Max characteristics and specifications are guaranteed over all operating conditions.
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
MCLK = 4.096 MHz
Parameter
Symbol
Min
Typ
Max
Unit
MCLK
3
4.096
5
MHz
-
40
-
60
%
(Note 8 and 9)
-
40
-
60
%
-3 dB
-
-
0.125
-
Hz
(VD+) - 0.5
0.8 VD+
-
-
V
V
-
-
1.5
0.2 VD+
V
V
-
-
0.3
0.2 VD+
V
V
Master Clock Characteristics
Master Clock Frequency
Internal Gate Oscillator
Master Clock Duty Cycle
CPUCLK Duty Cycle
Filter Characteristics
High-pass Filter Corner Frequency
Input/Output Characteristics
High-level Input Voltage
XIN
RESET
Low-level Input Voltage (VD = 5 V)
XIN
RESET
Low-level Input Voltage (VD = 3.3 V)
XIN
RESET
VIH
VIL
VIL
High-level Output Voltage (except XOUT)
Iout = +5 mA
VOH
(VD+) - 1.0
-
-
V
Low-level Output Voltage (except XOUT)
Iout = -5 mA
VOL
-
-
0.4
V
Iin
-
±1
±10
µA
Cout
-
5
-
pF
IDR
-
50
-
mA
Input Leakage Current
Digital Output Pin Capacitance
Drive Current FOUT, E1, E2, NEG
(Note 10)
Notes: 7. All measurements performed under static conditions.
8.
9.
10.
DS659F1
If external MCLK is used, then the duty cycle must be between 45% and 55% to maintain this specification.
The frequency of CPUCLK is equal to MCLK.
VOL and VOH are not specified under this condition.
7
CS5466
SWITCHING CHARACTERISTICS
•
•
•
•
Min / Max characteristics and specifications are guaranteed over all operating conditions.
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
Logic Levels: Logic 0 = 0 V, Logic 1 = VD+.
Parameter
Symbol
Min
Typ
Max
Unit
Rise Times
Digital Output (Note 11)
trise
-
50
-
ns
Fall Times
Digital Output (Note 11)
tfall
-
50
-
ns
XTAL = 4.096 MHz (Note 12)
tost
-
60
-
ms
Period
t1
500
-
-
ms
Pulse Width
t2
250
-
-
ms
Rising Edge to Falling Edge
t3
250
-
-
ms
E1 Falling Edge to E2 Falling Edge
t4
250
-
-
ms
t5
0.10
1 / fFOUT
t6
-
0.5*t5
90
ms
t7
-
0.5*t5
-
ms
Start-up
Oscillator Start-up Time
E1 and E2 Timing (Note 13 and 14)
FOUT Timing (Note 13 and 14)
Period
Pulse Width
(Note 15)
FOUT Low
ms
Notes: 11. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
12.
Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external
clock source.
13. Pulse output timing is specified at MCLK = 4.096 MHz. Current and voltage signals are at unity power factor. See
”Energy Pulse Outputs” on page 11. for more information on pulse output pins.
14. Timing is proportional to the frequency of MCLK.
15. When FREQ2 = 0, FREQ1=1 and FREQ0=1, FOUT will have a typical pulse width of 20 µs at MCLK = 4.096 MHz.
t1
E1
t2
t3
t4
t1
t2
E2
t3
t5
FOUT
t6
t7
Figure 1. Timing Diagram for E1, E2 and FOUT (Not to Scale)
8
DS659F1
CS5466
ABSOLUTE MAXIMUM RATINGS
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Parameter
DC Power Supplies
Input Current, Any Pin Except Supplies
Symbol
Min
Typ
Max
Unit
(Notes 16 and 17)
Positive Digital
Positive Analog
VD+
VA+
-0.3
-0.3
-
+6.0
+6.0
V
V
(Notes 18, 19, 20)
IIN
-
-
±10
mA
IOUT
-
-
100
mA
Output Current, Any Pin Except VREFOUT
PD
-
-
500
mW
Analog Input Voltage
All Analog Pins
VINA
- 0.3
-
(VA+) + 0.3
V
Digital Input Voltage
All Digital Pins
VIND
-0.3
-
(VD+) + 0.3
V
Ambient Operating Temperature
TA
-40
-
85
°C
Storage Temperature
Tstg
-65
-
150
°C
Power Dissipation
(Note 21)
Notes: 16. VA+ and AGND must satisfy {(VA+) - (AGND)} ≤ + 6.0 V.
17. VD+ and AGND must satisfy {(VD+) - (AGND)} ≤ + 6.0 V.
18. Applies to all pins including continuous over-voltage conditions at the analog input pins.
19. Transient current of up to 100 mA will not cause SCR latch-up.
20. Maximum DC input current for a power supply pin is ±50 mA.
21. Total power dissipation, including all input currents and output currents.
DS659F1
9
CS5466
IIN± PGA
4th Order
∆Σ
Modulator
Sinc3
IIR
FREQ[2:0]
IGAIN[1:0]
HPF
HPF
Config
Digital Filter
Current Channel
E1
N=400
VIN±
10x
2nd Order
∆Σ
Modulator
x
Sinc3
IIR
HPF
Σ
N
Energy-toPulse Rate
Converter
E2
FOUT
NEG
Digital Filter
Voltage Channel
Figure 2. Data Flow
4.
THEORY OF OPERATION
The CS5466 is a dual-channel analog-to-digital converter (ADC) followed by a computation engine that performs an energy-to-pulse conversion. The flow diagram
for the two data paths is depicted in Figure 2. The analog inputs are structured with two dedicated channels,
voltage and current, then optimized to simplify interfacing to sensing elements.
The voltage-sensing element introduces a voltage
waveform on the voltage channel input VIN± and is subject to a fixed 10x gain amplifier. A second-order deltasigma modulator samples the amplified signal for digitization.
Simultaneously, the current sensing element introduces
a voltage waveform on the current channel input IIN±
and is subject to four programmable gains. The amplified signal is sampled by a fourth-order delta-sigma
modulator for digitization. Both converters sample at a
rate of MCLK / 8. The over-sampling provides a wide
dynamic range and simplified anti-alias filter design.
4.1
Digital Filters
The decimating digital filters on both channels are Sinc3
filters followed by fourth-order IIR filters. The single-bit
data is passed to the low-pass decimation filter and output at a fixed word rate. The output word is passed to
10
the IIR filter to compensate for the magnitude roll-off of
the low-pass filtering operation.
An optional digital high-pass filter (HPF in Figure 2) removes any DC component from the selected signal
path. By removing the DC component from the voltage
or current channel, any DC content will also be removed
from the calculated average active (real) power as well.
4.2
Active Power Computation
The instantaneous voltage and current data samples
are multiplied to obtain the instantaneous power. The
product is then averaged over 400 conversions to compute the active power value used to drive pulse outputs
E1, E2, and FOUT. Output pulse rate of E1 and E2 can
be set to one of four frequencies to directly drive a stepper motor or a electromechanical counter or interface to
a microcontroller or infrared LED. The alternating output
pulses of E1 and E2 allows for use with low-cost electromechanical counters.
Output FOUT provides a uniform pulse stream that is
proportional to the active power and is designed for system calibration. The FREQ[2:0] inputs set the output
pulse rate of E1, E2, and FOUT. See ”Energy Pulse
Outputs” on page 11. for more details.
DS659F1
CS5466
5.
5.1
FUNCTIONAL DESCRIPTION
Analog Inputs
The CS5466 is equipped with two fully differential input
channels. The inputs VIN± and IIN± are designated as
the voltage and current channel inputs, respectively.
The full-scale differential input voltage for the current
and voltage channel is ±250 mVP.
5.1.1
Voltage Channel
The output of the line-voltage resistive divider or transformer is connected to the VIN+ and VIN- input pins of
the CS5466. The voltage channel is equipped with a
10x, fixed-gain amplifier. The full-scale signal level that
can be applied to the voltage channel is ±250 mV. If the
input signal is a sine wave, the maximum RMS voltage
is:
250mV P
----------------- ≅ 176.78mV RMS
2
which is approximately 70.7% of maximum peak voltage.
5.1.2
Current Channel
The output of the current-sense resistor or transformer
is connected to the IIN+ and IIN- input pins of the
CS5466. To accommodate different current-sensing devices, the current channel incorporates programmable
gains which can be set to one of four input ranges. Input
pins IGAIN1 and IGAIN0 (See Table 1) define the four
gain selections and corresponding maximum input signal level.
IGAIN1 IGAIN0
Maximum Input
Range
0
0
±250mV
10x
0
1
±50mV
50x
1
0
±25mV
100x
1
1
±16.67mV
150x
Table 1. Current Channel PGA Setting
For example, if IGAIN1=IGAIN0=0, the current channel’s gain is set to 10x. If the input signals are pure sinusoids with zero phase shift, the maximum peak
differential signal on the current or voltage channel is
±250 mVP. The input signal levels are approximately
70.7% of maximum peak voltage producing a full-scale
energy pulse registration equal to 50% of absolute maximum energy pulse registration. This will be discussed
further in Section 5.3 Energy Pulse Outputs on page 11.
DS659F1
5.2
High-pass Filter
By removing the offset from either channel, no error
component will be generated at DC when computing the
active power. Input pin HPF defines the three options:
– High-pass Filter (HPF) is disabled when pin HPF is
connected high.
– HPF is enabled in the voltage channel when pin HPF is
connected low.
– HPF is enabled in the current channel when pin HPF is
connected to pin FOUT.
5.3
Energy Pulse Outputs
The CS5466 provides three output pins for energy registration. The E1 and E2 pins provide a simple interface
from which energy can be registered. These pins are
designed to directly connect to a stepper motor or electromechanical counter. The pulse rate on the E1 and E2
pins are in the range of 0 to 4 Hz and all frequency settings are optimized to be used with standard meter constants. The FOUT pin is designated for system
calibration and the pulse rate can be selected to reach
a frequency of 8000 Hz.
5.3.1
Pulse Output Format.
The CS5466 produces alternating pulses on E1 and E2.
This pulse format is designed to drive a stepper motor.
Each pin produces active-low pulses with a minimum
pulse width of 250 ms when MCLK = 4.096 MHz. Refer
to “Switching Characteristics” on page 8 for timing parameters.
The FOUT pin issues active-high pulses. The pulse
width is equal to 90 ms (typical), unless the period falls
below 180 ms. At this time the pulses will be equal to
half the period. In mode 3 (FREQ[2:0] = 3), the pulse
width of all FOUT pulses is typically 20 µs regardless of
the pulse rate (MCLK = 4.096 MHz).
5.3.2
Selecting Frequency of E1 and E2
The pulse rate on E1 and E2 can be set to one of four
frequency ranges. Input pins FREQ1 and FREQ0 (See
Table 2) determine the maximum frequency on E1 and
E2 for pure sinusoidal inputs with zero phase shift. As
shown in Figure 1 on page 8, the frequency of E2 is
equal to the frequency of E1 with active-low alternating
pulses.
As discussed in Section 5.1.2 Current Channel on page
11, the maximum frequency on the E1 and E2 output
pins is equal to the selected frequency in Table 2 if the
maximum peak differential signal applied to both channels is a sine wave with zero phase shift.
11
CS5466
Frequency Select
Maximum Frequency for a Sine Wave (Notes 1, 2 and 3)
FREQ2
FREQ1
FREQ0
E1 or E2
E1+E2
0
0
0
0.125 Hz
0.25 Hz
64x(E1+E2)
16 Hz
0
0
1
0.25 Hz
0.5 Hz
32x(E1+E2)
16 Hz
0
1
0
0.5Hz
1.0 Hz
16x(E1+E2)
16 Hz
0
1
1
1.0 Hz
2.0 Hz
2048x(E1+E2)
4,096 Hz
1
0
0
0.125 Hz
0.25 Hz
128x(E1+E2)
32 Hz
1
0
1
0.25 Hz
0.5 Hz
64x(E1+E2)
32 Hz
1
1
0
0.5 Hz
1.0 Hz
32x(E1+E2)
32 Hz
1
1
1
1.0 Hz
2.0 Hz
16x(E1+E2)
32 Hz
Notes:
1
2
3
FOUT
A pure sinusoidal input with zero phase shift is applied to the voltage and current channel.
MCLK = 4.096 MHz
See Figure 1 on page 8 for E1 and E2 timing diagram.
Table 2. Maximum Frequency for E1, E2, and FOUT
5.3.3
Selecting Frequency of FOUT
The pulse output FOUT is designed to assist with meter
calibration. Using the FREQ[2:0] pins, FOUT can be set
to frequencies higher than that of E1 and E2. The FOUT
frequency is directly proportional to the E1 and E2 frequencies. Table 2 defines the maximum frequencies for
FOUT and the dependency of FOUT on E1 and E2.
5.3.4
Absolute Max Frequency on E1
and E2
The CS5466 supports input signals on the voltage and
current channels that may not be a sine wave. A typical
situation of achieving the absolute maximum frequency
on E1 and E2 would be if a 250 mV dc signal is applied
to the VIN and IIN input pins. The digital high-pass filter
should be disengaged by selecting HPF = 1.
12
The absolute maximum pulse rate observed on E1 and
E2, determined by the FREQ[2:0] selection is defined
below in Table 3.
Frequency Select
FREQ2 FREQ1 FREQ0
Absolute Max Frequency
E1 or E2
E1+E2
x
0
0
0.25 Hz
0.5 Hz
x
0
1
0.5 Hz
1.0 Hz
x
1
0
1.0 Hz
2.0 Hz
x
1
1
2.0 Hz
4.0 Hz
Table 3. Absolute Max Frequency on E1 and E2
DS659F1
CS5466
5.3.5
E1 and E2 Frequency Calculation
The pulse output frequency of E1 and E2 is directly proportional to the active power calculated from the input
signals. To calculate the output frequency on E1 and
E2, use the following transfer function:
output pin will become active-high and will remain active-high until positive active power is detected. The
NEG pin is valid at least 250ns prior to any assertion of
E1 or E2, and FOUT, to indicate the sign of a given energy output. The NEG pin is updated at a rate of 10 Hz
at MCLK = 4.096 MHz.
5.5
FREQ E1,E2
=
VIN × 10 × IIN × IGAIN × PF × FREQ max
-----------------------------------------------------------------------------------------------------------------2
VREFIN
FREQE1,E2 = Actual frequency of E1 and E2 pulses [Hz]
VIN = rms voltage across VIN+ and VIN- [V]
IIN = rms voltage across IIN+ and IIN- [V]
IGAIN = Current channel gain selection (10, 50, 100, 150)
PF = Power Factor
FREQmax = Absolute Max Frequency for E1 and E2 [Hz]
VREFIN = Voltage at VREFIN pin [V]
Power-on Reset
Upon powering up, the digital circuitry is held in reset
until the analog voltage reaches 4.0 V. At that time, an
eight-XIN-clock-period delay is enabled to allow the oscillator to stabilize. The CS5466 will then initialize. The
device reads the control pins IGAIN[1:0], FREQ[2:0]
and HPF, and begins performing energy measurements.
5.6
Oscillator Characteristics
XIN and XOUT are the input and output of an inverting
amplifier which can be configured as an on-chip oscillator, as shown in Figure 3. The oscillator circuit is designed to work with a quartz crystal. To reduce circuit
Example:
For a given application, assume a 50 Hz line frequency
and a purely resistive load (unity power factor), the following configuration is used:
– FREQ[2:0] = 3 ∴ FREQmax = 2 Hz
– IGAIN[1:0] = 2 ∴ IGAIN = 100
– VREFIN = VREFOUT = 2.5 V
In this configuration, the maximum sine wave that can
be applied is 250 mVp on the voltage channel and
25 mVp on the current channel. Using the above equation, the output frequency of energy pulse E1 or E2 is
calculated:
0.25V p × 10 × 0.025V p × 100 × 1 × 2Hz
--------------------------------------------------------------------------------------------------------- = 1Hz
2
2 × 2 × 2.5V
With maximum pure sinusoidal input signals, the frequency of E1 or E2 is half the absolute maximum frequency set with FREQ[2:0].
To calculate the frequency of FOUT for the example
above, assume FREQ2 = 0.
FOUT = 2048 × ( E1 + E2 ) = 2048 × 2Hz = 4096Hz
5.4
Energy Direction Indicator
XOUT
C1
Oscillator
Circuit
XIN
C2
DGND
C1 = C2 = 22 pF
Figure 3. Oscillator Connection
cost, two load capacitors C1 and C2 are integrated in
the device, one between XIN and DGND and the other
between XOUT and DGND. Lead lengths to/from the
crystal should be minimized to reduce stray capacitance. To drive the device from an external clock
source, XOUT should be left unconnected while XIN is
driven by the external circuitry. There is an amplifier between XIN and the digital section which provides
CMOS-level signals. This amplifier works with sinusoidal inputs so there are no problems with slow edge
times.
The NEG pin indicates the sign of the calculated active
power. If negative active power is detected, the NEG
DS659F1
13
CS5466
5.7
Basic Application Circuit
shunt resistor configuration, the common-mode level of
the CS5466 must be referenced to the line side of the
power line. This means that the common-mode potential of the CS5466 will track the high voltage levels, as
well as low voltage levels, with respect to earth ground
potential.
Figure 4 shows the CS5466 configured to measure
power in a single-phase, 2-wire system while operating
in a single-supply configuration. In this diagram, a shunt
resistor is used to sense the line current and a voltage
divider is used to sense the line voltage. In this type of
120 VAC
N
L
500 Ω
500 Ω
470 nF
+ 470 µF
10 Ω
1 µF
10 kΩ
0.1 µF
0.1µF
+
14
AGND
VA+
9
C V+
R2
Calibratio
n
Resistor
R1
C V-
RV-
C I-
RSHUNT
C I+
RI+
RESET
EDIR / P4
E2
E1
CVdiff
10
15
RI-
VIN+
VIN-
FOUT
NEG
IIN-
FREQ2
FREQ1
FREQ0
CIdiff
16
3
VD+
IGAIN1
IIN+
IGAIN0
IHPF
XOUT
12
11
0.1 µF
XIN
AGND
VA13
Stepper
Motor
22
18
6
17
20
23
7
5
5466
Config.
Settings
8
1
4.096 MHz
VREFIN
VREFOUT
19
21
CPUCLK
24
2
DGND
4
Note:
Indicates common (floating) return.
Figure 4. Typical Connection Diagram
14
DS659F1
CS5466
6. PACKAGE DIMENSIONS
24L SSOP PACKAGE DRAWING
N
D
E11
A2
E
e
2
b
SIDE VIEW
A
∝
A1
L
END VIEW
SEATING
PLANE
1 2 3
TOP VIEW
DIM
A
A1
A2
b
D
E
E1
e
L
∝
MIN
-0.002
0.064
0.009
0.311
0.291
0.197
0.022
0.025
0°
INCHES
NOM
-0.006
0.068
-0.323
0.307
0.209
0.026
0.03
4°
MAX
0.084
0.010
0.074
0.015
0.335
0.323
0.220
0.030
0.041
8°
MIN
-0.05
1.62
0.22
7.90
7.40
5.00
0.55
0.63
0°
MILLIMETERS
NOM
-0.13
1.73
-8.20
7.80
5.30
0.65
0.75
4°
NOTE
MAX
2.13
0.25
1.88
0.38
8.50
8.20
5.60
0.75
1.03
8°
2,3
1
1
JEDEC #: MO-150
Controlling Dimension is Millimeters.
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
DS659F1
15
CS5466
7.
ORDERING INFORMATION
Model
CS5466-IS
CS5466-ISZ (lead free)
8.
Temperature
Package
-40 to +85 °C
24-pin SSOP
ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number
Peak Reflow Temp
MSL Rating*
Max Floor Life
CS5466-IS
240 °C
2
365 Days
CS5466-ISZ (lead free)
260 °C
3
7 Days
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
9.
REVISION HISTORY
Revision
Date
Changes
PP1
SEP 2004
Initial Release
PP2
OCT 2004
Corrected table heading on Page 6.
PP3
JUN 2005
F1
AUG
Minor edits
Updated with most-current characterization data. corrected energy pulse output
rate equation on p13. Added MSL data.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
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16
DS659F1