application INFO available Frequency Foldback Current Mode PWM Controller UCC1884 UCC2884 UCC3884 PRELIMINARY FEATURES DESCRIPTION • Frequency Foldback Reduces Operating Frequency Under Fault Conditions The UCC3884 is a high performance current mode PWM controller intended for single ended switch mode power supplies. The chip implements a frequency foldback scheme that decreases the oscillator frequency as the output voltage falls below a programmed value. This technique decreases the average output current sourced into a low impedance load which can occur during an output short circuit or overload condition. Excessive short circuit current is more prevalent in high frequency converters where the propagation delay and switch turn-off time forces a minimum attainable duty cycle. An accurate volt-second clamp limits the duty cycle during line or load transient conditions which could otherwise saturate the transformer. The volt-second clamp may also be used with an external overvoltage protection circuit to handle fault conditions such as current sense disconnect or current transformer saturation. The frequency foldback, volt-second clamp, cycle-by-cycle current limit, and overcurrent shutdown provide a rich set of protection features for use in peak current mode pulse width modulators. • Accurate Programmable Volt-Second Clamp • Programmable Maximum Duty Cycle Clamp • Oscillator Synchronization • Overcurrent Protection • Shutdown with Full Soft Start • Wide Gain Bandwidth Amplifier (GBW > 2.5MHz) • Current Mode Operation • Precision 5V Reference BLOCK DIAGRAM UDG-96026-1 SLUS160A - AUGUST 1999 UCC1884 UCC2884 UCC3884 CONNECTION DIAGRAMS ABSOLUTE MAXIMUM RATINGS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Output Sink Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A Output Source Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C DIL-16, SOIC-16 (Top View) J, N or D Packages Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. PLCC-20 (Top View) Q Package ELECTRICAL CHARACTERISTICS: Unless otherwise specified, these specifications apply for TA = –55°C to 125°C for the UCC1884, –40°C to 85°C for the UCC2884, and 0°C to 70°C for the UCC3884, CT = 220pF, RON = 53k, ROFF = 38k, VOUT = VREF, VVS = 0V, CSS = 2.5nF, VDD = 11V, Output no load, TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 4.86 5 5.14 V 1 10 mV 5V Reference Section VREF IREF = 0mA Line Regulation VDD = 10V to 12V Load Regulation 0 < IREF < 5mA 1 20 mV Short Circuit I VREF = 0V 15 45 mA Oscillator Section Accuracy VOUT = VREF 360 400 440 kHz Foldback Frequency VOUT = 0.75V 200 230 260 kHz CLKSYNC Output High 4.8 CLKSYNC Output Low CLKSYNC Sink Current CLKSYNC = 1V CLKSYNC Source Current CLKSYNC = 3V 1.2 CLKSYNC Input Threshold CLKSYNC from 5V to 0V (Edge Detect) 2.5 5 5.2 V 0.0 0.4 V 2.2 mA –0.2 –0.1 mA 3.0 3.5 V 1 µA 2.57 V Error Amplifier Section IB Total Bias Current; Regulating Level FB Voltage FB = COMP 2.43 2.5 50 90 dB F = 100kHz (Note 1) 2.5 5 MHz AVO GBW –1 Output Source Current FB = 2.3V, COMP = 2.5V –0.6 –1.2 mA Output Sink Current FB = 2.7V, VCOMP = 1V 0.250 1.5 mA VOL IO = 100µA 0.3 0.9 V VOH IO = –100µA 2.7 3.1 3.5 V 2 UCC1884 UCC2884 UCC3884 ELECTRICAL CHARACTERISTICS: Unless otherwise specified, these specifications apply for TA = –55°C to 125°C for the UCC1884, –40°C to 85°C for the UCC2884, and 0°C to 70°C for the UCC3884, CT = 220pF, RON = 53k, ROFF = 38k, VOUT = VREF, VVS = 0V, CSS = 2.5nF, VDD = 11V, Output no load, TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS PWM Section Minimum Duty Cycle FB = 3V, CS = 0V Maximum Duty Cycle FB = 0V, CS = 0V 0 % 75 78 81 % 3.0 µA 1.235 1.3 1.365 Current Sense Section Input Bias Current (CS) CS Shutdown Threshold CS Shutdown Hysteresis 20 CS Over Current Threshold V mV 0.95 1 1.05 V Soft Start Charge Current –10 –20 –30 µA Soft Start Discharge Current 10 20 30 µA Current/Fault Section 0 50 mV Soft Start Complete Threshold 3.6 4 4.4 V Soft Start Restart Threshold 0.4 0.5 0.6 V VVS = 1.4V, TA = 0°C to 70°C 53.8 56.8 59.8 % VVS = 3.6V, TA = –55°C to 125°C 19.8 22 26.0 % VVS = 3.6V, TA = –40°C to 85°C VOL Volt Second Clamp Duty Cycle IB 20.9 22 25.0 % VVS = 3.6V, TA = 0°C to 70°C 21 22 23 % VVS = 3.7V –1 +1 µA Output Stage Output Low Saturation IOUT = 100mA 0.5 0.9 V Output High Saturation IOUT = –50mA 0.5 0.9 V 1.9 V UVLO Output Low Saturation IOUT = –200mA (Note 1) IOUT = 20mA, VDD = 0V 0.7 1.2 V Rise Time CL = 1nF 50 70 ns Fall Time CL = 1nF 30 50 ns Undervoltage Lockout Turn-On Threshold Voltage 8.4 8.9 9.4 V Hysteresis 200 600 1000 mV 9.5 10 Startup Regulator Regulated VDD Voltage VDD Override Threshold 10.5 V 10.7 V 14.5 V Overall VDD Range IDD (run) f = 400kHz 2 IDD Startup Current VDD = 5.4V 100 VDD Clamp IDD = 10mA 12 Note 1: Guaranteed by design. Not 100% tested in production. 3 5 13.5 10 mA 250 µA 15 V UCC1884 UCC2884 UCC3884 PIN DESCRIPTIONS GND: The ground pin internally used for all the amplifiers and as the return for all resistor and capacitor connections to the UCC3884. CLKSYNC: An edge triggered active low TTL signal to this pin synchronizes the oscillator to an external clock. When VOUT decreases below 3.0V, the frequency foldback circuit is activated and the controller becomes unsynchronized. When VOUT exceeds 3.0V, the controller resynchronizes to the external clock. GT: Used to drive an external depletion-mode MOSFET for the housekeeping power supply. The MOSFET is turned off when the bootstrap winding voltage exceeds 10V. There is 300mV of hysteresis around the 10V turn-off voltage to prevent oscillation. See Typical Application. COMP: The output of the voltage error amplifier used for compensation. The output is clamped to 3.0V minimum. CS: Current sense input. This pin accepts a voltage proportional to converter inductor current. The voltage at CS is compared to the output of the compensated error amplifier to control the on-time of the switch. Voltage mode control can be realized by driving this pin with a fixed sawtooth ramp. Voltage feedforward is achieved by making the peak of this ramp proportional to the input voltage. IOFF: A resistor, ROFF, to ground, programs the discharge current of the timing capacitor CT. This is a variable discharge current which determines the negative slope of the oscillator voltage waveform at CT. The discharge time is dependent on the voltage at the VOUT pin. The discharge current is given by IOFF = VOUT/ROFF. The VOUT pin is internally clamped to 3.5V maximum. CSS: A capacitor, CSS, to ground programs the soft start time for the power up sequence. This function is also used when an overcurrent fault occurs. As CSS is charged, the PWM comparator uses the lowest of either the voltage at CSS or the error amplifier output voltage to determine the duty cycle. The duty cycle, therefore, slowly increases during the soft start cycle. The faults that cause CSS to discharge and shutdown the controller are the logical OR of VREF below 4.4V or VDD below 8.8V. If a fault is still present when CSS is discharged below 0.5V, the supply remains off until the fault is cleared. The soft start time is determined by: TSS = 3.5 • ION: A resistor, RON, to ground programs the charge current of the timing capacitor, CT, which generates the positive slope of the oscillator waveform. The charge time is constant and corresponds to the maximum output on-time at OUT. The charge current equation is ION = 1.5V/RON. When required the linear positive slope of the CT voltage could be buffered and used to provide slope compensation into the CS pin. OUT: The output of the controller. The peak source current is 0.5A and the peak sink current is 1.0A. The faults listed under the CSS description turn off this output. CSS ISS PGND: The power ground pin is used as the return for the output transistor drive stage. where ISS is 20µA. A current limit terminates the present cycle. It does not generate a soft start cycle. VDD: The input voltage of the chip. A low ESR and ESL ceramic capacitor from this pin to GND should be used to bypass internal switching transients. CT: A capacitor, CT to ground, is charged and discharged creating the oscillator waveform. This waveform varies between 1.5V and 3.5V. The operating frequency is determined by: f= VOUT: This pin accomplishes frequency foldback by controlling the discharge current for the oscillator CT capacitor. A dc voltage proportional to the output voltage is connected to this pin. To startup with zero output voltage the user should tie a resistor between VREF and VOUT. The value depends on the lowest desired operating frequency. When VOUT decreases below 3.5V the frequency decreases by reducing the discharge current IOFF. When VOUT increases, the frequency increases by increasing the discharge current. The maximum operating frequency occurs when VOUT = 3.5V. The CT charge time is constant to guarantee a maximum output duty cycle. This pin must be above 3.0V to allow synchronization to occur. 4.4 R ON R OFF CT • + 3.5 1.5 The ratio of the time duration of the positive sloped portion of the CT voltage waveform to the period gives the maximum duty cycle. FB: The inverting input of the voltage amplifier used to sense the output voltage. The non-inverting input of the error amplifier is internally connected to 2.5V. 4 UCC1884 UCC2884 UCC3884 PIN DESCRIPTIONS (cont.) IC determines the reciprocal of the voltage at VVS and scales the result. The voltage is then compared to the oscillator waveform to clamp the duty cycle. The purpose of this clamp is to reduce the likelihood of saturating the isolation transformer during unusual line or load conditions. VREF: This pin is the output of the 5V regulated reference. Bypass this pin with a low ESR and ESL ceramic capacitor (e.g., 0.47µF). VVS: Provides a programmable duty cycle clamp which is dependent upon the input voltage. A resistor divider network reduces the input voltage supplied to VVS. The APPLICATION INFORMATION a load transient (a fault such as a momentary short circuit) as the error amplifier increases the duty cycle, that when the volt-second clamp accurately limits the maximum volt-seconds. This ensures that the transformer does not saturate during a fault which can fail the power supply. After the fault is removed the converter resumes closed loop control. Theory of Operation The UCC3884 current mode PWM controller contains a programmable oscillator which includes the ability to synchronize multiple PWMs. The positive and negative sloped portions of the oscillator waveform (measured at CT), have time intervals that are set by external resistors at ION and IOFF. The operating frequency is inversely proportional to the timing capacitor. The negative sloped portion of the oscillator waveform is extended in time as the measured output voltage decreases providing protection during output faults. The power supply output voltage and the voltage from VREF are fed back to VOUT. When the output voltage decreases, the voltage at VOUT also decreases. As VOUT decreases below 3.5V, the operating frequency decreases. This reduction in frequency allows the duty cycle to decrease below what the CS to OUT delay would otherwise permit. This is referred to as frequency foldback. An output short circuit or overload causes the converter to enter the frequency foldback mode. Synchronization to other controllers can only occur during normal operation, that is, when VOUT is greater than 3.0V. CSS is provided which allows the UCC3884 to be disabled with an external transistor. The increasing pulse width at OUT during soft start should be programmed to be less than the pulse width of the duty cycle limit that the frequency foldback circuitry creates. The frequency foldback circuit will be in effect during soft start since the output voltage fed back to VOUT is less than 3.5V. Designing the circuit in this fashion allows a proper startup sequence. The current sense feedback pin has an overcurrent protection feature which forces a soft start cycle only if the IC is not currently in a soft start cycle. A 1V bias at the PWM comparator’s non-inverting input and a reset dominant PWM latch permit zero duty cycle operation. The error amplifier has a wide gain-bandwidth product and its non-inverting input is internally set to 2.5VDC. GT is provided to turn off an external depletion-mode MOSFET after startup when the bootstrap winding exceeds 10V. This depletion-mode MOSFET is used in the housekeeping section of the converter to simplify startup biasing circuitry. The amplifier that drives this MOSFET has 300mV of hysteresis to avoid oscillation during power up. Oscillator The oscillator has charge and discharge currents programmed with resistors to ground from ION and IOFF respectively, as seen on the Oscillator Block Diagram (Fig. 1). This generates a linear sawtooth waveform on CT. Frequency foldback is accomplished by the level shifted output voltage controlling the VOUT voltage which decreases the discharge current and the frequency. An accurate programmable volt-second technique clamps the duty cycle. The duty cycle limit is inversely proportional to input voltage and a resistor divider network is used to program the proportionality constant. At a given input voltage and constant load, under closed loop control, the operating duty cycle is a fixed value. The volt-second clamp duty cycle may then be set somewhat higher than this operating duty cycle. For other input voltages, the volt-second clamp will still exceed the steady state operating duty cycle. This allows normal closed loop operation of the converter. It is during Synchronization is accomplished by coupling the fastest oscillator CLKSYNC signal as shown on the Oscillator Synchronization Diagram (Fig. 2). The fastest (master) CLKSYNC pin will couple a negative pulse into the slower (slave) CLKSYNC pins forcing the slaves’ CT pins to quickly discharge as shown on the Oscillator Waveform diagram (Fig. 3). 5 UCC1884 UCC2884 UCC3884 APPLICATION INFORMATION (cont.) VREF 1.5V ION 11 CLK CT 3.5V 10 VREF VOUT 13 IOFF 12 1.5V S Q R Q 6 CLKSYNC 3.0V 3.5V 14 SYNCEN 3V SYNCEN 8.8X UDG-99088 Figure 1. UCC3884 oscillator. UDG-96028-1 UDG-96027 Figure 2. Oscillator synchonization connection diagram. Figure 3. Oscillator waveforms. 6 UCC1884 UCC2884 UCC3884 APPLICATION INFORMATION (cont.) The following explains two synchronization techniques: 1. and maximum duty cycle clamp should be programmed accordingly. The ROFF resistor which programs the slave units oscillator discharge ramp should be between 50% and 100% of the ROFF resistor which programs the master. This guarantees that if a slave unit tries to synchronize the master, the master frequency will still be faster than the slave frequency and the master will synchronize all the remaining units. If the user does not care which unit is the master, then the oscillator frequencies are designed as accurate as necessary and one unit will become the master and synchronize the remaining units. The user will never know exactly which unit will be themaster upon power up. 2. If the user does care which unit is the master, a unit should be identified as the master, and the frequency UDG-96032-1 Figure 4. Typical application. UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 FAX (603) 424-3460 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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