SA53 SA53 P r o d u c t IInnnnoovvaa t i o n FFr roomm Switching Amplifier FEATURES ♦ Low Cost Intelligent Switching Amplifier ♦ Directly Connects to Most Embedded Microcontrollers and Digital Signal Controllers ♦ Integrated Gate Driver Logic with Dead-time Generation and Shoot-through Prevention ♦ Wide Power Supply Range (8.5 V To 60 V) ♦ Over 10A Peak Output Current per Phase ♦ 3A Continuous Output Current per Phase ♦ Independent Current Sensing for each Output ♦ User Programmable Cycle-by-cycle Current Limit Protection ♦ Over-Current and Over-Temperature Warning Signals APPLICATIONS ♦ Bidirectional DC Brush Motors ♦ 2 Unidirectional DC Brush Motors ♦ 2 Independent Solenoid Actuators ♦ Stepper Motors DESCRIPTION The SA53 is a fully integrated switching amplifier designed primarily to drive DC brush motors. Two independent half bridges provide over 10 amperes peak output current under microcontroller or DSC control. Thermal and short circuit monitoring is provided, which generates fault signals for the microcontroller to take appropriate action. A block diagram is provided in Figure 1. Additionally, cycle-by-cycle current limit offers user programmable hardware protection independent of the microcontroller. Output current is measured using an innovative low loss technique. The SA53 is built using a multi-technology process allowing CMOS logic control and complementary DMOS output power devices on the same IC. Use of P-channel high side FETs enables 60V operation without bootstrap or charge pump circuitry. The Power Quad surface mount package balances excellent thermal performance with the advantages of a low profile surface mount package. Figure 1. BLOCK Diagram VS + VDD SC TEMP ILIM/D IS 1 Fault Logic I1 I2 I1' Vs 2 VDD VDD I1' I2' I2' D IS 2 Gate Control 1t 1b P ha se 1 PWM Signals Vs 1 O ut 1 O ut 2 Control Logic 2t P ha se 2 2b SGND SA53 Switching Amplifier PGND 1 PGND 2 GND SA53U http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2009 (All Rights Reserved) MAY 2009 APEX − SA53UREVA SA53 P r o d u c t I n n o v a t i o nF r o m 1. Characteristics and Specifications Absolute Maximum Ratings Parameter Symbol Min Max Units SUPPLY VOLTAGE VS 60 V SUPPLY VOLTAGE VDD 5.5 V (VDD+0.5) V LOGIC INPUT VOLTAGE (-0.5) OUTPUT CURRENT, peak, 10ms (NOTE 2) IOUT 10 A POWER DISSIPATION, avg, 25ºC (NOTE 2) PD 100 W TS 260 °C TEMPERATURE, solder, 10sec TEMPERATURE, junction (NOTE 2) TJ TEMPERATURE RANGE, storage OPERATING TEMPERATURE, case 150 °C TSTG −55 125 °C TA −40 125 °C Specifications PARAMETER MIN TEST CONDITIONS (Note 1) TYP MAX UNITS 1 V LOGIC INPUT LOW INPUT HIGH 1.8 V OUTPUT LOW 0.3 OUTPUT HIGH 3.7 V V OUTPUT CURRENT (SC, Temp, ILIM/DIS1) 50 mA POWER SUPPLY VS UVLO 50 VS UNDERVOLTAGE LOCKOUT, (UVLO) 60 8.3 VDD V V 4.5 5.5 V SUPPLY CURRENT, VS 20 kHz (One phase switching at 50% duty cycle) , VS=50V, VDD=5V 25 30 mA SUPPLY CURRENT, VDD 20 kHz (One phase switching at 50% duty cycle) , VS=50V, VDD=5V 5 6 mA CURRENT LIMIT Current Limit Threshold (Vth) 3.75 V Vth Hysteresis 100 mV OUTPUT CURRENT, continuous 25ºC Case Temperature Rising delay, td (rise) See Figure 10 270 ns Falling delay, td (fall) See Figure 10 270 ns Disable delay, td (dis) See Figure 10 200 ns Enable delay, td (dis) See Figure 10 200 ns Rise Time, t (rise) See Figure 11 50 ns Fall Time, t (fall) See Figure 11 50 ns On resistance Sourcing (P-Channel) 3A Load 400 mΩ On resistance Sinking (N-Channel) 3A Load 400 mΩ 3 A SA53U SA53 P r o d u c t I n n o v a t i o nF r o m Specifications, continued PARAMETER TEST CONDITIONS (Note 1) MIN TYP MAX UNITS THERMAL Thermal Warning 135 ºC Thermal Warning Hysteresis 40 ºC RESISTANCE, junction to case Full temperature range TEMPERATURE RANGE, case Meets Specifications 1.25 -40 1.5 ºC/W 85 ºC NOTES: 1. (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at typical supply voltages and TC = 25°C). 2. Long term operation at elevated temperature will result in reduced product life. De-rate internal power dissipation to achieve high MTBF. 3. Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. Figure 2. 64-pin QFP, Package Style HQ SA53U SA53 P r o d u c t I n n o v a t i o nF r o m 10 ONE PHASE SWITCHING FREQUENCY = 20kHz 50% DUTY CYCLE 5 8 20 30 40 50 VS SUPPLY VOLTAGE (V) VDD SUPPLY CURRENT 7 6.5 6 125°C 5.5 25°C 5 4.5 4 10 20 30 40 50 VS SUPPLY VOLTAGE (V) 80 60 40 ONE PHASE SWITCHING @ 50% DUTY CYCLE; VS=50V 20 0 50 0.1 0.01 100 150 200 250 300 FREQUENCY (kHz) VDD SUPPLY CURRENT 120 4.9 4.8 4.7 4.6 ONE PHASE SWITCHING @ 50% DUTY CYCLE; VS=50V 50 1 0.1 1 SENSE CURRENT (mA) 10 POWER DERATING 100 80 60 40 20 0 -40 100 150 200 250 300 FREQUENCY (kHz) 0 40 80 120 CASE TEMPERATURE, TC 0.8 0.75 (P-Channel) 0.7 0.65 0.6 VS=11 0.55 VS=13 0.5 0.45 VS=15 0.4 0.35 0.3 VS>17 0.25 0.2 0.15 0 1 2 3 4 5 6 7 8 9 10 IOUT,(A) DIODE FORWARD VOLTAGE - BOTTOM FET 5 (N-Channel) 4 DIODE FORWARD VOLTAGE - TOP FET (P-Channel) 4 CURRENT (A) CURRENT (A) 100 ON RESISTANCE - TOP FET RDS(on),(Ω) RDS(on),(Ω) ON RESISTANCE - BOTTOM FET 3 2 1 3 2 1 0 0.5 120 4.5 0 60 0.8 0.75 (N-Channel) 0.7 0.65 0.6 0.55 VS=11 0.5 VS=13 0.45 VS=15 0.4 0.35 VS=17 0.3 0.25 0.2 VS>22 0.15 0 1 2 3 4 5 6 7 8 9 10 IOUT,(A) 5 140 5 ONE PHASE SWITCHING FREQUENCY = 20kHz 50% DUTY CYCLE 7.5 CURRENT SENSE 160 0 60 10 LOAD CURRENT (A) 25°C 0 10 VDD SUPPLY CURRENT (mA) VS SUPPLY CURRENT (mA) 125°C VDD SUPPLY CURRENT (mA) VS SUPPLY CURRENT (mA) 20 15 VS SUPPLY CURRENT 180 POWER DISSIPATION, PD VS SUPPLY CURRENT 25 0.7 0.9 1.1 1.3 FORWARD VOLTAGE (V) 0 1.5 0.5 0.7 0.9 1.1 1.3 FORWARD VOLTAGE (V) 1.5 SA53U SA53 P r o d u c t I n n o v a t i o nF r o m OUT 2 OUT 2 NC VS 2 VS 2 VS 2 VS 2 NC NC NC NC NC PGND 1 PGND 1 PGND 1 PGND 1 NC OUT 1 OUT 1 OUT 1 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Figure 3. External Connections OUT 2 53 32 NC NC 54 31 VS 1 PGND 2 55 30 VS 1 PGND 2 56 29 VS 1 PGND 2 57 28 NC HS 58 27 HS Table 1. Pin Descriptions Pin # Pin Name 29,30,31 51,52,53 55,56,57 3 61 63 1 VS (phase 1) OUT 2 PGND (phase 2) SC 2b 2t I2 7 ILIM/DIS1 SA53U Signal Type 10 11 12 13 14 15 16 17 18 19 20 NC SGND NC SGND NC 1b NC 1t NC VDD NC 9 SGND I1 8 21 NC 64 ILIM/DIS1 NC NC 7 22 6 63 NC DIS2 2t 5 23 SGND 62 4 NC NC NC 24 3 61 SC TEMP 2b 2 HS 25 1 26 60 I2 59 NC HS NC Simplified Pin Description Power Power Output Power Logic Output Logic Input Logic Input Analog Output High Voltage Supply (8.5-60V) supplies phase 1 only Half Bridge 2 Power Output High Current GND Return Path for Power Output 2 Indication of a short of an output to supply, GND or another phase Logic high commands 2 phase lower FET to turn on Logic high commands 2 phase upper FET to turn on Phase 2 current sense output As an output, logic high indicates cycle-by-cycle current limit, and logic low indicates normal operation. As an input, logic high places Logic Input/Output all outputs in a high impedance state and logic low disables the cycle-by-cycle current limit function. SA53 P r o d u c t I n n o v a t i o nF r o m Table 1. Pin Descriptions Pin # 5,9,11,13 15 17 19 21 23 25 46,47,48,49 33,34,35 37,38,39,40 26,27,58,59 2,4,6,8,10, 12,14,16,18, 20,22,24,28, 32,36,41,42, 43,44,45,50, 54,60,62,64 Pin Name Signal Type Simplified Pin Description SGND 1b 1t VDD I1 DIS2 TEMP VS (phase 2) OUT 1 PGND (phase 1) HS Power Logic Input Logic Input Power Analog Output Logic Input Logic Output Power Power Output Power Mechanical Analog and digital GND – internally connected to PGND Logic high commands 1 phase lower FET to turn on Logic high commands 1 phase upper FET to turn on Logic Supply (5V) Phase 1 current sense output Logic high places all outputs in a high impedance state Thermal indication of die temperature above 135ºC High Voltage Supply phase 2 Half Bridge 1 Power Output High Current GND Return Path for Power Outputs 1&2 Pins connected to the package heat slug NC --- Do Not Connect 1.2 Pin Descriptions VS: Supply voltage for the output transistors. These pins require decoupling (1μF capacitor with good high frequency characteristics is recommended) to the PGND pins. The decoupling capacitor should be located as close to the VS and PGND pins as possible. Additional capacitance will be required at the VS pins to handle load current peaks and potential motor regeneration. Refer to the applications section of this datasheet for additional discussion regarding bypass capacitor selection. Note that VS pins 29-31 carry only the phase 1 supply current. Pins 46-49 carry supply current for phase 2. Phase 1 may be operated at a different supply voltage from phase 2. Both VS voltages are monitored for undervoltage conditions. OUT 1, OUT 2: These pins are the power output connections to the load. NOTE: When driving an inductive load, it is recommended that two Schottky diodes with good switching characteristics (fast tRR specs) be connected to each pin so that they are in parallel with the parasitic back-body diodes of the output FETs. (See Section 2.6) PGND: Power Ground. This is the ground return connection for the output FETs. Return current from the load flows through these pins. PGND is internally connected to SGND through a resistance of a few ohms. See section 2.1 of this datasheet for more details. SC: Short Circuit output. If a condition is detected on any output which is not in accordance with the input commands, this indicates a short circuit condition and the SC pin goes high. The SC signal is blanked for approximately 200ns during switching transitions but in high current applications, short glitches may appear on the SC pin. A high state on the SC output will not automatically disable the device. The SC pin includes an internal 12kΩ series resistor. 1b, 2b: These Schmitt triggered logic level inputs are responsible for turning the associated bottom, or lower Nchannel output FETs on and off. Logic high turns the bottom N-channel FET on, and a logic low turns the low side N-channel FET off. If 2b or 2b is high at the same time that a corresponding 1t or 2t input is high, protection circuitry will turn off both FETs in order to prevent shoot-through on that output phase. Protection circuitry also includes a dead-time generator, which inserts dead time in the outputs in the case of simultaneous switching of the top and bottom input signals. 1t, 2t: These Schmitt triggered logic level inputs are responsible for turning the associated top side, or upper Pchannel FET outputs on and off. Logic high turns the top P-channel FET on, and a logic low turns the top Pchannel FET off. SA53U SA53 P r o d u c t I n n o v a t i o nF r o m I1, I2: Current sense pins. The SA53 supplies a positive current to these pins which is proportional to the current flowing through the top side P-channel FET for that phase. Commutating currents flowing through the backbody diode of the P-channel FET or through external Schottky diodes are not registered on the current sense pins. Nor do currents flowing through the low side N-channel FET, in either direction, register at the current sense pins. A resistor connected from a current sense pin to SGND creates a voltage signal representation of the phase current that can be monitored with ADC inputs of a processor or external circuitry. The current sense pins are also internally compared with the current limit threshold voltage reference, Vth. If the voltage on any current sense pin exceeds Vth, the cycle by cycle current limit circuit engages. Details of this functionality are described in the applications section of this datasheet. ILIM/DIS1: This pin is directly connected to the disable circuitry of the SA53. Pulling this pin to logic high places OUT 1 and OUT 2 in a high impedance state. This pin is also connected internally to the output of the current limit latch through a 12kΩ resistor and can be monitored to observe the function of the cycle-by-cycle current limit feature. Pulling this pin to a logic low effectively disables the cycle-by-cycle current limit feature. SGND: This is the ground return connection for the VDD logic power supply pin. All internal analog and logic circuitry is referenced to this pin. PGND is internally connected to GND through a resistance of a few ohms,. However, it is highly recommended to connect the GND pin to the PGND pins externally as close to the device as possible. Failure do to this may result in oscillations on the output pins during rising or falling edges. VDD: This is the connection for the 5V power supply, and provides power for the logic and analog circuitry in the SA53. This pin requires decoupling (at least 0.1μF capacitor with good high frequency characteristics is recommended) to the SGND pin. DIS2: The DIS2 pin is a Schmitt triggered logic level input that places OUT 1 and OUT 2 in a high impedance state when pulled high. DIS2 has an internal 12kΩ pull-down resistor and may therefore be left unconnected. TEMP: This logic level output goes high when the die temperature of the SA53 reaches approximately 135ºC. This pin WILL NOT automatically disable the device. The TEMP pin includes a 12kΩ series resistor. HS: These pins are internally connected to the thermal slug on the reverse of the package. They should be connected to GND. Neither the heat slug nor these pins should be used to carry high current. NC: These “no-connect” pins should be left unconnected. 2. SA53 OPERATION The SA53 is designed primarily to drive DC brush motors. However, it can be used for any application requiring two high current outputs. The signal set of the SA53 is designed specifically to interface with a DSP or microcontroller. A typical system block diagram is shown in the figure below. Over-temperature, Short-Circuit and Current Limit fault signals provide important feedback to the system controller which can safely disable the output drivers in the presence of a fault condition. High side current monitors for both phases provide performance information which can be used to regulate or limit torque. SA53U SA53 P r o d u c t I n n o v a t i o nF r o m Figure 4. System Diagram Vs + VDD SC TEMP ILIM/D IS 1 Vs 1 Vs 2 Fault Logic Current I1 monitor I2 Signals GND DC BRUSH MOTOR D IS 2 1t 1b Control Logic PWM Signals Gate Control OUT 1 1 2 OUT 2 2t 2b SGND SA53 Switching Amplifier M icrocontroller or DSC SGND PGND 2 PGND 1 GND SA53U SA53 P r o d u c t I n n o v a t i o nF r o m The block diagram in Figure 5 illustrates the features of the input and output structures of the SA53. For simplicity, a single phase is shown. Figure 5. Input and output structures for a single phase 12k SC Current Sense SC Logic Vdd I1' Temp Sense Ref Lim 1 12k I LIM/DIS1 Vth + _ _ + 12k TEMP Lim 2 I1 UVLO DIS2 12k Vs 1t Gate Control OUT 1 1b PGND SGND X X >Vth X X X X X X X X X X X X SA53U Dis2 OUT 1 OUT 2 I1, I2 0 X 1 <Vth 0 <Vth 1 X ILIM/Dis1 0 0 1 1 1b, 2b 1t, 2t TABLE 2. Truth Table X 0 0 X X 0 0 X High-Z PGND VS High-Z Comments Top and Bottom output FETs for that phase are turned off. Bottom output FET for that phase is turned on. Top output FET for that phase is turned on. Both output FETs for that phase are turned off. Voltage on I1 or I2 has exceeded Vth, which causes ILim/Dis1 to go high. 1 X High-Z This internally disables Top and Bottom output FETs for ALL phases. X 1 High-Z Dis2 pin pulled high, which disables all outputs. Pulled Pulling the ILim/Dis1 pin high externally acts as a second disable input, X High-Z High which disables ALL output FETs. Determined Pulling the Dis2 pin low externally disables the cycle-by-cycle current limit Pulled 0 by PWM function. The state of the outputs is strictly a function of the PWM inputs. Low inputs X X High-Z If VS is below the UVLO threshold all output FETs will be disabled. SA53 P r o d u c t I n n o v a t i o nF r o m 2.1 LAYOUT CONSIDERATIONS Output traces carry signals with very high dV/dt and dI/dt. Proper routing and adequate power supply bypassing ensures normal operation. Poor routing and bypassing can cause erratic and low efficiency operation as well as ringing at the outputs. The VS supply should be bypassed with a surface mount ceramic capacitor mounted as close as possible to the VS pins. Total inductance of the routing from the capacitor to the VS and GND pins must be kept to a minimum to prevent noise from contaminating the logic control signals. A low ESR capacitor of at least 25μF per ampere of output current should be placed near the SA53 as well. Capacitor types rated for switching applications are the only types that should be considered. The bypassing requirements of the VDD supply are less stringent, but still necessary. A 0.1μF to 0.47μF surface mount ceramic capacitor (X7R or NPO) connected directly to the VDD pin is sufficient. SGND and PGND pins are connected internally. However, these pins must be connected externally in such a way that there is no motor current flowing in the logic and signal ground traces as parasitic resistances in the small signal routing can develop sufficient voltage drops to erroneously trigger input transitions. Alternatively, a ground plane may be separated into power and logic sections connected by a pair of back to back Schottky diodes. This isolates noise between signal and power ground traces and prevents high currents from passing between the plane sections. Unused area on the top and bottom PCB planes should be filled with solid or hatched copper to minimize inductive coupling between signals. The copper fill may be left unconnected, although a ground plane is recommended. 2.2 FAULT INDICATIONS In the case of either an over-temperature or short circuit fault, the SA53 will take no action to disable the outputs. Instead, the SC and TEMP signals are provided to an external controller, where a determination can be made regarding the appropriate course of action. In most cases, the SC pin would be connected to a FAULT input on the processor, which would immediately disable its PWM outputs. The TEMP fault does not require such an immediate response, and would typically be connected to a GPIO, or Keyboard Interrupt pin of the processor. In this case, the processor would recognize the condition as an external interrupt, which could be processed in software via an Interrupt Service Routine. The processor could optionally bring all inputs low, or assert a high level to either of the disable inputs on the SA53. Figure 6 shows an external SR flip-flop which provides a hard wired shutdown of all outputs in response to a fault indication. An SC or TEMP fault sets the latch, pulling the disable pin high. The processor clears the latched condition with a GPIO. This circuit can be used in safety critical applications to remove software from the fault-shut- Figure 6. External Fault Latch Circuit down loop, or simply to reduce processor overhead. PWM In applications which may not have available GPIO, the TEMP pin may be externally connected to the SC SA53 adjacent DIS1 pin. If the device temperature reachDIS2 TEMP es ~135ºC all outputs will be disabled, de-energizing PROCESSOR the motor. The SA53 will re-energize the motor when the device temperature falls below approximately FAULT RESET GPIO 95ºC. The TEMP pin hysteresis is wide to reduce the likelihood of thermal oscillations which can greatly LATCHED FAULT INTERRUPT reduce the life of the device. 2.3 UNDER-VOLTAGE LOCKOUT The undervoltage lockout condition results in the SA53 unilaterally disabling all output FETs until VS is above the UVLO threshold indicated in the spec table. There is no external signal indicating that an undervoltage lock- out condition is in progress. The SA53 has two VS connections: one for phase 1 and another for phase 2. The supply voltages on these pins need not be the same, but the UVLO will engage if either is below the threshold. Hysteresis on the UVLO circuit prevents oscillations with typical power supply variations. 10 SA53U SA53 P r o d u c t I n n o v a t i o nF r o m 2.4 CURRENT SENSE External power shunt resistors are not required with the SA53. Forward current in each top, Pchannel output FET is measured and mirrored to the respective current sense output pin, Ia, Ib and Ic. By connecting a resistor between each current sense pin and a reference, such as ground, a voltage develops across the resistor that is proportional to the output current for that phase. An ADC can monitor the voltages on these resistors for protection or for closed loop torque control in some application configurations. The current sense pins source current from the VDD supply. Headroom required for the current sense circuit is approximately 0.5V. The nominal scale factor for each proportional output current is shown in the typical performance plot on page 4 of this datasheet. 2.5 CYCLE-BY-CYCLE CURRENT LIMIT Figure 7. Start-up Voltage and Current NON-LIMITED MOTOR CURRENT NON-LIMITED BACK EMF LIMITED BACK EMF LIMITED MOTOR CURRENT TIME In applications where the current in the motor is not directly controlled, both the average current rating of the motor and the inrush current must be considered when selecting a proper amplifier. For example, a 1A continuous motor might require a drive amplifier that can deliver well over 10A peak in order to survive the inrush condition at startup. Because the output current of each upper output FET is measured, the SA53 is able to provide a very robust current limit scheme. This enables the SA53 to safely and easily drive virtually any DC brush motor through a startup inrush condition. With limited current, the starting torque and acceleration are also limited. The plot in Figure 7 shows starting current and back EMF with and without current limit enabled. If the voltage of any of the two current sense pins exceeds the current limit threshold voltage (Vth), all outputs are disabled. After all current sense pins fall below the Vth threshold voltage AND the offending phase’s top side input goes low, the output stage will return to an active state on the rising edge of ANY top side input command signal (1t or 2t). With most commutation schemes, the current limit will reset each pwm cycle. This scheme regulates the peak current in each phase during each pwm cycle as illustrated in the timing diagram below. The ratio of average to peak current depends on the inductance of the motor winding, the back EMF developed in the motor, and the width of the pulse. Figure 8 illustrates the current limit trigger and reset sequence. Current limit engages and ILIM/DIS1 goes high when any current sense pin exceeds Vth. Notice that the moment at which the current sense signal exceeds the Vth threshold is asynchronous with respect to the input PWM signal. The difference between the PWM period and the motor winding L/R time constant will often result in an audible beat frequency sometimes called a sub-cycle oscillation. This oscillation can be seen on the ILIM/DIS1 pin waveform in Figure 8. Input signals commanding 0% or 100% duty cycle may be incompatible with the current limit feature due to the absence of rising edges of 1t and 2t except when commutating phases. At high RPM, this may result in poor performance. At low RPM, the motor may stall if the current limit trips and the motor current reaches zero without a commutation edge which will typically reset the current limit latch. The current limit feature may be disabled by tying the ILIM/Dis1 pin to GND. The current sense pins will continue to provide top FET output current information. SA53U 11 SA53 P r o d u c t I n n o v a t i o nF r o m Typically, the current sense pins source current into grounded resistors which provide voltages to the current limit comparators. If instead the current limit resistors are connected to a voltage output DAC, the current limit can be controlled dynamically from the system controller. This technique essentially reduces the current limit threshold voltage to (Vth-VDAC). During expected conditions of high torque demand, such as start-up or reversal, the DAC can adjust the current limit dynamically to allow periods of high current. In normal operation when low current is expected, the DAC output voltage can increase, reducing the current limit setting to provide more conservative fault protection. Figure 8. Current Limit Waveforms It INPUT Vth I1 OUT 1 2.6 EXTERNAL FLYBACK DIODES External fly-back diodes will offer superior reverse recovery characteristics and low- ILIM/DIS1 er forward voltage drop than the internal back-body diodes. In high current applications, external flyback diodes can reduce power dissipation and heating during commutation of the motor current. Reverse recovery time and capacitance are the most important parameters to consider when selecting these diodes. Ultra-fast rectifiers offer better reverse recovery time and Schottky diodes typically have low capacitance. Individual application requirements will be the guide when determining the need for these diodes and for selecting the component which is most suitable. 12 Figure 9. Schottky Diodes VS VS OUT 1 SA53 OUT 2 SA53U SA53 P r o d u c t I n n o v a t i o nF r o m Figure 10. Timing Diagrams TOP INPUT BOTTOM INPUT DISABLE OUTPUT td(fall) DELAY TIMING td(rise) 3. POWER DISSIPATION td(dis) td(dis) td(dis) td(dis) Figure 11. OUTPUT RESPONSE The thermally enhanced package of the SA53 allows several options for managing the power dissi80% pated in the three output stages. Power dissipation in traditional PWM applications is a combination of output power dissipation and switching losses. OUTPUT Output power dissipation depends on the quadrant of operation and whether external flyback diodes 20% are used to carry the reverse or commutating currents. Switching losses are dependent on the frequency of the PWM cycle as described in the typical performance graphs. The size and orientation of the heatsink must be selected to manage the average power dissipation t(rise) t(fall) of the SA53. Applications vary widely and various thermal techniques are available to match the required performance. The patent pending mounting TOP INPUT technique shown in Figure 12, with the SA53 inverted and suspended through a cutout in the PCB BOTTOM INPUT is adequate for power dissipation up to 17W with the HS33, a 1.5 inch long aluminum extrusion with four fins. In free air, mounting the PCB perpendicular to the ground, such that the heated air flows upward along the channels of the fins can provide a total ΘJA of less than 14 ºC/W (9W max average PD). Mounting the PCB parallel to the ground impedes the flow of heated air and provides a ΘJA of 16.66 ºC/W (7.5W max average PD). In applications in which higher power dissipation is expected or lower junction or case temperatures are required, a larger heatsink or circulated air can significantly improve the performance. 4. ORDERING AND PRODUCT STATUS INFORMATION MODEL TEMPERATURE PACKAGE PRODUCTION STATUS SA53-IHZ -25 to 85ºC 64 pin Power QFP (HQ package drawing) Samples Available 1Q09 SA53U 13 SA53 P r o d u c t I n n o v a t i o nF r o m Figure 12. Heatsink Technique Patent Pending Contacting Cirrus Logic Support For all Apex Precision Power product questions and inquiries, call toll free 800-546-2739 in North America. For inquiries via email, please contact [email protected]. International customers can also request support by contacting their local Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). 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