MM54HC123A/MM74HC123A Dual Retriggerable Monostable Multivibrator General Description The MM54/74HC123A high speed monostable multivibrators (one shots) utilize advanced silicon-gate CMOS technology. They feature speeds comparable to low power Schottky TTL circuitry while retaining the low power and high noise immunity characteristic of CMOS circuits. Each multivibrator features both a negative, A, and a positive, B, transition triggered input, either of which can be used as an inhibit input. Also included is a clear input that when taken low resets the one shot. The ’HC123 can be triggered on the positive transition of the clear while A is held low and B is held high. The ’HC123A is retriggerable. That is it may be triggered repeatedly while their outputs are generating a pulse and the pulse will be extended. Pulse width stability over a wide range of temperature and supply is achieved using linear CMOS techniques. The out- put pulse equation is simply: PW e (REXT) (CEXT); where PW is in seconds, R is in ohms, and C is in farads. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Features Y Y Y Y Y Y Y Y Y Typical propagation delay: 25 ns Wide power supply range: 2V – 6V Low quiescent current: 80 mA maximum (74HC Series) Low input current: 1 mA maximum Fanout of 10 LS-TTL loads Simple pulse width formula T e RC Wide pulse range: 400 ns to % (typ) Part to part variation: g 5% (typ) Schmitt Trigger A & B inputs enable infinite signal input rise and fall times. Connection Diagram Timing Component Dual-In-Line Package Note: Pin 6 and Pin 14 must be hard-wired to GND. TL/F/5206 – 2 TL/F/5206 – 1 Top View Order Number MM54HC123A or MM74HC123A Truth Table Inputs H e High Level Outputs L e Low Level Clear A B Q Q L X X H H X H X L X X L v u L L L L É É É H H H ß ß ß u H H C1995 National Semiconductor Corporation TL/F/5206 ue ve Transition from Low to High Transition from High to Low Ée One High Level Pulse ße One Low Level Pulse X e Irrelevant RRD-B30M105/Printed in U. S. A. MM54HC123A/MM74HC123A Dual Retriggerable Monostable Multivibrator January 1988 Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) b 0.5V to a 7.0V Supply Voltage (VCC) b 1.5V to VCC a 1.5V DC Input Voltage (VIN) b 0.5V to VCC a 0.5V DC Output Voltage (VOUT) g 20 mA Clamp Diode Current (IIK, IOK) g 25 mA DC Output Current, per pin (IOUT) g 50 mA DC VCC or GND Current, per pin (ICC) b 65§ C to a 150§ C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Lead Temperature (TL) (Soldering 10 seconds) 260§ C Operating Temp. Range (TA) MM74HC MM54HC Min 2 Max 6 0 VCC Units V V b 40 b 55 a 85 a 125 §C §C 1000 500 400 ns ns ns Input Rise or Fall Times (Clear Input) VCC e 2.0V (tr, tf) VCC e 4.5V VCC e 6.0V DC Electrical Characteristics (Note 4) Symbol Parameter Conditions VCC TA e 25§ C Typ 74HC TA eb40 to 85§ C 54HC TA eb55 to 125§ C Units Guaranteed Limits VIH Minimum High Level Input Voltage 2.0V 4.5V 6.0V 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V V V VIL Maximum Low Level Input Voltage 2.0V 4.5V 6.0V 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V V V VOH Minimum High Level Output Voltage VIN e VIH or VIL lIOUTl s 20 mA 2.0V 4.5V 6.0V 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V V V 4.5V 6.0V 4.2 5.7 3.98 5.48 3.84 5.34 3.7 5.2 V V V 2.0V 4.5V 6.0V 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V V V VIN e VIH or VIL lIOUTl s4 mA lIOUTl s5.2 mA 4.5V 6.0V 0.2 0.2 0.26 0.26 0.33 0.33 0.4 0.4 V V V VIN e VIH or VIL lIOUTl s 4.0 mA lIOUTl s 5.2 mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA IIN Maximum Input Current (Pins 7, 15) VIN e VCC or GND 6.0V g 0.5 g 5.0 g 5.0 mA IIN Maximum Input Current (all other pins) VIN e VCC or GND 6.0V g 0.1 g 1.0 g 1.0 mA ICC Maximum Quiescent Supply Current (standby) VIN e VCC or GND IOUT e 0 mA 6.0V 8.0 80 160 mA ICC Maximum Active Supply Current (per monostable) VIN e VCC or GND R/CEXT e 0.5VCC 2.0V 4.5V 6.0V 80 1.0 2.0 110 1.3 2.6 130 1.6 3.2 mA mA mA 36 0.33 0.7 Note 1: Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation Temperature Derating: Plastic ‘‘N’’ Package: b 12mW/§ C from 65§ C to 85§ C Ceramic ‘‘J’’ Package: b 12mW/§ C from 100§ C to 125§ C. Note 4: For a power supply of 5V g 10% the worst-case output voltages (VOH, VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst-case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst-case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 2 AC Electrical Characteristics VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns Symbol Parameter Conditions Typ Limit Units tPLH Maximum Trigger Propagation Delay A, B or Clear to Q 22 33 ns tPHL Maximum Trigger Propagation Delay A, B or Clear to Q 25 42 ns tPHL Maximum Propagation Delay, Clear to Q 20 27 ns tPLH Maximum Propagation Delay, Clear to Q 22 33 ns tW Minimum Pulse Width, A, B or Clear 14 26 ns tREM Minimum Clear Removal Time 0 ns tWQ(MIN) Minimum Output Pulse Width CEXT e 28 pF REXT e 2 kX tWQ Output Pulse Width CEXT e 1000 pF REXT e 10 kX 400 ns 10 ms AC Electrical Characteristics CL e 50 pF tr e tf e 6 ns (unless otherwise specified) Symbol Parameter Conditions VCC TA e 25§ C Typ 74HC 54HC TA eb40 to 85§ C TA eb55 to 125§ C Units Guaranteed Limits tPLH Maximum Trigger Propagation Delay, A, B or Clear to Q 2.0V 77 4.5V 26 6.0V 21 169 42 32 194 51 39 210 57 44 ns ns ns tPHL Maximum Trigger Propagation Delay, A, B or Clear to Q 2.0V 88 4.5V 29 6.0V 24 197 48 38 229 60 46 250 67 51 ns ns ns tPHL Maximum Propagation Delay Clear to Q 2.0V 54 4.5V 23 6.0V 19 114 34 28 132 41 33 143 45 36 ns ns ns tPLH Maximum Propagation Delay Clear to Q 2.0V 56 4.5V 25 6.0V 20 116 36 29 135 42 34 147 46 37 ns ns ns tW Minimum Pulse Width A, B, Clear 2.0V 57 4.5V 17 6.0V 12 123 30 21 144 37 27 157 42 30 ns ns ns tREM Minimum Clear Removal Time 2.0V 4.5V 6.0V 0 0 0 0 0 0 0 0 0 ns ns ns 2.0V 30 4.5V 8 6.0V 7 75 15 13 95 19 16 110 22 19 ns ns ns tTLH, tTHL Maximum Output Rise and Fall Time tWQ(MIN) Minimum Output Pulse Width CEXT e 28 pF REXT e 2 kX REXT e 6 kX (VCC e 2V) 2.0V 1.5 4.5V 450 6.0V 380 tWQ Output Pulse Width CEXT e 0.1 mF REXT e 10 kX Min 5.0V 1 0.9 0.86 0.85 ms Max 5.0V 1 1.1 1.14 1.15 ms ms ns ns CIN Maximum Input Capacitance (Pins 7 & 15) 12 20 20 20 pF CIN Maximum Input Capacitance (other inputs) 6 10 10 10 pF CPD Power Dissipation Capacitance (Note 5) 70 pF Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC. 3 Logic Diagram TL/F/5206 – 5 Theory of Operation TL/F/5206 – 6 j POSITIVE EDGE TRIGGER m POSITIVE EDGE RE-TRIGGER (PULSE LENGTHENING) k NEGATIVE EDGE TRIGGER n RESET PULSE SHORTENING l POSITIVE EDGE TRIGGER o CLEAR TRIGGER FIGURE 1 channel transistor N1 j . At the same time the output latch is set. With transistor N1 on, the capacitor CEXT rapidly discharges toward GND until VREF1 is reached. At this point the output of comparator C1 changes state and transistor N1 turns off. Comparator C1 then turns off while at the same time comparator C2 turns on. With transistor N1 off, the capacitor CEXT begins to charge through the timing re- TRIGGER OPERATION As shown in Figure 1 and the logic diagram before an input trigger occurs, the one shot is in the quiescent state with the Q output low, and the timing capacitor CEXT completely charged to VCC. When the trigger input A goes from VCC to GND (while inputs B and clear are held to VCC) a valid trigger is recognized, which turns on comparator C1 and N- 4 toward VCC. The Q output will remain high until time T, after the last valid retrigger. Because the trigger-control circuit flip-flop resets shortly after CX has discharged to the reference voltage of the lower reference circuit, the minimum retrigger time, trr is a function of internal propagation delays and the discharge time of CX: 187 565 a (0.256 VCC) CX a trr & 20 a [VCC b 0.7] 2 VCC b 0.7 Another removal/retrigger time occurs when a short clear pulse is used. Upon receipt of a clear, the one shot must charge the capacitor up to the upper trip point before the one shot is ready to receive the next trigger. This time is dependent on the capacitor used and is approximately: sistor, REXT, toward VCC. When the voltage across CEXT equals VREF2, comparator C2 changes state causing the output latch to reset (Q goes low) while at the same time disabling comparator C2. This ends the timing cycle with the monostable in the quiescent state, waiting for the next trigger. A valid trigger is also recognized when trigger input B goes from GND to VCC (while input A is at GND and input clear is at VCC k ). The ’HC123A can also be triggered when clear goes from GND to VCC (while A is at GND and B is at VCC o ). It should be noted that in the quiescent state CEXT is fully charged to VCC causing the current through resistor REXT to be zero. Both comparators are ‘‘off’’ with the total device current due only to reverse junction leakages. An added feature of the ’HC123A is that the output latch is set via the input trigger without regard to the capacitor voltage. Thus, propagation delay from trigger to Q is independent of the value of CEXT, REXT, or the duty cycle of the input waveform. trr e 196 a RESET OPERATION These one shots may be reset during the generation of the output pulse. In the reset mode of operation, an input pulse on clear sets the reset latch and causes the capacitor to be fast charged to VCC by turning on transistor Q1 n . When the voltage on the capacitor reaches VREF2, the reset latch will clear and then be ready to accept another pulse. If the clear input is held low, any trigger inputs that occur will be inhibited and the Q and Q outputs of the output latch will not change. Since the Q output is reset when an input low level is detected on the Clear input, the output pulse T can be made significantly shorter than the minimum pulse width specification. RETRIGGER OPERATION The ’HC123A is retriggered if a valid trigger occurs l followed by another trigger m before the Q output has returned to the quiescent (zero) state. Any retrigger, after the timing node voltage at the R/CEXT pin has begun to rise from VREF1, but has not yet reached VREF2, will cause an increase in output pulse width T. When a valid retrigger is initiated m , the voltage at the R/CEXT pin will again drop to VREF1 before progressing along the RC charging curve Typical Output Pulse Width vs. Timing Components 640 522 a (0.3 VCC) CX a ns VCC b 0.7 (VCC b 0.7)2 Typical Distribution of Output Pulse Width, Part to Part Typical 1ms Pulse Width Variation vs. Supply TL/F/5206 – 8 TL/F/5206–7 Minimum REXT vs. Supply Voltage TL/F/5206 – 9 Typical 1ms Pulse Width Variation vs. Temperature TL/F/5206 – 10 TL/F/5206 – 11 Note: R and C are not subjected to temperature. The C is polypropylene. 5 MM54HC123A/MM74HC123A Dual Retriggerable Monostable Multivibrator Physical Dimensions inches (millimeters) Dual-In-Line Package (J) Order Number MM54HC123AJ or MM74HC123AJ NS Package Number J16A Dual-In-Line Package (N) Order Number MM74HC123AN NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.