TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 D D D D D D D D Drive Capability and Output Counts – 80 mA (Current Sink) x 16 Bits Constant Current Output Range – 5 to 80 mA (Current Value Setting for All Output Terminals Using External Resistor and Internal Brightness Control Register) Constant Current Accuracy – ± 4 % (Maximum Error Between Bits) Voltage Applied to Constant Current Output Terminals – Minimum 0.4 V (Output Current 5 mA to 40 mA) – Minimum 0.7 V (Output Current 40 mA to 80 mA) 1024 Gray Scale Display – Pulse Width Control 1024 Steps Brightness Adjustment† – All Output Current Adjustment for 64 Steps (Adjustment for Brightness Deviation Between LED Modules) – Output Current Adjustment by Output (OUT0 to OUT15) for 128 Steps (Adjustment for Brightness Deviation Between Dots) – Brightness Control by 16 Steps Frequency Division Gray Scale Control Clock (Brightness Adjustment for Panel) Gray Scale Clock Generation – Gray Scale Control Clock Generation by Internal PLL or External Input Selectable Clock Invert/Noninvert Selectable at Cascade Operation – Clock Invert Selectable to Reduce Changes in Duty Ratio D D D D D D D D D D Protection – Watchdog Timer (WDT) Function (Turn Output Off When Scan Signal Stopped) – Thermal Shutdown (TSD) Function (Turn Output Off When Junction Temperature Exceeds Limit) LOD – LED Open Detection (Detection for LED Disconnection) Data Input/Output‡ – Port A (for Data Display) – Clock Synchronized 10 Bit Parallel Input (Schmitt-Triggered Input) – Clock Synchronized 10 Bit Parallel Output (3-State Output) – Port B (for Dot Correction Data) – Clock Synchronized 7 Bit Parallel Input (Schmitt-Triggered Input) – Clock Synchronized 7 Bit Parallel Output Input/Output Signal Level – CMOS Level Power Supply Voltage – 4.5 V to 5.5 V (Logic, Analog and Constant Current) – 3 V to 5.5 V (Interface) Maximum Output Voltage . . . 15 V Data Transfer Rate . . . 20 MHz (Max) Gray Scale Clock Frequency – 16 MHz (Max) Using Internal PLL – 8 MHz (Max) Using External Clock Operating Free-Temperature Range – 20°C to 85°C 100-Pin Package HTQFP (PD = 4.7 W, TA = 25°C) † Adjustable for these functions independently. ‡ Allows to write all the data at port A by setting. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 description The TLC5911 is a constant current driver incorporating shift register, data latch, and constant current circuitry with a current value adjustable, PLL circuitry for gray scale control clock generation, and 1024 gray scale display using pulse width control. The output current is maximum 80 mA with 16 bits, and the current value of constant current output can be set by one external resistor. The device has two channel I/O ports. The brightness deviation between LED modules (ICs) can be adjusted by external data input from the display data port, and the brightness control for the panel can be accomplished by the brightness adjustment circuitry. Independent of these functions, the device incorporates the shift register and data latch to correct the deviation between LEDs by adjusting the output current using data from the dot correction data port. Moreover, the device incorporates WDT circuitry, which turns constant current output off when the scan signal stops during the dynamic scanning operation, and TSD circuitry, which turns constant current output off when the junction temperature exceeds the limit. Also the LED open detection (LOD) circuitry is used to make error signal output at the LED disconnection. pin assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VCCLED XDWN2TST GNDANA XDPOUT WDCAP TSENA IREF VCCANA DCDOUT0 DCDOUT1 DCDOUT2 DCDOUT3 DCDOUT4 DCDOUT5 DCDOUT6 DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 DOUT8 DOUT9 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 GNDLED OUT0 OUT1 GNDLED OUT2 OUT3 GNDLED OUT4 OUT5 GNDLED OUT6 OUT7 GNDLED OUT8 OUT9 GNDLED OUT10 OUT11 GNDLED OUT12 OUT13 GNDLED OUT14 OUT15 GNDLED 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 TEST3 TEST2 GNDLOG TEST1 DPOL DCENA BCENA VCCLOG DCDIN6 DCDIN5 DCDIN4 DCDIN3 DCDIN2 DCDIN1 DCDIN0 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 PZP PACKAGE (TOP VIEW) 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCOIN RBIAS MAG0 MAG1 MAG2 PDOUT GSPOL GSCLK BLANK XENABLE XOE DCLK XLATCH DCCLK XDCLAT RSEL0 RSEL1 LEDCHK NC WDTRG XDOWN1 XDOWN2 BOUT XGSOUT XPOUT TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 functional block diagram XOE BCENA DCLK DPOL XENABLE DOUT(9–0) DCLK Control XDPOUT DIN(9–0), XLATCH 1 x 10 bit B.C. Data Shift Register Data Latch 16 x 10 bit Data Shift Register RSEL(1–0) DCDIN(6–0), XDCLAT, DCCLK .......... 8 16 x 10 bit Data Latch .......... MAG(2–0), GSPOL, GSCLK, RBIAS, VCOIN, PDOUT PLL 10 bit Clock Countor 16 x 10 bit Data Comparator BLANK WDCAP WDTRG .......... 16 bit LED Driver+LOD WDT LEDCHK XDOWN2TST .......... TSENA XPOUT XGSOUT BOUT OUT0 ··· OUT15 XDOWN1 XDOWN2 16 bit Current Controller TSD .......... IREF 16 x 7 bit D.C. Data Latch DCENA .......... 16 x 7 bit D.C. Data Shift Register DCDOUT(6–0) Legend: B.C. (Brightness Control): Adjustment for brightness deviation between LED modules, and between panels. D.C. (Dot Control): Adjustment for brightness deviation between dots. NOTE: All the input terminals are with Schmitt triggered inverter except RBIAS, VCOIN, PDOUT, IREF and WDCAP. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 functional block diagram for shift register and data latch XOE 10 16 DATA S/R DCLK DPOL XENABLE DCLK Controller a 10 16 DATA Comparator † A b B DCCLK 10 DATA LATCH a c 10 b A 10 L c 10 DIN(9–0) DOUT(9–0) HI–Z A 10 b DCDIN(6–0) 10 10 a B H 10 B.C. S/R 10 B.C. LATCH Clock Counter Current Controller c 7 a XLATCH XDCLAT A b B 7 c DCDOUT(6–0) ‡ 7 RSEL(1–0) D.C. S/R 7 16 D.C. LATCH 7 16 H L 7 16 BCENA Default DCENA † Connecting to 16th 10-bit Bus ‡ Connecting to 16th 7-bit Bus Legend: B.C. (Brightness Control): Adjustment for brightness deviation between LED modules, and between panels. D.C. (Dot Control): Adjustment for brightness deviation between dots. RSEL RSEL1 4 RSEL0 CONNECTION L L A – a, B – c L H A – b, B – c H L A–c H H INHIBIT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 16 DATA Comparator TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 equivalent input and output schematic diagrams Input DOUT0–9, DCDOUT0–6, XGSOUT, XPOUT, BOUT VCCIF VCCLOG OUTPUT INPUT GNDLOG GNDLOG OUTn XDOWN1, XDOWN2 XDOWN1, XDOWN2 OUTn GNDLOG GNDLED Terminal Functions ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TERMINAL NAME BCENA NO. 94 I/O DESCRIPTION I Brightness control enable. When BCENA is low, the brightness control latch is set to the default value. The output current value in this status is 100% of the value set by an external resistor. The frequency division ratio of GSCLK is1/1. When BCENA is high, writing to brightness control latch is enabled. BLANK 67 I Blank (Light off). When BLANK is high, all output of the constant current driver are turned off. When GSPOL is high, all the output is turned on (LED on) synchronizing to the falling edge of GCLK after next rising edge of GSCLK when BLANK goes from high to low. When GSPOL is low, all the output is turned on (LED on) synchronizing to the rising edge of GCLK after next falling edge of GSCLK when BLANK goes from high to low. BOUT 53 O BLANK buffered output DCCLK 62 I Clock input for data transfer. The input data is from DCDIN (port B) . The output data at DCDOUT. All data on the shift register for dot correction data from DCDIN is shifted by 1 bit and is synchronized to the rising edge of DCCLK. DCDIN0 – DCDIN6 86,87,88, 89,90,91,92 I Input for 7 bit parallel data (port B). These terminals are used as shift register input for dot correction data. DCDOUT0 – DCDOUT6 34,35,36, 37,38,39,40 O Output for 7 bit parallel data (port B). These terminals are used as shift register output for dot correction data. DCENA 95 I Latch enable for dot correction data. When DCENA is low, the latch is set to the default value. At this time, the output current value is 100% of the value set by an external resistor. DCLK 64 I Clock input for data transfer. The input data is from DIN (port A) , all the data on the shift register selected by RSEL0, 1 and the output data at DOUT are shifted by 1 bit and synchronized to DCLK. Note that whether synchronizing to the rising or falling edge of DCLK is dependent on the value of DPOL. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 Terminal Functions (Continued) ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TERMINAL NAME I/O DESCRIPTION DIN0 – DIN9 76,77,78,79,80, 81,82,83,84,85 I Input for 10 bit parallel data (port A). These terminals are inputs for shift register for gray scale data, brightness control, and dot correction data. The register selected is determined by RSEL0, 1. DOUT0 – DOUT9 41,42,43,44,45, 46,47,48,49,50 O Output for 10 bit parallel data (port A). These terminals are outputs for shift register for gray scale data, brightness control, and dot correction data. The register selected is determined by RSEL0, 1. DPOL 96 I Selects the valid edge of DCLK. When DPOL is high, the rising edge of DCLK is valid. When DPOL is low, the falling edge of DCLK is valid. GNDANA 28 Analog ground (Internally connected to GNDLOG and GNDLED) GNDLOG 98 Logic ground (Internally connected to GNDANA and GNDLED) GNDLED 1,4,7,10,13, 16,19,22,25 LED driver ground (Internally connected to GNDANA and GNDLED) GSCLK 68 I Clock input for gray scale. When MAG0 through MAG2 are all low, GSCLK is used for pulse width control. When MAG0 through MAG2 are not low, GSCLK is used for PLL timing control. The gray scale display is accomplished by lighting the LED until the number of GSCLK or PLL clocks counted is equal to the data latched. GSPOL 69 I Select the valid edge of GSCLK. When GSPOL is high, the rising edge of GSCLK is valid. When GSPOL is low, the falling edge of GSCLK is valid. IREF 32 I/O Constant current value setting. LED current is set to the desired value by connecting an external resistor between IREF and GND. The 38 times current is compared to current across the external resistor sink on the output terminal. LEDCHK 58 I LED disconnection detection enable. When LEDCHK is high, the LED disconnection detection is enabled and XDOWN2 is valid. When LEDCHK is low, the LED disconnection detection is disabled. 73,72,71 I PLL multiple ratio setting. The clock frequency generated by PLL referenced to GSCLK is set . MAG0 – MAG2 NC 57 No internal connection 2,3,5,6,8,9,11, 12,14,15,17,18, 20,21,23,24 O Constant current output PDOUT 70 I/O Resistor connection for PLL feedback adjustment RBIAS 74 I/O Resistor connection for PLL oscillation frequency setting OUT0 – DOUT15 60 59 I Input/output port selection and shift register data latch switching. When RSEL1 is low and RSEL0 is low, the gray scale data shift register latch is selected to port A, and the dot correction register latch is selected to port B. When RSEL1 is low and RSEL0 is high, the brightness control register latch is selected to port A, and the dot correction register latch is selected to port B. When RSEL1 is high and RSEL0 is low, the dot correction register latch is selected to port A and no register latch is selected to port B. TEST1 – TEST3 97,99,100 I TEST. Factory test terminal. These terminals should be connected to GND. THERMAL PAD Package bottom RSEL0 RSEL1 6 NO. Heat sink pad. This pad is connected to the lowest potential IC or thermal layer. TSENA 31 I TSD enable. When TSENA is high, TSD is enabled. When TSENA is low, TSD is disabled. VCCANA 33 Analog power supply voltage VCCLOG 93 Logic power supply voltage VCCLED 26 LED driver power supply voltage VCOIN 75 I/O Capacitance connection for PLL feedback adjustment WDCAP 30 I/O WDT detection time adjustment. WDT detection time is adjusted by connecting a capacitor between WDCAP and GND. When WDCAP is directly connected to GND, the WDT function is disabled. In this case, WDTRG should be tied to high or low level. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 Terminal Functions (Continued) ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TERMINAL NAME NO. I/O DESCRIPTION WDTRG 56 I WDT trigger input. By applying a scan signal to this terminal, the scan signal can be monitored by turning the constant current output off and protecting the LED from the damage of burning when the scan signal stops during the constant period designed. XDCLAT 61 I Data latch for dot correction. When XDCLAT is high, data on the shift register for dot correction data from DCDIN (port B) goes through latch. When XDCLAT is low, the data is latched. Accordingly, if data on the shift register is changed during XDCLAT high, the new value is latched (level latch). XDOWN1 55 O Shutdown. XDOWN1 is configured as open collector. It goes low when the constant current output is shut down by the WDT or TSD function. XDOWN2 54 O LED disconnection detection output. XDOWN2 is configured as open collector. XDOWN2 goes low when a LED disconnection is detected. XDPOUT 29 O DPOL output inverted XDWN2TST 27 I Test for XDOWN2. When XDWN2TST is low, XDOWN2 goes low. (This terminal is internally pulled up with 50 kΩ) XENABLE 66 I DCLK enable. When XENABLE is low, data transfer is enabled. Data transfer starts on the valid edge of DCLK after XENABLE goes low. During XENABLE high, no data is transferred. XGSOUT 52 O Clock output for gray scale. When MAG0 through MAG2 are all low, a clock with GSCLK inverted appears on this terminal. When MAG0 through MAG2 are not low., PLLCLK appears on this terminal. XLATCH 63 I Latch. When XLATCH is high, data on shift register from DIN (port A) goes through latch. When XLATCH is low, data is latched. Accordingly, if the data on the shift register is changed during XLATCH high, this new value is latched (level latch). XOE 65 I Data output enable. When XOE is low, the DOUT0–9 terminals are driven. When XOE is high, the DOUT0–9 terminals go to a high-impedance state. XPOUT 51 O GSPOL output inverted POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Logic supply voltage, VCC(LOG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Supply voltage for constant current circuit, VCC(LED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Analog supply voltage, VCC(ANA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Output current (DC), IOL(C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 mA Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCCLOG + 0.3 V Output voltage range, V(DOUT), V(DCDOUT), V(BOUT), V(XPOUT) and V(XGSOUT) – 0.3 V to VCCLOG + 0.3 V Output voltage range, VO and V(XDOWNn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 16 V Storage temperature range, Tstr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C Continuous total power dissipation at (or below) TA = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 W Power dissipation rating at (or above) TA = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38.2m W/°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GNDLOG terminal. recommended operating conditions ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ dc characteristics MIN NOM MAX UNIT Logic supply voltage, VCC(LOG) 4.5 5 5.5 V Supply voltage for constant current circuit, VCC(LED) 4.5 5 5.5 V Analog power supply, VCC(ANA) 4.5 5 5.5 V –0.3 0 0.3 V –0.3 0 0.3 V 15 V Voltage between VCC, V(DIFF1) Voltage between GND, V(DIFF2) Voltage applied to constant current output, VO V(DIFF1) = VCC(LOG) – VCC(ANA) VCC(LOG) – VCC(LED) VCC(ANA) – VCC(LED) V(DIFF2)= GND(LOG) – GND(ANA) GND(LOG) – GND(LED) GND(ANA) – GND(LED) OUT0 to OUT15 off High–level input voltage, VIH 0.8 VCC(LOG) Low–level input voltage, VIL VCC(LOG) 0.2 VCC(LOG) GND(LOG) VCC(LOG) = 4.5 V, DOUT0 to DOUT9, DCDOUT0 to DCDOUT5, BOUT, XGSOUT, XPOUT –1 Low–level output current, IOL VCC(LOG) = 4.5 V, DOUT0 to DOUT9, DCDOUT0 to DCDOUT5, BOUT, XGSOUT, XPOUT 1 Constant output current, IOL(C) V(CCLOG) = 4.5 V, XDOWN1, XDOWN2 OUT0 to OUT15 High–level output current, IOH Operating free–air temperature range, TA PLL resistor, R(BIAS) At 16 MHz oscillation PLL resistor, R(PD) 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V mA 5 –20 PLL capacitance, C(VCO) V 5 mA 80 mA 85 °C 1 µF 22 kΩ 30 kΩ TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 recommended operating conditions (continued) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á ÁÁÁ ÁÁ Á ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á ÁÁÁ ÁÁ Á ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ac characteristics, VCC(LOG)= VCC(ANA) = VCC(LED) = 4.5 V to 5.5 V, TA = – 20 to 85°C (unless otherwise noted) MIN DCLK DCCLK clock frequency, frequency f(DCLK)/f(DCCLK) DCLK, TYP MAX At single operation 20 At cascade operation 15 DCLK, DCCLK pulse duration (high- or low-level), tw(h)/tw(l) GSCLK clock frequency, f(GSCLK) 20 GSCLK pulse duration (high- or low-level), tw(h)/tw(l) 40 PLLCLK clock frequency, f(PLLCLK) WDT clock frequency, f(WDT) UNIT MHz ns 8 MHz 16 MHz 8 MHz ns WDT pulse duration (high- or low-level), tw(h)/tw(l) 40 ns XLATCH, XDCLAT pulse duration (high-level), tw(h) 30 ns Rise/fall time, tr/tf 100 ns Setup time, tsu DINn – DCLK DCDINn – DCCLK BLANK – GSCLK XENABLE – DCLK XLATCH – DCLK XLATCH – GSCLK XDCLAT – DCCLK RSEL – DCLK RSEL – DCCLK RSEL – XLATCH RSEL – XDCLAT 5 5 10 15 10 10 10 10 15 30 15 ns Hold time, th DINn – DCLK DCDINn – DCCLK XENABLE – DCLK XLATCH – DCLK XDCLAT – DCCLK RSEL – DCLK RSEL – DCCLK RSEL – XLATCH RSEL – XDCLAT 15 15 20 30 20 20 20 20 10 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 electrical characteristics, LEDCHK = L, MIN/MAX: VCC(LOG) = VCC(ANA) = VCC(LED) = 4.5 V to 5.5 V, TA = –20 to 85°C, TYP: VCC(LOG) = VCC(ANA) = VCC(LED) = 5 V, TA = 25°C (unless otherwise noted) ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á ÁÁÁ ÁÁ Á ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ PARAMETER TEST CONDITIONS MIN IOH = – 1 mA, DOUTn, DCOUTn, XGSOUT, XPOUT, BOUT VCC(LOG) – 0.5 VOH High-level output voltage VOL g Low-level output voltage IOL = 1 mA, DOUTn, DCOUTn, XGSOUT, XPOUT, BOUT Input current IOL = 5 mA, XDOWN1, XDOWN2 VI = VCC(LOG) or GND(LOG) II I(LOG) I(ANA) I(LED) Supply current (logic) Supply current (analog) Supply current (constant current driver) TYP MAX UNIT V 0.5 V 0.5 ±1 µA Input signal is static, TSENA = H, WDCAP = OPEN, No PLL is used 1 mA Input signal is static, TSENA = H, WDCAP = OPEN, PLL multiple ratio = 1042 3 mA Data transfer, DCLK = 20 MHz, GSCLK = 8 MHz No PLL is used 35 45 Data transfer, DCLK = 20 MHz, GSCLK = 15 kHz PLL multiple ratio = 1042 39 49 BLANK = L, R(IREF) = 1200 Ω 6.5 8 BLANK = L, R(IREF) = 600 Ω 13 15 LED turn off, R(IREF) = 1200 Ω 12 20 LED turn off, R(IREF) = 600 Ω 20 35 VO = 1 V, R(IREF) = 1200 Ω all output bits turn on 12 20 VO = 1 V, R(IREF) = 600 Ω all output bits turn on 20 35 mA mA mA IOL(C1) Constant output current (includes error between bits) VO = 1 V, V(IREF) = 1.2 V, R(IREF) = 1200 W 35 40 45 mA IOL(C2) Constant output current (includes error between bits) VO = 0.7 V, V(IREF) = 1.2 V R(IREF) = 600 W 70 80 90 mA OUT0 to OUT15 (VOUTn = 15 V) 0.1 µA XDOWN1, 2 (VXDOWNn = 15 V) 1 µA DOUTn, DCDOUTn (VOUTn = VCCLOG or GND) 1 µA IOL(K) Constant out output ut leakage current ∆IOL(C) Constant output current error between bit VCC(LOG)=VCC(ANA)=VCC(LED) VO = 1 V, R(IREF) = 600 W All output bits turn on ± 1% ± 4% I∆OL(C1) Changes in constant output current depend on supply voltage VO = 1 V, R(IREF) = 600 W, VIREF = 1.2 V ± 1% ± 4% V I∆OL(C2) Changes in constant output current depend on output voltage VO = 1 V to 3 V, R(IREF) = 600 Ω, VIREF = 1.2 V, 1 bit output turn on ± 1% ± 3% V T(tsd) T(wdt) TSD detection temperature Junction temperature 150 160 170 °C WDT detection temperature No external capacitor 5 10 15 ms V(IREF) Voltage reference BCENA = L, R(IREF) = 9.6 kΩ, V(LEDDET) Voltage applied to LED disconnection detection P(LLJITTER) PLL jitter 10 1.2 0.2 R(BIAS) = 22 kΩ, R(PD) = 30 kΩ, C(VCO) = 0.1 µF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V 0.3 0.4 0.4% 2% V TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 switching characteristics, CL = 15 pF, MIN/MAX: VCC(LOG) = VCC(ANA) = VCC(LED) = 4.5 V to 5.5 V, TA = –20 to 85°C, TYP: VCC(LOG) = VCC(ANA) = VCC(LED) = 5 V, TA = 25°C (unless otherwise noted) ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ Á ÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ Á ÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ Á ÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ PARAMETER TEST CONDITIONS MIN DOUTn, DCDOUTn tr tf Rise time Fall time XGSOUT, BOUT, XPOUT 30 12 30 110 DOUTn, DCDOUTn 10 30 10 30 XGSOUT, BOUT, XPOUT 30 45 BLANK↑ – OUT0 40 50 70 BLANK – BOUT 10 20 40 GSCLK – OUT0 (see Note 2) ns ns 7 GSCLK – XGSOUT 10 20 40 DCLK – DOUTn 15 30 45 DCLK – DCDOUTn 15 30 45 DCCLK – DCDOUTn 15 30 45 XOE↓ – DOUTn (see Note 3) 10 20 35 XOE↑ – DOUTn (see Note 3) 10 15 25 RSEL – DOUTn 10 20 LEDCHK – XDOWN2 UNIT 130 OUTn+1 – OUTn Propagation delay time MAX 12 OUTn (see Figure 1) OUTn (see Figure 1) td TYP ns 40 1000 NOTES: 2. MAG0 to MAG2 are all low level. 3. Until DOUT is turned on (drive) or turned off (Hi-Z). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION VCC 51 Ω VCC IREF OUTn GND 600 Ω 15 pF Figure 1. Rise Time and Fall Time Test Circuit for OUTn VIH or VOH 100% VIH 90% 50% 10% VIL tr VIL or VOL 0% tf td 100% VIH 50% 100% 50% 0% VIL tw(h) 0% tw(l) Figure 2. Timing Requirements 12 VIH or VOH POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VIL or VOL TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 PRINCIPLES OF OPERATION setting for output constant current value On the constant current output terminals (OUT0–15), approximately 38 times the current which flows through the external resistor, R(IREF) (connected between IREF and GND), can flow. The external resistor value is calculated using the following equation: R(IREF) (Ω) ≅ 38 × 1.2 (V) / IOL(C)(A) where both BCENA and DCENA are low. Note that more current flows if IREF is connected to GND directly. constant output current operation The constant current output turns on (sink constant current), if GSPOL is high and if all the gray scale data latched into the gray scale latch is not zero on the falling edge of the gray scale clock after the next rising edge of the gray scale clock when BLANK goes from high to low. After that, the number of the falling edge is counted by the 10-bit gray scale counter. Then, the output counted corresponding to the gray scale data is turned off (stop to sink constant current). The gray scale clock can be selected, as discussed in later section, from GSCLK or by internal PLL circuitry. If the shift register for the gray scale is updated during XLATCH high, the data on the gray scale data latch is also updated affecting the number of the gray scale of constant current output. Accordingly, during the on-state of the constant current output, XLATCH should be kept at a low level and the gray scale data latch should be held. input/output port and shift register selection The TLC5911 supplies two parallel input ports such as DIN (10 bits : port A) and DCDIN (7 bits: port B). The DIN and DCDIN ports also supply DCLK and DCCLK for the shift clock, XLATCH and XDCLAT for latch, and DOUT and DCDOUT for output, respectively. The device has three kinds of shift register latchs such as the gray scale data, brightness control, and dot correction. The port and shift registers can be selected by RSEL0 and RSEL1. The selection of the shift registers will be done by RESL0 and RSEL1 as shown in Table 1. Note that the RSELn setting is done at DCLK low and DPOL high (DCLK is high when DPOL is low). When only port A is used, DCDIN, DCDOUT, DCCLK, and XDCLAT should be connected to GND. ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Table 1. Shift Register Latch Selection SELECTED SHIFT REGISTER LATCH PORT A RSEL1 PORT B RSEL0 DIN, DCLK, XLATCH, DOUT DCDIN, DCCLK, XDCLAT DCDOUT L L Gray scale data displayed Dot correction Dot correction L H Brightness control Dot correction Dot correction H L Dot correction (see Note 4) Not connected Dot correction H H N/A (inhibit) N/A (inhibit) N/A (inhibit) NOTE 4: Zero is output to DOUT7 through DOUT9. shift register latch for gray scale data The shift register latch for the gray scale data is configured with 16 × 10 bits. The gray scale data, configured with 10 bits, represents the time when constant current output is being turned on, and the data range is 0 to 1023 (00h to 3FFh). When the gray scale data is 0, the time is shortest, and the output is not turned on (light off). On the other hand, when the gray scale data is 1023, the time is longest, and it turns on during the time of the 1023 clocks from the gray scale clock. The configuration of the shift register and the latch for gray scale data is shown in Figure 3. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 PRINCIPLES OF OPERATION Latch for Gray Scale Data XLATCH OUT15 Data OUT14 Data OUT1 Data OUT0 Data (10 bits) (10 bits) (10 bits) (10 bits) 2nd byte DIN9 MSB DIN0 LSB 1st byte DIN9 MSB DIN0 LSB Shift Register for Gray Scale Data DOUT0 to 9 16th byte DIN9 MSB DIN0 LSB 15th byte DIN9 MSB DIN0 LSB DCLK DIN0 to 9 Figure 3. Relationship Between Shift Register and Latch for Gray Scale Data shift register latch for brightness control The shift register latch for brightness control is configured with 1 × 10 bits. Using the shift register latch for the brightness control, the division ratio of the gray scale clock can be set and the output current value on constant current output can be adjusted. When powered up, the latch data is indeterminate and the shift register is not initialized. When these functions are used, data should be written to the shift register latch prior to lighting-on (BLANK=L). Also, it is prohibited from rewriting the latch value for the brightness control when the constant current output is turned on. When these functions are not used, the latch value can be set to the default value setting of BCENA at low level (connect to GND). Also, DIN9 is assigned to the LSB of the reference current control to maintain compatibility with the TLC5901/02/03 family. The configuration of the shift register and the latch for brightness control is shown in Figure 4. Latch for Brightness Control Gray Scale Clock Division Ratio Data Set XLATCH 0 0 0 MSB Current Data Adjusted On Constant Current Output 0 1 LSB MSB 1 1 1 1 1 (see Note A) LSB Shift Register for Brightness Control DOUT0 to 9 DIN8 DATA DIN7 DATA DIN6 DATA DIN5 DATA DIN4 DATA DIN3 DATA DIN2 DATA DIN1 DATA DIN0 DATA DIN9 DATA DCLK DIN0 to 9 NOTE A: Indicates default value at BCENA low. Figure 4. Relationship Between Shift Register and Latch for Brightness Control shift register latch for dot correction The shift register latch for dot correction is configured with 16 × 7 bits. Using the shift register latch for dot correction, the current value on the constant current output can be set individually. When powered up, the latch data is indeterminate and the shift register is not initialized. When these functions are used, data should be written to the shift register latch prior to lighting-on (BLANK=L). Also, rewriting the latch value for dot correction when the constant current output is turned on is inhibited. When these functions are not used, the latch value can be set to the default value setting of DCENA at low level (connect to GND). The configuration of the shift register and the latch for dot correction is shown in Figure 5. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 PRINCIPLES OF OPERATION Latch for Dot Correction XDCLAT OUT15 Data OUT14 Data OUT1 Data OUT0 Data (7 bits) (7 bits) (7 bits) (7 bits) 2nd byte DCDIN6 MSB DCDIN0 LSB 1st byte DCDIN6 MSB DCDIN0 LSB Shift Register for Dot Correction DCDOUT0 to 6 16th byte DCDIN6 MSB DCDIN0 LSB 15th byte DCDIN6 MSB DCDIN0 LSB DCCLK DCDIN0 to 6 Using Port B (RSEL0=L or H, RSEL1=L) Latch for Dot Correction XLATCH OUT15 Data OUT14 Data OUT1 Data OUT0 Data (7 bits) (7 bits) (7 bits) (7 bits) 2nd byte DIN6 MSB DIN0 LSB 1st byte DIN6 MSB DIN0 LSB Shift Register for Dot Correction DOUT0 to 6 16th byte DIN6 MSB DIN0 LSB 15th byte DIN6 MSB DIN0 LSB DCLK DIN0 to 6 Using Port A (RSEL0=L, RSEL1=H) Figure 5. Relationship Between the Shift Register and the Latch for Dot Correction write data to shift register latch The shift register latch written is selected using the RSEL0 and RSEL1 terminal. At port A, the data is applied to the DIN data input terminal, clocked into the shift register and synchronized to the rising edge of DCLK after XENABLE is pulled low. At port B, the data is applied to the DCDIN data input terminal, clocked into the shift register, and synchronized to the rising edge of DCCLK. The shift register for the gray scale data is configured with 16 × 10 bits and the shift register for dot correction is configured with 16 × 7 bits resulting in sixteen times DCLK. The shift register for the brightness control is configured with 1 × 10 bits resulting in one times DCLK. At the number of DCLK input for each case, data can be written into the shift register. In this condition, when the XLATCH at port A or the XDCLAT at port B is pulled high, data in the shift register is clocked into the latch (data through). When the XLATCH at port A or XDCLAT at port B is pulled low, data is held (latch). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 PRINCIPLES OF OPERATION brightness control function By writing data into the brightness control latch, current on all the constant current outputs can be adjusted to control the variation of brightness between ICs. The division ratio for the gray scale clock can be set to control the variation of brightness for the total panel system. Furthermore, by writing data into the dot correction latch, current on each constant current output can be adjusted. output current adjustment on all constant current outputs – brightness adjustment between ICs By using the lower 6 bits of the brightness control latch, output current can be adjusted in 64 steps as 1 step of 0.8% of the current ratio between 100% and 50.8% when the output current is set to 100% of an external resistor (note that the current value is lower if the constant current output is corrected using the dot correction function). By using this function, the brightness control between modules (ICs) can be adjusted sending the desired data externally even if ICs are mounted on a print-circuit board. When BCENA is pulled low, the output current is set to 100%. ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ Table 2. Relative Current Ratio For Total Constant Current Output CURRENT RATIO % 20 (mA) 80 (mA) CODE VIREF (TYP) 50.8 10.2 40.6 MSB 000000 LSB 0.60 . . . . . . . . . . . . . . . . . . . . 99.2 19.8 79.7 20.0 80.0 111110 111111† 1.19 100 1.20 † BCENA is low. frequency division ratio setting for gray scale clock – panel brightness adjustment By using the upper 4 bits of the brightness control latch, the gray scale clock can be divided into 1/1 to 1/16. If the gray scale clock is set to 16 times the speed of frequency (1024×16=16384) during horizontal scanning time, the brightness can be adjusted in 16 steps by selecting the frequency division ratio. By using this function, the total panel brightness can be adjusted at once, and applied to the brightness of day or night. When BCENA is pulled low, the gray scale clock is not divided. When BCENA is pulled high, the brightness can be adjusted as shown in Table 3. ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Table 3. Relative Brightness Ratio For Total Constant Current Output CODE FREQUENCY DIVISION RATIO RELATIVE BRIGHTNESS RATIO (%) MSB 0000 LSB† 1/1 6.3 . . . . . . . . . . . . 1110 1/15 93.8 1111 1/16 100 † BCENA is low. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 PRINCIPLES OF OPERATION output current adjustment on each constant current output – LED brightness adjustment By using the dot correction latch, the output current on each constant current output can be adjusted in 128 steps as 1 step of 0.8% of the current ratio between 100% and 0% when the output current is set to 100% of an external resistor at 7Fh of the latched value and the lower 6 bits of the brightness control register. By using this function, the brightness deviation from the LED brightness variation can be minimized. When DCENA is pulled low, the output current is set to 100% without the dot correction. ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Table 4. Relative Current Ratio By Constant Current Output CODE CURRENT RATIO % MSB 0000000 LSB 0.0 IOL(C)=40 (mA) 0.0 . . . . . . . . . . . . 1111110 1111111† 99.2 39.7 100 40 † DCENA is low. clock edge selection The high speed clock signal is diminished due to the duty ratio change through the multiple stages of the IC or module as shown in Figure 6. IN A OUT IN A IN IN’ A A’ OUT OUT a) Propagate through multiple stages buffer with slow falling edge A’ OUT OUT’ b) Insert inverter between buffers Figure 6. Clock Edge Selection In Figure 6a, if the falling edge at the internal buffer is behind the rising edge, the clock will disappear if a multiple cascade connection is made. To resolve this problem, the duty ratio can be held unchanged using the connection as shown in Figure 6b if the valid clock edge can be selected (arrow in Figure 6). Note that the clock delay is not avoided even in this case. The device incorporates the clock edge selection function for each DCLK and GSCLK. By using this function, the falling edge or rising edge for the valid edge can be selected depending on the status of DPOL and GSPOL, thus the degradation for the duty ratio can be reduced. The relationship between each signal is shown in Table 5. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 PRINCIPLES OF OPERATION ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Table 5. Valid Edge For DCLK and GSCLK DPOL DCLK valid edge H DCLK↑ Operation at XENABLE = H Pull DCLK to low level L DCLK↓ Pull DCLK to high level GSPOL GSCLK valid edge PLL operation H GSCLK↑ Synchronize to the high level of DCLK L GSCLK↓ Synchronize to the low level of DCLK The device supplies the XPOUT and XGSOUT output terminals for the cascade operation which inverts GSPOL and GSCLK respectively. It also supplies the BOUT output terminal as a buffered BLANK to make timing easy with GSCLK and XGSOUT. gray scale clock generation When MAG<0:2> are all low, the clock input from the GSCLK terminal is used as the gray scale clock with no change, and except for this case the internal PLL generates the clock for the gray scale control clock. When using the PLL, the gray scale clock is generated by adjusting the clock to have the same number of pulses as the multiple ratio of the GSCLK reference period (when GSCLK and GSPOL are kept at the same level). The ratio in this case is determined depending on MAG0 through MAG2 as shown in Table 6. When using the PLL, the internal PLLCLK is clocked out at the XGSOUT terminal. Therefore, the clock can be utilized for other devices on the same print-circuit board. Note that the number of ICs connected is limited depending on the frequency. ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Table 6. PLL Multiple Ratio 18 MAG2 MAG1 MAG0 MULTIPLE RATIO XGSOUT L L L L H 1 (Signal to control GSCLK by GSPOL) 28+6(=262) Inverted GSCLK L L H L L H H H L L H L H H H L H H H 29+10(=522) 210+18(=1042) 211+34(=2082) 212+66(=4162) 213+130(=8322) 214+258(=16642) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PLLCLK (Gray scale clock is internally generated) TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 PRINCIPLES OF OPERATION gray scale clock generation (continued) MAG<2:0> Except all low level Except all low level GSPOL GSCLK XGSOUT PLLCLK Same number of pulse as ratio Same number of pulse as ratio a) GSPOL is low a) GSPOL is high Figure 7. Gray Scale Clock Generation The oscillation frequency bandwidth as referenced for the PLL can be set by an external resistor connected between RBIAS and GND. The relation between the external resistor and the oscillation frequency is shown in Table 7. ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Table 7. PLL Oscillation Frequency RBIAS 22 kΩ 30 kΩ 62 kΩ 12 0kΩ FREQUENCY 13 to 16 MHz 8 to 14 MHz 4 to 9 MHz 3 to 5 MHz Note that it takes 30 ms for the PLL to be stabilized. Furthermore, to make the PLL operation stabilized, a resistor and a capacitor connection is required between VCOIN, PDOUT and GND. The recommended values are shown in the Figure 8. PDOUT VCOIN C(VCO) R(pd) Recommeded Value 0.1 to 1 µF R(pd) 22 to 62 kΩ C(VCO) Figure 8. Resistor and Capacitor Connection POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 PRINCIPLES OF OPERATION protection This device incorporates WDT and TSD functions. If the WDT or TSD functions, the constant current output is stopped and XDOWN1 goes low. Therefore, by monitoring the XDOWN1 terminal, these failures can be detected immediately. Since the XDOWN1 output is configured as open collector, outputs of multiple ICs are brought together. WDT (watchdog timer) The constant current output is forced to turn off and XDOWN1 goes low when the fixed period elapsed after the signal applied to WDTRG has not been changed. Therefore, by connecting a scan signal (a signal to the control line displayed) to WDTRG, the stop of the scan signal can be detected and the constant current output is turned off preventing the LED from burning and damage caused by continuous LED turn on at the dynamic scanning operation. The detection time can be set using an external capacitor, C1. The typical value is approximately 10 ms without capacitor, 160 ms with a1000 pF capacitor, and 1500 ms with a 0.01 µF capacitor. During static operation, the WDT function is disabled connecting the WDCAP to GND (high or low level should be applied to WDTRG). Note that normal operations will be resumed changing the WDTRG level when WDT functions. WDT operational time T (ms) ≅ 10 + 0.15 x C1 (pF) Time (ms) 1500 TLC5911 Scan Signal WDTRG WDCAP 160 C1 10 0 0.001 0.01 C1 – External Capacitor – µF Figure 9. WDT Operational Time and Usage Example TSD (thermal shutdown) When the junction temperature exceeds the limit, TSD functions and turns the constant current output off, and XDOWN1 goes low. When TSD is used, TSENA is pulled high. When TSD is not used, TSENA is pulled low. To recover from the constant current output off-state to normal operations, the power supply should be turned off or TSENA should be pulled low once. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 PRINCIPLES OF OPERATION LOD function (LED open detection) When LEDCHK is low, the LED disconnection detection function is disabled and XDOWN2 goes to a high-impedance state. When LEDCHK is high, the LED disconnection detection function is enabled, and XDOWN2 goes low if any LED is disconnected while monitoring the OUTn terminals to be turned on. This function is operational for sixteen OUTn terminals individually. To determine which constant current output is disconnected, the level of XDOWN2 is checked 16 times from OUT0 to OUT15 turning one constant current output on. The power supply voltage should be set so the constant current output applied is above 0.4 V when the LED is turned on normally. Also, since approximately 1000 ns is required from turning the constant current output on to XDOWN2 output, the gray scale data to be turned on during that period should be applied. Table 8 is an example of XDOWN2 output status using four LEDs . ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Table 8. XDOWN2 Output Example LED NUMBER 1 2 3 4 LED STATUS GOOD NG GOOD NG OUTn ON ON ON ON DETECTION RESULT GOOD NG GOOD NG XDOWN2 LOW (by case 2, 4) LED NUMBER 1 2 3 4 LED STATUS GOOD NG GOOD NG OUTn ON ON OFF OFF DETECTION RESULT GOOD NG GOOD GOOD XDOWN2 LOW (by case 2) LED NUMBER 1 2 3 4 LED STATUS GOOD NG GOOD NG OUTn OFF OFF OFF OFF DETECTION RESULT GOOD GOOD GOOD GOOD XDOWN2 HIGH-IMPEDANCE noise reduction concurrent switching noise reduction Concurrent switching noise has a potential to occur when multiple outputs turn on or off at the same time. To prevent this noise, the device has delay output terminals such as XGSOUT, BOUT for GSCLK (gray scale clock), and BLANK (blanking signal) respectively. By connecting these outputs to the GSCLK and BLANK terminals of next stage IC, it allows differences in the switching time between ICs. When GSCLK is output to GSOUT through the device, duty will be changed between input and output. The number of stages to be connected will be limited depending on the frequency. delay between constant current output The constant current output has a delay time of approximately 20 ns between outputs. It means approximately 300 ns delay time exists between OUT0 and OUT15. This time difference by delay is effective for the reduction of concurrent switching noise. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 PRINCIPLES OF OPERATION others power supply The following should be taken into consideration: D D VCCLOG, VCCANA and VCCLED should be supplied by a single power supply to minimize voltage differences between these terminals. The bypass capacitor should be located between the power supply and GND to eliminate the variation of power supply voltage. GND Although GNDLOG, GNDANA, and GNDLED are internally tied together, these terminals should be externally connected to reduce noise influence. thermal pad The thermal pad should be connected to GND to eliminate the noise influence, since it is connected to the bottom side of IC chip. Also, the desired thermal effect will be obtained by connecting this pad to the PCB pattern with better thermal conductivity. 4.7 3.2 2.3 1.48 0 –20 Output Voltage (Constant Current) – V PD – Total Power Dissipation – W power rating free-air temperature 0 0 25 85 TA – Free-Air Temperature – °C NOTES: A. The IC is mounted on PCB. PCB size : 102 × 76 × 1.6 [mm3], four layers with the internal two layers being plane. The thermal pad is soldered to the PCB pattern of 10 × 10 [mm2]. For operation above 25°C free-air temperature, derate linearly at the rate of 38.2 mW/°C. VCC(LOG)=VCC(ANA)=VCC(LED)=5 V, IOL(C) = 80 mA, ICC is a typical value. B. The thermal impedance will be varied depending on the mounting conditions. Since the PZP package established a low thermal impedance by radiating heat from the thermal pad, the thermal pad should be soldered to the pattern with a low thermal impedance. C. The material for the PCB should be selected considering the thermal characteristics since the temperature will rise around the thermal pad. Figure 10. Power Rating 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 PRINCIPLES OF OPERATION 90 80 70 IOL(C) – mA 60 50 40 30 20 10 0 0.1 1.0 10.0 R(IREF) (kΩ) Conditions : VO = 1 V, V(IREF) = 1.2 V ^ R (IREF)(kW) V I OL(C) R (mA) (IREF) (V) 38 (IREF) W (k ) ^I 46 OL(C) (mA) NOTE: The brightness control and dot corrected value are set at 100%. The resistor, R(IREF), should be located as close as possible to the IREF terminal to avoid noise influence. Figure 11. Current on Constant Current Output vs External Resistor POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 DPOL XOE XENABLE tsu(XENABLE–DCLK) 1/f(DCLK) th(XENABLE–DCLK) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DCLK tsu(DIN–DCLK) tw(l)(DCLK) tw(h)(DCLK) DIN0 D00_A D01_A D02_A D0E_A D0F_A D00_B D0D_B D0E_B D0F_B D00_C D01_C DIN9 D90_A D91_A D92_A D9E_A D9F_A D90_B D9D_B D9E_B D9F_B D90_C D91_C th(DIN–DCLK) th(XLATCH–DCLK) tsu(XLATCH–DCLK) XLATCH tw(h)(XLATCH) DOUT0 HI–Z D00_A D01_A D0E_A D0F_A D00_B DOUT9 HI–Z D90_A D91_A D9E_A D9F_A D90_B td(XOE↓–DOUT) td(DCLK–DOUT) DPOL DCLK DPOL and DCLK can be replaced with the combination of these signals enclosed by the parenthesis (Both are inverted each other). Figure 12. Timing Diagram (Shift Register for Gray Scale Data) td(XOE↑–DOUT) Template Release Date: 7–11–94 RSEL1 TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 24 RSEL0 BCENA RSEL0 tsu(RSEL–XLATCH) th(RSEL–XLATCH) RSEL1 XOE td(XOE↓–DOUT) DPOL POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 XENABLE tsu(RSEL–DCLK) tsu(RSEL–DCLK) DCLK DIN0 D0_A D0_B D0_C D0_J D0_K D0_L D0_M D0_N D0_O DIN9 D9_A D9_B D9_C D9_J D9_K D9_L D9_M D9_N D9_O th(XLATCH–DCLK) XLATCH tw(h)(XLATCH) BCL_0–5 Default Value 1 D<5:0>_A Default Value 1 D<9:6>_A Default Value 0 (Brightness Control Latch-Internal Signal) BCL_6–9 Default Value 0 td(XOE↑–DOUT) DOUT0 HI–Z D0_A D0_C D0_E D0_F D0_G D0_H D0_I DOUT9 HI–Z D9_A D9_C D9_E D9_F D9_G D9_H D9_I DPOL and DCLK can be replaced with signals inverted each other same as shift register for gray scale data. 25 Figure 13. Timing Diagram (Shift Register for Brightness Control) TLC5911 LED DRIVER td(DCLK–DOUT) SLLS402 – DECEMBER 1999 tsu(RSEL–DOUT) tsu(XENABLE–DCLK) RSEL1 tsu(RSEL–XDCLAT) th(RSEL–XDCLAT) tsu(RSEL–DCCLK) tsu(RSEL–DCCLK) DCCLK POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DCDIN0 D0_A D0_B D0_C D0_J D0_K D0_L D0_M D0_N D0_O DCDIN5 D5_A D5_B D5_C D5_J D5_K D5_L D5_M D5_N D5_O th(XDCLAT–DCCLK) XDCLAT tw(h)(XDCLAT) DCL_0–15 Default Value “1” Dx<15:0>_A (Note) (Dot Correction Latch-Internal Signal: 6 bit x 16) Default Value “1” td(DCCLK–DCDOUT) DCDOUT0 D0_A D0_C D0_E D0_F D0_G D0_H D0_I DCDOUT5 D5_A D5_C D5_E D5_F D5_G D5_H D5_I NOTE : Register value is immediately before DCLAT↓. Figure 14. Timing Diagram (Shift Register for Dot Correction: Using Port B) Template Release Date: 7–11–94 RSEL0 TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 26 DCENA RSEL0 RSEL1 tsu(RSEL–XLATCH) th(RSEL–XLATCH) XOE td(XOE↓–DOUT) DPOL XENABLE tsu(RSEL–DCLK) tsu(RSEL–DCLK) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DCLK DIN0 ... DIN9 D0_A D0_B D0_C D0_J D0_K D0_L D0_M D0_N D0_O D9_A D9_B D9_C D9_J D9_K D9_L D9_M ... D9_N D9_O th(XLATCH–DCLK) XLATCH tsu(RSEL–DOUT) DOUT0 DOUT5 td(XOE↑–DOUT) HI–Z D0_A D0_C D0_E D0_F D0_G D0_H D0_I HI–Z D5_A D5_C D5_E D5_F D5_G D5_H D5_I td(XOE↓–DOUT) HI–Z td(DCLK–DCDOUT) DCDOUT5 ... D0_A D0_C D0_E D0_F D0_G D0_H D0_I D5_A D5_C D5_E D5_F D5_G D5_H D5_I DPOL and DCLK can be replaced with signals inverted each other same as shift register for gray scale data. 27 Figure 15. Timing Diagram (Shift Register for Dot Correction: Using Port A) TLC5911 LED DRIVER DCDOUT0 SLLS402 – DECEMBER 1999 DOUT <9:6> tw(h)(XLATCH) td(DCLK–DOUT) BLANK GSPOL tsu(BLANK–GSCLK) 1/f(GSCLK) td(BLANK–OUT0) GSCLK 1/f(WDT) tw(l)(GSCLK) tw(h)(GSCLK) WDTRG POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 tw(h)(WDTRG) tw(l)(WDTRG) td(BLANK–OUT0) td(GSCLK–OUT0) OFF OUT0 ON (See Note1) td(OUTn+1–OUTn) OUT15 (SeeNote1) OFF OFF (SeeNote1) td(OUTn+1–OUTn) ON (See Note1) OFF OUT1 twdt td(GSCLK–OUT0) ON (See Note1) OFF OFF OFF (SeeNote1) (SeeNote1) OFF OFF (SeeNote1) (SeeNote1) HI–Z XDOWN1 (See Note2) XDOWN2 (See Note2) td(GSCLK–XDOWN2) td(BLANK–BOUT) BOUT td(GSCLK–XGSOUT) XGSOUT td(LEDCHK–XDOWN2) td(LEDCHK–XDOWN2) LEDCHK GSPOL, GSCLK and XGSOUT can be replaced with signals inverted each other. NOTE 1: ON or OFF, or ON time is varied depend on the gray scale data and BLANK. NOTE 2: When LED is disconnected. Figure 16. Timing Diagram (Constant Current Output) – MAG0 to MAG2 Are All Zero (See Note2) Template Release Date: 7–11–94 tsu(XLATCH–GSCLK) TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 28 XLATCH TLC5911 LED DRIVER SLLS402 – DECEMBER 1999 MECHANICAL DATA PZP (S-PQFP-G100) PowerPAD PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 50 76 Thermal Pad (see Note D) 26 100 0,13 NOM 1 25 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 1,05 0,95 0,25 0,15 0,05 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4146929/A 04/99 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads.The dimensions of the thermal pad are 2 mm × 2 mm (maximum). The pad is centered on the bottom of the package. E. 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