CLARE CPC1466DTR

CPC1466
Broadband ADSL/VDSL DC Termination IC
Features
Description
• Meets wetting (sealing) current requirements per
ITU-T G.991.2
• Integrated bridge rectifier for polarity correction
• Uses inexpensive opto-coupler for DC sealing
current monitoring
• Electronic inductor, breakover, and latch circuits
• Current limiting and excess power protection circuits
• ADSL/VDSL compatible with low-pass filter network
• MLT and SARTS compatible
• Compatible with portable test sets
• Small SOIC or Micro-Leadframe Package (MLP)
• MLP package 60 percent smaller than SOIC
The CPC1466 is a DC Termination IC for broadband
ADSL/VDSL applications. The high-voltage,
monolithic device provides a path for DC wetting
(sealing) current in customer premises equipment
(CPE) to eliminate phone line corrosion on DSL
twisted-pair copper lines without telephone voice
services (i.e. only broadband services).
PR
EL
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IN
AR
Y
Applications
•
•
•
•
•
Internally, a bridge rectifier provides a
polarity-insensitive DC termination for DSL loop
sealing current. The IC includes an electronic inductor,
break-over and latch circuits, current limit and excess
power protection. A sealing current detect output
provides the means to monitor the loop for the
presence of sealing current in the loop.
ADSL/VDSL broadband modems
Router and bridge customer premises equipment
Leased line equipment
Mechanized Loop Test (MLT) networks
Switched Access Remote Test System (SARTS)
networks
The CPC1466 is manufactured in Clare’s high voltage
BCDMOS process that is used extensively in
telephony applications worldwide.
Ordering Information
Figure 1. CPC1466 Block Diagram
Part Number Description
DC Termination IC, 16-pin SOIC in tubes,
47/tube
DC Termination IC, 16-pin SOIC tape and reel,
CPC1466DTR
1000/reel
DC Termination IC, 16-pin MLP in tubes,
CPC1466M
52/tube
DC Termination IC, 16-pin MLP tape and reel,
CPC1466MTR
1000/reel
CPC1466D
1
2
3
4
5
6
7
8
PR+
Electronic
Inductor,
Breakover,
Latch, and
Opto Driver
NC
TIP
NC
NC
Bridge
Rectifier
RING
NC
PR-
Current Limit
and Excess
Power Protection
DS-CPC1466 - R00B
TC
16
NC
15
NC
14
RS
13
NC
12
PD
11
NC
10
COM
9
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1
CPC1466
1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.1 DC Characteristics, Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.2 AC Characteristics, Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.3 Transition Characteristics, Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Sealing Current Monitor Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.1 LED Trigger Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
3
3
4
4
4
4
8
8
10
10
10
10
10
10
10
10
11
11
11
3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 MLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Printed Circuit Board Layout Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 MLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2 MLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Washing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
12
13
14
14
14
14
14
15
15
15
15
15
PR
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IN
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2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Surge Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Bridge Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1 Activation - On-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.2 Deactivation - Off-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Photo-Diode (PD) Output Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 On-State Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.1 Typical Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.2 Over-Voltage Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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R00B
1. Specifications
1.1 Package Pinout
1.2 Pin Description
Pin
Name
1
PR+
Protection resistor positive side
PR+
1
16
TC
2
NC
No connection
NC
2
15
NC
3
TIP
Tip Lead
TIP
3
14
NC
4
NC
No connection
5
NC
No connection
NC
4
13
RS
NC
5
12
NC
RING
6
11
PD
NC
7
10
NC
PR-
8
9
COM
6
EL
IM
PR
RING Ring lead
NC
No connection
IN
A
RY
7
R00B
Description
8
PR-
Protection resistor negative side
9
COM
Common
10
NC
No connection
11
PD
Photo-diode (LED input current)
12
NC
No connection
13
RS
Current limiting resistor
14
NC
No connection
15
NC
No connection
16
TC
Timing capacitor
1.3 Absolute Maximum Ratings
Parameter
Minimum Maximum Unit
Maximum Voltage
(T to R, R to T)*
-
300
V
Power dissipation
-
1
W
-40
+85
°C
5
95
%
-40
+125
°C
Operating temperature
Operating relative humidity
Storage temperature
Electrical absolute maximum ratings are at 25°C.
Absolute maximum ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at conditions
beyond those indicated in the operational sections of this
data sheet is not implied.
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3
CPC1466
1.4 Electrical Characteristics
informational purposes only and are not part of the
testing requirements.
Unless otherwise specified, minimum and maximum
values are guaranteed by production testing
requirements. Typical values are characteristic of the
device and are the result of engineering evaluations.
In addition, typical values are provided for
All electrical specifications are provided for TA=25°C
1.4.1 DC Characteristics, Normal Operation
For operational templates: (see Figure 2 on page 5) and (see Figure 3 on page 5).
Parameter
Off State
Breakover current
-
Symbol
Minimum
Typical
Maximum
Unit
VAN
30.0
35.0
39.0
V
IBO
-
0.5
1
mA
IN
A
RY
Activate/Non-activate Voltage
Conditions
DC Voltage drop
Active State, 1 mA ≤ ISL ≤ 20 mA
VON
-
12.5
15
V
DC leakage current
VOFF = 20 V
ILKG
-
1.5
5
µA
Hold/Release current
Active State
IH/R
0.1
0.5
1.0
mA
Minimum on current
VON < 54 V
IMIN1
20
38
-
mA
54 V ≤ VON ≤ 100 V for 2 seconds,
source resistance 200 Ω to 4 kΩ
IMIN2
9.0
45
-
mA
VON > 100 V
IMIN3
0
0.1
-
mA
IMAX1
-
38.4
70
mA
IMAX2
-
-
V ON
---------1kΩ
mA
IPD
0.2
0.3
10
mA
Maximum on current
VON ≤ 70 V
Photodiode drive current
EL
IM
VON > 70 V
Active State
1.4.2 AC Characteristics, Normal Operation
For test conditions: (see Figure 4 on page 6).
Conditions
PR
Parameter
AC impedance
200 Hz to 50 kHz
Linearity distortion
ƒ = 200 Hz to 40 kHz, ISL = 1 mA to
20 mA, VAPP ≤ 12 VPP
Symbol
Minimum
Typical
Maximum
Unit
ZMT
10
38
-
kΩ
D
40
70
-
dB
1.4.3 Transition Characteristics, Normal Operation
For activation/deactivation test conditions: (see Figure 5 on page 7).
Parameter
Conditions
Symbol
Minimum
Typical
Maximum
Unit
Activate time
(see Figure 6 on page 7)
t1
3.0
13
50
ms
Deactivate time
(see Figure 7 on page 7)
t2
3.0
-
100
ms
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R00B
Figure 2. I-V Requirements Template, 0 V to 50 V
1A
IMAX1
100 mA
VON
IMIN1
On State
VAN
1 mA
Transition
Region
100 µA
IHR
10 µA
1 µA
ILKG
Off State
0
0
IBO
IN
A
RY
Current
10 mA
10
Transition
Region
20
30
40
50
EL
IM
Absolute Voltage (V)
Figure 3. I-V Requirements Template, 0 V to 250 V
1A
70 V, 70 mA
IMAX1
100 mA
54 V, 9 mA
PR
10 mA
Current
IMAX2
IMIN1
IMIN2
1 mA
100 µA
10 µA
1 µA
100 V, 0 mA
0
0
50
100
150
200
250
Absolute Voltage (V)
R00B
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5
CPC1466
Figure 4. Test Circuit for ac Impedance and Linearity
68 µF
ISL
VAPP
ac generator
DUT
IN
A
RY
Vmt
1 - 20 mA
dc current source
1k Ω
EL
IM
Vsig
1000 × V mt
Z mt = --------------------------V sig
PR
V mt
1000
Linearity = 20 log ---------------------------------------- + 20 log -----------V sig2ndHarmonic
67.5
6
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R00B
Figure 5. Test Circuit for Activate and Deactivate Times
1 µF
Pulse
generator
DUT
85 mH
IN
A
RY
85 Ω
Figure 6. Applied Waveform for Activation Test
43.5 V
40 V
Source Impedance
200 Ω to 4k Ω
t1
30 V
EL
IM
20 V
500 ms
10 V
Measure
0
PR
Figure 7. Applied Waveform for Deactivation Test
2.0 mA
Current source limited to 30 V
Measure
1.5 mA
500 ms
1.0 mA
0.5 mA
t2
0
R00B
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7
CPC1466
1.5 Sealing Current Monitor Characteristics
1.5.1 LED Trigger Characteristics
For test conditions: (see Figure 8 on page 8).
Parameter
Conditions
Symbol
Minimum
Typical
Maximum
Unit
Applied dc battery Voltage
-
-
-43.5
-
-56
VDC
Frequency (pulses per second)
-
-
4
-
8
-
Percent break
-
-
40
-
60
%
Number of pulses
-
-
6
-
10
-
Total Loop Resistance
-
-
200
-
4000
Ω
Required opto-coupler response
-
-
-
1
-
-
10
-
-
ms
10
-
-
ms
IN
A
RY
Number of applied pulses per make/break
Pulse width (opto on)
(see Figure 8 on page 8)
TON
Pulse width (opto off)
(see Figure 8 on page 8)
TOFF
Figure 8. Test Circuit for LED Operation
RLOOP
200Ω - 4kΩ
900Ω - 4.5kΩ (MLT)
EL
IM
Series rotary dial
25Ω
1µF
+
VBAT
-43.5V to -56V
85Ω
85mH
25Ω
RING
Shunt rotary dial
PR
TIP
PR+
TC
16
2
NC
NC
15
TIP
NC
14
NC
RS
3
4
5
6
7
2.2kΩ
5%
4W 8
8
CPC1466
1
NC
NC
RING
PD
NC
PR-
13
1µF
68.1Ω
1%
1/4 W
1
6
11
2
5
10
3
4
75kΩ
NC
COM
VCC
5V
12
VOUT
9
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R00B
R00B
RING
TIP
SP1
L2
L1
30 - 35mH
with Loop Current
SSR
CPC1225N
Solid State
Relay
C1
2.2k
5%
4W
NC
PR-
8
RING
NC
NC
TIP
Current Limit
and Excess
Power Protection
Bridge
Rectifier
Electronic
Inductor,
Breakover,
Latch, and
Opto Driver
CPC1466
COM
NC
PD
NC
RS
NC
NC
TC
9
10
11
12
13
14
15
16
EL
IM
NC
PR+
7
6
5
4
3
2
1
PR
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6
5
4
1
VCC
2
3
75k
IN
A
RY
68
1%
1/4W
1µF
DC
Blocking
Capacitor
Digital
Control
Circuitry
Transceiver
Figure 9. Typical ADSL/VDSL Application Diagram
9
CPC1466
2. Functional Description
2.1 Introduction
2.4 State Transitions
The CPC1466 can be used for a number of DSL
designs requiring a dc hold circuit such as ADSL
modem applications. Typical ADSL applications will
use a filter circuit design similar to the one shown in
Figure 9‚ “Typical ADSL/VDSL Application Diagram”
on page 9.
The dc tip to ring voltage-current characteristics of the
CPC1466 are shown in Figure 2‚ “I-V Requirements
Template, 0 V to 50 V”, and in Figure 3‚ “I-V
Requirements Template, 0 V to 250 V” on page 5.
2.2 Surge Protection
EL
IM
As can be seen in the application circuit in Figure 9 on
page 9, CPC1466 designs require few external
components. For the CPC1466, all that is needed is a
circuit protector, two resistors and a capacitor. To
ensure DSL signal integrity over a wide variety of
conditions a POTS splitter type filter is recommended
to isolate the DSL traffic from the termination.
IN
A
RY
The DC Termination IC performs two fundamental
functions in an ADSL modem application; as an
electronic inductor providing a low impedance dc
termination with a high impedance ac termination and
second as part of the sealing current detection system
for automated line sensing. This function provides an
excellent method to monitor for the presence of
sealing current. Generally, loss of sealing current
indicates loop loss.
PR
Although the CPC1466 self protects via current
limiting, it requires over-voltage surge protection to
protect against destructive over-voltage transients.
Clare recommends the use of a crowbar-type surge
protector to limit the surge voltage seen by the
CPC1466 to less than 250 V. The protection device
must be able to withstand the surge requirements
specified by the appropriate governing agency in
regions where the product will be deployed. Teccor,
Inc. and Bourns, Inc. make suitable surge protectors
for most applications. Devices such as Teccor’s
P1800SD or P2000SD Sidactors and Bourns’
TISP4220H3BJ or TISP4240H3BJ thyristors should
provide suitable protection.
Transition timings are illustrated in Figure 6‚ “Applied
Waveform for Activation Test”, and in Figure 7‚
“Applied Waveform for Deactivation Test”. The test
configuration for these timings is given in Figure 5‚
“Test Circuit for Activate and Deactivate Times”. All
timing figures are located on page 7.
State transition timings are set by the 1 µF capacitor
connected between the TC and COM pins.
2.4.1 Activation - On-State
Application of battery voltage to the loop causes the
CPC1466 to conduct whenever the voltage exceeds
approximately 35 V. With application of sufficient
voltage applied across the tip and ring terminals, the
CPC1466 will initially conduct a nominal 150 µA of
sealing current for approximately 20 ms prior to
activation. Once activated, the CPC1466 will remain in
the on state for as long as the loop current exceeds a
nominal 0.5 mA.
The CPC1466 turn-on timing circuit assures device
activation will occur within 50 ms of an applied voltage
greater than 43.5 V but not within the first 3 ms.
2.4.2 Deactivation - Off-State
While the CPC1466 activation protocol is based on an
initial minimum voltage level, deactivation is based on
a diminished sealing current level. Deactivation occurs
when the nominal sealing current level drops below
0.5 mA with guaranteed deactivation occurring for
sealing current levels less than 0.1 mA
The turn-off timing circuit deactivates the sealing
current hold circuit when 1 mA of sealing current has
been removed for 100 ms but ignores periods of loss
up to 3 ms.
2.3 Bridge Rectifier
The bridge rectifier in the CPC1466 ensures that the
device is polarity insensitive and provides consistent
operational characteristics if the tip to ring polarity is
reversed.
2.5 Photo-Diode (PD) Output Behavior
Output from the PD pin provides a minimum of 0.2 mA
of photodiode drive current for an optocoupler’s LED
anytime sealing current exceeds 1 mA.
Because LED current is interrupted whenever loop
current is interrupted, the optocoupler provides an
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R00B
excellent means of indicating loop availability for
designs with a full time sealing current requirement. In
addition, for pulsed sealing current loops, the status
from this detector when used in conjuntion with the
timing of modem retraining events can be used as an
indicator to determine if the sealing current event is
clearing line impairments.
2.6 On-State Behavior
On-state sealing current levels are determined by the
network’s power feed circuit and the loop’s dc
impedance. To compensate for low loop resistance or
very high loop voltage, the CPC1466 limits the
maximum sealing current to 70 mA.
The CPC1466 manages package power dissipation
by shunting excess sealing current through the 2.2 kΩ
4W power resistor located between the PR+ and PRpins.
2.6.2 Over-Voltage Conditions
PR
EL
IM
Potentials in excess of 100 V applied to the tip and
ring interface will cause the CPC1466 to disable the
sealing current hold circuit and enter a standby state
with very little current draw. Once the over-voltage
condition is removed, the CPC1466 automatically
resumes normal operation.
IN
A
RY
2.6.1 Typical Conditions
R00B
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11
CPC1466
3. Manufacturing Information
3.1 Mechanical Dimensions
3.1.1 SOIC
0.400±0.015
(10.160±0.381)
NOTES:
1. Coplanarity = 0.004 (0.1016) max.
2. Leadframe thickness does not include solder plating (1000 microinch maximum).
3. Sum of package height, standoff, and coplanarity does not exceed 0.083 (2.108).
PIN 16
IN
A
RY
0.408±0.005
(10.363±0.127)
0.295±0.005
(7.493±0.127)
PIN 1
0.050 TYP
(1.270 TYP)
0.016 TYP
(0.406 TYP.)
0.025 X 45˚
(0.635 X 45˚)
EL
IM
0.083 MAX
(2.108 MAX.)
SEE NOTE 3
0.350 TYP
(8.890 TYP.)
0.010 ±0.0005
(0.254 ±0.0127)
LEAD TO PACKAGE STANDOFF:
MIN: 0.001 (0.0254)
MAX: 0.004 (0.102)
PR
0.020±0.004
(0.508±0.1016)
12
0.040 TYP
(1.016 TYP)
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DIMENSIONS
inches
(mm)
R00B
3.1.2 MLP
7.00 ± 0.25
(0.276 ± 0.01)
6.00 ± 0.25
(0.236 ± 0.01)
INDEX AREA
TOP VIEW
0.90 ± 0.10
(0.035 ± 0.004)
SIDE VIEW
0.23
(0.009)
IN
A
RY
0.02, + 0.03, - 0.02
(0.0008, + 0.0012, - 0.0008)
0.33, + 0.07, - 0.05
(0.013, + 0.003, - 0.002)
1
0.55 ± 0.10
(0.022 ± 0.004)
SEATING
PLANE
0.20
(0.008)
EXPOSED
METALLIC PAD
1.80
(0.071)
0.55 ± 0.10
(0.022 ± 0.004)
4.00 ± 0.05
(0.157 ± 0.002)
0.40
(0.016)
16
Terminal Tip
0.80
(0.032)
6.00 ± 0.05
(0.236 ± 0.002)
0.55 ± 0.10
(0.022 ± 0.004)
BOTTOM VIEW
PR
EL
IM
Dimensions
mm
(inch)
R00B
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13
CPC1466
3.2 Printed Circuit Board Layout Pattern
3.2.1 SOIC
3.2.2 MLP
0.40
(0.016)
1.27
(0.050)
0.65
(0.026)
1.15
(0.045)
9.30
(0.366)
5.70
(0.224)
1.90
(0.075)
1.15
(0.045)
IN
A
RY
0.43
(0.017)
0.40
(0.016)
0.60
(0.024)
DIMENSIONS
mm
(inches)
0.80
(0.031)
DIMENSIONS
mm
(inches)
NOTE: As the metallic pad on the bottom of the MLP
package is connected to the substrate of the die, Clare
recommends that no printed circuit board traces or
vias be placed under this area.
3.3.1 SOIC
EL
IM
3.3 Tape and Reel Packaging
Tape and Reel Packaging for 16-Pin SOIC Package
330.2 Dia
(13.00 Dia)
B0=10.70 + 0.15
(0.421 + 0.01)
PR
Top Cover
Tape Thickness
0.102 Max
(0.004 Max)
Embossed
Carrier
Embossment
14
W=16.00 + 0.30
(0.630 + 0.010)
Top Cover
Tape
K0=3.20 + 0.15
(0.193 + 0.01)
P=12.00
(0.47)
K1=2.70 + 0.15
(0.106 + 0.01)
User Direction of Feed
A0=10.90 + 0.15
(0.429 + 0.010)
Dimensions
mm
(inches)
NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2
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R00B
3.3.2 MLP
Tape and Reel Packaging for 6mm x 7mm 16-Pin MLP Package
B0=7.24 + 0.10
(0.285 + 0.004)
330.2 Dia
(13.00 Dia)
Pin 1
Top Cover
Tape Thickness
0.102 Max
(0.004 Max)
W=16.00 + 0.30
(0.630 + 0.012)
Embossed
Carrier
A0=6.24 + 0.10
(0.246 + 0.004)
IN
A
RY
K0=1.61 + 0.10
(0.063 + 0.004)
P=12.00 + 0.10
(0.472 + 0.004)
Dimensions
mm
(inches)
NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2
Embossment
3.4 Soldering
3.4.2 Reflow Profile
3.4.1 Moisture Reflow Sensitivity
For proper assembly, this component must be
processed in accordance with the current revision of
IPC/JEDEC standard J-STD-020. Failure to follow the
recommended guidelines may cause permanent
damage to the device resulting in impaired
performance and/or a reduced lifetime expectancy.
3.5 Washing
Clare does not recommend ultrasonic cleaning of this
part.
PR
EL
IM
Clare has characterized the moisture reflow sensitivity
for this product using IPC/JEDEC standard
J-STD-020. Moisture uptake from atmospheric
humidity occurs by diffusion. During the solder reflow
process, in which the component is attached to the
PCB, the whole body of the component is exposed to
high process temperatures. The combination of
moisture uptake and high reflow soldering
temperatures may lead to moisture induced
delamination and cracking of the component. To
prevent this, this component must be handled in
accordance with IPC/JEDEC standard J-STD-033 per
the labeled moisture sensitivity level (MSL), level 1 for
the SOIC package, and level 3 for the MLP package.
For additional information please visit www.clare.com
Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make
changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set
forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its
products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into
the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a
person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice.
Specifications: DS-CPC1466 - R00B
© Copyright 2007, Clare, Inc.
All rights reserved. Printed in USA.
6/29/2007
R00B
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15