MXED401 200-Column Cholesteric LCD Driver FEATURES: OVERVIEW: • Clare introduces the MXED401, targeted for the emerging non-volatile reflective LCD market, specifically bi-stable and multi-stable Cholesteric LCD’s. The MXED401 supports 200 phase-controlled voltage data outputs. This is the first standard product driver for ChLCD display panels. • • • • • • • • • • • • Drives Reflective-type Liquid Crystal Displays Black-White or Gray-Scale Cholesteric LCD (ChLCD) Compatible 200 Output Channels, Cascadeable 192-Channel Mode Token-Based Bi-directional Data Transfer 6-Bit Data to support 64-Level Gray-Scale ±2V to ±7V panel drive 4mA Minimum Source/Sink at ±7VOutput Levels 2.5V to 5V logic supply 26 MHz clock frequency 4mA Minimum Source/Sink at ±7V Output Levels Gold-Bumped Die @ 60 micron Output Pitch FUNCTIONAL DESCRIPTION: The MXED401 driver functions as a level shifter with a resting state at ground potential. Proper operation of the logic enables gray-scale capability. The output is a 128 Counter Clock (CCLK) event where each channel is a low resistive switch to external symmetric (with respect to ground) voltage supplies. Proper operation of the logic allows gray scale capability. The output is initially low (MV4) from one to sixty-four CCLK times, then continuously high (PV4) for sixty-four CCLK times, returning low for the balance of the 128 CCLK cycle (before returning to its quiescent value (VSS2)). The data driver chip is manufactured in a high voltage (30 V) CMOS process and is available in gold-bumpeddie form. The Token Bit Shift Register is used to control data latch timing for the Temporary Storage Register. A token bit (initialized by SRIN input) is transferred sequentially among the 200 possible (internal) outputs of the Shift register. This allows data to fill the Temporary Storage Register to in a Right to Left fashion. When the Temporary Register is filled its contents may be transferred to the Output Storage register via the LAT input. Output phase control is then accomplished by the Pulse Phase Shift Logic, data then passes to the High Voltage Translator unit to control the three output switches associated with each column output driver. 14580 www.clare.com January 29, 2003 MXED401 FIGURE 1 - MXED401 BLOCK DIAGRAM 00 01 0197 02 PV4 VSS2 MV4 3 OUT0 3 3 1 3 1 1 1 1 1 6 6 6 6 6 6 1 1 1 PULSE PHASE SHIFT LOGIC 6 6 6 LAT OUTPUT STORAGE REGISTER (6 BITS X 200) 6 6 6 D(5:0) TEMPORARY STORAGE REGISTER (6 BITS X 200) 1 1 1 SCLK SHR SEL200 SRIN VDD1 VSS1 TOKEN BIT SHIFT REGISTER (1 BIT X 200) SLIN 5.0 VOLT REGULATOR PV4 – 4.0V REGULATOR TEST CIRCUITRY HEN HREF VMCAS www.clare.com VPCAS RB NON DON PON FLYHI FLYLO 2 3 HIN XIN LOGIC TO FORCE OUTPUT TO VSS2 AND HV TRANSLATOR INTERFACE CCLK CRB INV REN REG5V HIN=(PV4 – 4.0V) XIN=4.75 TO 11.0V) 3-LEVEL OUTPUT STAGE 3 0198 0199 14580 MXED401 MXED401 DATA SHEET Table of Contents FEATURES ....................................................................................................................1 OVERVIEW ....................................................................................................................1 FUNCTIONAL DESCRIPTION .....................................................................................1 FIGURE 1 - MXED401 BLOCK DIAGRAM .................................................................2 TABLE 1 - ABSOLUTE MAXIMUM RATINGS ............................................................4 TABLE 2 - OPERATING CONDITIONS .......................................................................4 CIRCUIT DESCRIPTION ..............................................................................................5 FIGURE 2 - REGULATOR BLOCK DIAGRAM ...........................................................5 FIGURE 3 - EXAMPLE USING ON-CHIP REGULATOR ............................................5 FIGURE 4 - EXAMPLE USING EXTERNAL BIAS ......................................................5 FIGURE 5 - TYPICAL PIN VOLTAGE WAVEFORMS.................................................6 FIGURE 6 - HREF BLOCK DIAGRAM ........................................................................7 FIGURE 7 - EXAMPLE USING ON-CHIP HREF BIAS ...............................................7 FIGURE 8 - EXAMPLE USING EXTERNAL HREF BIAS ..........................................7 FIGURE 9 - INTERNAL LOGIC DETAILS FOR DATA PATH .....................................8 FIGURE 10 - ...................................................................................................................9 FIGURE 11 - ...................................................................................................................9 FIGURE 12 - SIMPLIFIED OUTPUT LOGIC DIAGRAM ......................................... 10 FIGURE 13 THROUGH 15 - PHASE DETECTOR WAVEFORM EXAMPLES ........11 ELECTRICAL SPECIFICATIONS ........................................................................12-14 TABLE 3 - COLUMN DRIVER IC DESIGNATION TABLE ...................................... 15 TABLE 6 - AC CHARACTERISTICS ........................................................................ 16 FIGURE 16- OUTPUT WAVEFORM DEFINITION ................................................... 16 MECHANICAL SPECIFICATIONS ............................................................................ 17 DIE SPECIFICATIONS ............................................................................................... 17 FIGURE 17 - DIE DIMENSIONAL DRAWING .......................................................... 18 TABLE 4 - TRUTH TABLE (TOKEN BIT SHIFT REGISTER) ................................. 19 TABLE 5 - TRUTH TABLE (DATA LATCH) .............................................................. 19 ORDERING INFORMATION ...................................................................................... 20 3 www.clare.com 14580 MXED401 ABSOLUTE MAXIMUM RATINGS Parameter M in . Max. U n it Supply voltage VDD1 -0.3 7.0 V Supply voltage PV4 -0.3 9.0 V Supply voltage MV4 -9.0 +0.3 V X IN i n p u t -0.3 12.0 V H IN i n p u t PV4-6.0 PV4+0.3 V Logic input levels -0.3 VDD1 + 0.3 V S torage temperature -65 150 C e lsius OPERATING CONDITIONS Parameter M in . Max. U n it Supply voltage VDD1 2.5 5.5 V Supply Voltage PV4 2 7 V Supply Voltage MV4 -7 -2 V H IN PV4-4.2 PV4-3.8 X IN 4.75 11 V Te m p e r a t u r e A m b i e n t -20 80 C e lsius 4 www.clare.com 14580 MXED401 CIRCUIT DESCRIPTION Voltage Regulator This product may be operated from supplies as low as 2.5 Volts. The output drive transistors require a voltage of 5.0 volts to 11.0 volts on the XIN pin to assure proper circuit operation. This bias voltage may be developed on the chip or provided by the system designer. When XIN is provided externally, the REN (Regulator ENable) pin is held low, and the FLYHI/FLYLO pins are left unconnected. Systems lacking an available bias may use the on chip voltage regulator. The circuit is enabled by forcing REN high (to VDD1). This will cause an on-chip oscillator/charge pump circuit to operate continuously and output a somewhat regulated 5 volts at pin REG5V. A capacitor (CFLY=0.1uF) is connected between pins FLYHI and FLYLO. A storage capacitor (CHOLD=1.0uF) is required on REG5V. The XIN input is then connected to the REG5V output. The charge pump is capable of driving 18 XIN loads so generally only one or two circuits are used as regulator sources. In systems where more than one regulator circuit is enabled it is forbidden to short their respective HOLD capacitors. Enabling the regulator causes an additional DC current of 65uA (130 uA maximum) to flow from VDD1 to VSS1. FIGURE 2 - REGULATOR BLOCK DIAGRAM FIGURE 3 - EXAMPLE USING ON CHIP REGULATOR FIGURE 4 - EXAMPLE USING EXTERNAL BIAS 5 www.clare.com 14580 MXED401 FIGURE 5 - TYPICAL PIN VOLTAGE WAVEFORMS HREF Bias Generator The output stage requires a reference supply 3.8 to 4.2 volts lower than PV4 into each HIN input. This may be provided by the system designer or generated on-chip. When HEN is held high, a bias voltage is generated at the HREF output which is (PV4-4.0v). This generated voltage may then be used to supply 6 HIN inputs. The HREF output must be stabilized by connecting a 0.1uF capacitor between HREF and PV4. A separate stabilizing capacitor is required for each HREF used. It is forbidden to connect any HREF pin to another HREF pin. Each enabled HREF output causes an additional DC current of 60uA (130 uA maximum) to flow from PV4 to MV4. 6 www.clare.com 14580 MXED401 FIGURE 6 - HREF BLOCK DIAGRAM FIGURE 7 - EXAMPLE USING ON CHIP HREF BIAS FIGURE 8 - EXAMPLE USING EXTERNAL HREF BIAS 7 www.clare.com 14580 MXED401 Data Input Procedure A data synchronization bit is entered into the TOKEN bit shift register via the SRIN (or SLIN) on a rising edge of SCLK. The token bit travels along the complete shift register path in order to control data latching. The internal logic is shown below. Notice the use of the SCLK divider. SCLK frequency is halved inside the IC to keep the current consumption to a minimum. The shift logic modifies the input signals in a manner that requires input data (DAT5:0) to follow the SRIN synchronization bit by 2 SCLK rising edges. Initialization of the system is accomplished via the RB input pin. The 6-bit data word is passed through the output register when pin LAT is LOW. When pin LAT is HIGH data is latched in the output storage register. The inputs SHR and SEL200 are set by the user to control SHift-Right (versus shift left) operation and SELect 200 output configuration (versus 192 output configuration.). When SEL200 is LOW the user ignores the output pads near the edge of the die. That is, ignore outputs O0-O3 and O196O199, use only outputs O4-O195. When SHR is HIGH data is loaded first into the lower number outputs first and completes the load at the higher numbered outputs. For example, with SHR high and SEL200 low the input data will load into register O4 first and complete the cycle by loading O195 on the last clock edge. FIGURE 9 - INTERNAL LOGIC DETAILS FOR DATA PATH 8 www.clare.com 14580 MXED401 FIGURE 10 FIGURE 11 - 9 www.clare.com 14580 MXED401 Phase Logic and Out0 The circuit has a 7-bit counter that is reset in a synchronous manner via the CRB (Counter-ResetBar) and CCLK (Counter CLK) pins. The counter is “preset” to zero if the CRB pin is low when the CCLK pin rises. Each phase detector output is a 128 CCLK event. The INV pin will be assumed low for the purpose of this discussion. Upon reset (via CRB) the output will be low. The output is always guaranteed to be high continuously for 64 units of the 128 CCLK event. The output is also guaranteed to be low for 64 units of the 128 CCLK events, however, not usually continuously. The input data indicates which event should be completed in order to allow the data to go high. For example, an input data word of zero will cause the output to be low until the first rising edge of CCLK, then high for the subsequent 64 rising edges, then low again for the final 63 clocks. Notice that the output is always initially low for at least one CCLK period. A fifty percent (50%) duty cycle is attained when 63 (2F-HEX) is the input data; resulting in 64 units of low followed by 64 units of high. The INV pin may invert the output from the above discussion. Pin INV must be high in order to produce a 64 unit high followed by a 64 unit low pulse train. The OUT0 (OUTput ZERO) pin will always command all outputs to zero volts potential (via the VSS2 input) irrespective of the individual states of CCLK, CRB or data stored in the output storage register. FIGURE 12 - SIMPLIFIED OUTPUT LOGIC DIAGRAM 10 www.clare.com 14580 MXED401 FIGURES 13 - 15 - PHASE DETECTOR WAVEFORM EXAMPLES 11 www.clare.com 14580 MXED401 DC ELECTRICAL CHARACTERISTICS Parameter Symbol Min Max. Unit Condition mA Vdd=2.5V Vdd=2.5V Vdd=3.3V Vdd=5.0V Sclk=0MHz Sclk=26MHz Sclk=50MHz Sclk=50MHz Logic supply current IVDD1 0.01 2.6 6.6 10.0 IDD1 due to REG5V ckt IDDREG 130 uA REN=H (no XIN load) PV4 supply current (DC) IPV4DC1 60 uA HEN:L PV4 supply current (DC) IMV4DC2 150 uA HEN:H XIN supply current (DC) IXINDC 20 uA MV4 supply current (DC) IPV4DC1 -60 uA HEN:L MV4 supply current(DC) IPV4DC2 -170 uA HEN:H PV4 supply current(AC) IPV4AC 300 uA CCLK=2.5MHz XIN current(AC) IXINAC 300 uA CCLK=2.5MHz MV4 supply current(AC) IMV4AC -450 uA CCLK=2.5MHz Logic input high voltage VIH VDD1-0.3 V Logic input low voltage VIL Logic output high voltage VOH Logic output low voltage VOL Logic input current high level IIH Logic input current low level 0.3 V IOH=1mA 0.5 V IOL=-1mA 3 3 uA Vinput=VDD1 IIL -3 -3 uA Vinput=0V Output voltage high VOH +V4-0.02V Output voltage zero VOO -0.020V Output voltage low VOL 12 VDD1-0.5 V www.clare.com Iload=0 0.020V Iload=0 PV4+0.02V Iload=0 14580 MXED401 DC ELECTRICAL CHARACTERISTICS (CONT.) Parameter Symbol Min Max. Unit Condition REG5V fanout RFO 18 XIN loads HREF fanout HFO 8 HIN loads Output switch impedance high ZOH (1) PV4-0.2V Output switch impedance zero ZOO (1) -0.20V Output switch impedance low ZOL (1) Output switch current high IOH Output switch current sink IOOL4 Output switch current source IOOH4 Output switch current sink IOOL2 Output switch current source IOOH4 Output switch current low IOL Iload=-0.2mA (1) 0.20V -0.2mA>Iload>0.2mA (1) MV4+0.2V Iload=0.2mA (1) 4 -4 4 -2 2 -4 mA PV4=7,Vout=-7V mA Vout=4.0V, OUT0=H mA Vout=-4.0V,OUT0=H mA Vout=2.0V, OUT0=H mA Vout=-2.0V,OUT0=H mA MV4=-7,Vout=+7V (1) PV4 = 2V, MV4 = -2V 13 www.clare.com 14580 MXED401 AC ELECTRICAL CHARACTERISTICS Parameter Symbol VDD1=>2.5V VDD1>3.2V Unit SCLK min pulse width high TSPWH 15 8 nS SCLK min pulse width low TSPWL 15 8 nS SCLK data setup time TSS 15 8 nS SCLK data hold time TSH 15 8 nS CCLK min pulse width high TCPWH 50 25 nS CCLK min pulse width low TCPWL 50 25 nS CCLK -CRB setup time TCS 25 12 nS CCLK -CRB hold time TCH 25 12 nS LAT min pulse width high TLPWH 50 25 nS LAT min pulse width low TLPWL 50 25 nS LAT fall after SCLK rise time TSS 50 25 nS LAT rise before SCLK rise time TSH 50 25 nS 14 www.clare.com 14580 MXED401 COLUMN DRIVER IC DESIGNATION TABLE Symbol Name O0 to O199 I/O O Designation Function Column Drive Output - OUT0 I Output Gate (Asynchronous) H:Vss2 , CRB I Counter Clear Signal(synchronous) L & CCLK Rising Edge: Counter Clear H: Counter Enable L: disable CCLK I Pulse Phase Shifter Counter Clock Rising Edge : Count, Max 4MHz INV I Phase Shift Data Invert Signal L: Normal ,H: Invert (see Fig 14&15) LAT I Phase Shift Data Latch Strobe H : Latched, D[5:0] I Phase Shift Data D(5) : MSB, D(0):LSB SCLK I Token Shift Clock Data entered on Rising Edges SHR I Data Shift Direction H: Shift Right, Input is SRIN L: Shift Left, Input is SLIN SEL200 I Data Output Select 200 or 192 H: SRIN to O000, (SHR:H) L: SRIN to O004, (SHR:H) VDD1 - Power Supply For Logic System 2.5 To 5.5V VSS1 - Logic Ground 0V PV4 - Power Supply For LC Drive 7 to 2V MV4 - Power Supply For LC Drive -7 to -2V SRIN I/O Data Synchronization bit Input for SHR:H, Output for SHR:L SLIN I/O Data synchronization bit Input for SHR:L, Output for SHR:H L:PV4,MV4 L: Transparent HIN I High Reference input (PV4-4.0V) (see HREF/HIN also) HEN I HREF source enable signal L: HREF not used , H: Enable HREF O High Reference Output (PV4-4.0V)Reference output REN I Regulator Enable Input Enable:H, Disable:L FLYHI - Voltage Regulator flying capacitor. 0.1uF cap to FLYLO when REN:H No connect when REN:L FLYLO - Voltage Regulator flying capacitor. 0.1uF cap to FLYHI when REN:H No connect when REN:L REG5V O Regulated 5 volt output 1.0uF cap to VSS1 When REN:H HREF XIN I Translator input bias reference Bias between +5.0V to +11.0V VSS2 - Output Driver Ground 0V RB I Master Reset Reset :L , Normal:H 15 www.clare.com 14580 MXED401 TABLE 6 - AC CHARACTERISTICS (See Fig. 16) Parameter Symbol Min Typ. Max. Unit Condition Shift Clk Frequency 26 MHz VDD1 = 2.5V Count Clk Frequency 4 MHz VDD1=2.5V Rising Time Tr - 5 us SEE FIG. 16 Falling Time Tf - 5 us SEE FIG. 16 PV4 Driver PV4Ron Equivalent output resistance 1.0 Kohm Iout=200uA MV4 Driver MV4Ron Equivalent output resistance 1.0 Kohm Iout=200uA us See Section 8 us TBD PV4,MV4 Pulse Width Output Delay Time TPV4,TMV4 25 - - 1 FIGURE 16 - OUTPUT WAVEFORM DEFINITION 16 www.clare.com 14580 MXED401 MECHANICAL SPECIFICATIONS DIE SPECIFICATIONS Die Dimensions: "X" Dimension 12830 µm Measured from center of scribe to center of scribe "Y" Dimension 1760 µm Measured from center of scribe to center of scribe Thickness 635 µm (nominal) Unthinned (non-back lapped wafer) Gold Bump Height 15±3 µm Die Materials: Passivation Silicon Nitride (SiN) Gold Bump Hardness 45-75 HV Wafer Silicon (Si) Note: The active surface is sensitive to light. Cover with an opaque material after assembly. COORDINATES RELATIVE T O ORIGIN (0, 0) AT MINIMUM PAD CENTER LOCATION Corners of Scribe Centers 17 Lower Left: X = -115µm, Y = -205µm Upper Right: X = 12715µm, Y = 1555µm www.clare.com 14580 MXED401 FIGURE 17 - DIE DIMENSIONAL DRAWING 18 www.clare.com 14580 MXED401 TABLE 4 - TRUTH TABLE (TOKEN BIT SHIFT REGISTER) INPUT Input-Output SHR SCLK H SEL200 Data to clock synchronization SRIN SLIN Rising Edge H Input Output D(5:0) sequence O0,O1…O198,O199 H Rising Edge L Input Output D(5:0) sequence O4,O5…O194,O195 L Rising Edge H Output Input D(5:0) sequence O199,O198…O1,O0 L Rising Edge L Output Input D(5:0) sequence O195,O194…O5,O4 TABLE 5 - TRUTH TABLE (DATA LATCH) 19 LAT CONDITION H Latched L Open (Transparent) www.clare.com 14580 MXED401 ORDERING INFORMATION MXED401 Ordering Part Number Package 14501-00 Gold Bumped Die in Waffle Trays 14526-00 Gold Bumped Die in Wafer Form 14535-00 TCP (Tape Carrier Package) please consult factory 14539-00 BGA (typically for prototyping only) For additional information please visit our website at: www.clare.com Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. 20 www.clare.com 14580