SCLS571 − FEBRUARY 2004 D Controlled Baseline D D D D D D D D D D D Balanced Propagation Delay and Transition − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −40°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree† Buffered Inputs Common 3-State Output-Enable Control 3-State Outputs Bus-Line Driving Capability Typical Propagation Delay (Clock to Q): 15 ns at VCC = 5 V, CL = 15 pF, TA = 255C Fanout (Over Temperature Range) − Standard Outputs . . . 10 LSTTL Loads − Bus Driver Outputs . . . 15 LSTTL Loads D D D D Times Significant Power Reduction Compared to LSTTL Logic ICs VCC Voltage = 4.5 V to 5.5 V Direct LSTTL Input Logic Compatibility, VIL = 0.8 V (Max), VIH = 2 V (Min) CMOS Input Compatibility, Il v 1 mA at VOL, VOH M OR PW PACKAGE (TOP VIEW) OE D0 D1 D2 D3 D4 D5 D6 D7 GND † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CP description/ordering information The CD74HCT574 is an octal D-type flip-flop with 3-state outputs and the capability to drive 15 LSTTL loads. The eight edge-triggered flip-flops enter data into their registers on the low-to-high transition of the clock (CP). The output enable (OE) controls the 3-state outputs and is independent of the register operation. When OE is high, the outputs are in the high-impedance state. ORDERING INFORMATION PACKAGE‡ TA −40°C to 125°C ORDERABLE PART NUMBER TOP-SIDE MARKING SOIC − M Tape and reel CD74HCT574QM96EP HCT574EP TSSOP − PW Tape and reel CD74HCT574QPWREP HCT574EP ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCLS571 − FEBRUARY 2004 FUNCTION TABLE INPUTS OE CP D OUTPUT Q L ↑ H H L ↑ L L L L X Q0 H X X Z NOTE: H = High voltage level (steady state) L = Low voltage level (steady state) X = Don’t care ↑ = Transition from low to high level Q0 = Level before the indicated steady-state conditions were established Z = High-impedance state logic diagram (positive logic) D0 D1 D CP D2 D Q CP D3 D Q CP D4 D Q CP D5 D Q CP D6 D Q CP D7 D Q CP D CP Q Q CP OE Q0 2 Q1 Q2 POST OFFICE BOX 655303 Q3 Q4 • DALLAS, TEXAS 75265 Q5 Q6 Q7 SCLS571 − FEBRUARY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < −0.5 V or VI > VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < −0.5 V or VO > VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Drain current per output, IO (VO > −0.5 V or VO < VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Output source or sink current per output, IO (VO > −0.5 V or VO < VCC + 0.5 V) . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND, ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead temperature (during soldering): At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max . . . . . . . . . . . . . . . . . . . . . . . 300°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages referenced to GND unless otherwise specified. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) MIN MAX 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO Output voltage tt Input transition (rise and fall) time High-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 2 UNIT V V 0.8 V VCC VCC V 0 VCC = 2 V VCC = 4.5 V 0 1000 0 500 VCC = 6 V 0 400 V ns TA Operating free-air temperature −40 125 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCLS571 − FEBRUARY 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS CMOS loads VOH VI = VIH or VIL VOL VI = VIH or VIL TTL loads II IOZ VI = VCC or GND VI = VIL or VIH, VO = VCC or GND ICC VI = VCC or GND TTL loads CMOS loads ∆ICC VI = VCC − 2.1 V, CIN CL = 50 pF VCC −0.02 4.5 V 4.4 4.4 −6 4.5 V 3.98 3.7 0.02 4.5 V 0.1 0.1 6 4.5 V 0.26 0.4 0 5.5 V ±0.1 ±1 µA 6V ±0.5 ±10 µA 8 160 µA 360 490 µA 10 10 pF 20 20 pF 0 MIN TYP MAX 5.5 V 4.5 V to 5.5 V See Note 4 TA = −40°C TO 125°C TA = 25°C IO (mA) 100 COUT 3-state NOTE 4: For dual-supply systems, theoretical worst-case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. MIN UNIT MAX V V HCT input loading TYPE ’574 INPUT UNIT LOADS† D0−D7 0.4 CP 0.75 OE 0.6 † Unit load is ∆ICC limit specified in electrical characteristics table, e.g., 360 µA max at 25°C. timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER VCC TA = 25°C TA = −40°C TO 125°C MIN MIN MAX UNIT MAX fmax tw Maximum clock frequency 4.5 V 30 20 MHz Clock pulse duration 4.5 V 16 24 ns tsu th Setup time, data before clock↑ 4.5 V 12 18 ns Hold time, data after clock↑ 4.5 V 5 5 ns 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCLS571 − FEBRUARY 2004 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd CP Q tdis OE Q ten OE Q PARAMETER tt fmax Q CP LOAD CAPACITANCE VCC CL = 50 pF 4.5 V CL = 15 pF 5V CL = 50 pF 4.5 V CL = 15 pF 5V CL = 50 pF 4.5 V CL = 15 pF 5V CL = 50 pF 4.5 V CL = 15 pF 5V TA = −40°C TO 125°C TA = 25°C MIN TYP MAX 33 MIN UNIT MAX 50 ns 15 28 42 ns 11 30 45 ns 12 12 18 60 ns MHz operating characteristics, VCC = 5 V, TA = 25°C, input tr, tf = 6 ns PARAMETER Cpd TYP Power dissipation capacitance (see Note 5) 47 UNIT pF NOTE 5: Cpd is used to determine the dynamic power consumption (PD), per package. PD = (CPD × VCC2 × fI) + Σ (CL × VCC2 × fO) fI = input frequency fO = output frequency CL = output load capacitance VCC = supply voltage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCLS571 − FEBRUARY 2004 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point RL = 1 kΩ From Output Under Test CL (see Note A) S1 VCC Open TEST GND S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain CL (see Note A) Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.3 V Timing Input tw tsu 3V Input 1.3 V 0V th 3V 1.3 V 1.3 V Data Input 1.3 V 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 3V 1.3 V Input 1.3 V 0V tPLH tPHL VOH In-Phase Output 1.3 V VOL tPHL Out-of-Phase Output 1.3 V 3V Output Control Output Waveform 1 S1 at VCC (see Note B) 1.3 V 0V tPZL 1.3 V tPLZ ≈VCC 1.3 V tPZH tPLH VOH 1.3 V VOL 1.3 V Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 10% VOL tPHZ 1.3 V 90% VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. F. tPLH and tPHL are the same as tpd. G. tPLZ and tPHZ are the same as tdis. H. tPZH and tPZL are the same as ten. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CD74HCT574QM96EP ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT574QPWREP ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04739-01XE ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04739-01YE ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD74HCT574-EP : CD74HCT574 • Catalog: CD74HCT574-Q1 • Automotive: • Military: CD54HCT574 NOTE: Qualified Version Definitions: - TI's standard catalog product • Catalog - Q100 devices qualified for high-reliability automotive applications targeting zero defects • Automotive • Military - QML certified for Military and Defense Applications Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HCT574QM96EP SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 CD74HCT574QPWREP TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HCT574QM96EP SOIC DW 20 2000 367.0 367.0 45.0 CD74HCT574QPWREP TSSOP PW 20 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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