5x7mm Surface Mount High Precision TCXO In Stock at Digi-Key 2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630-851-4722 Fax: 630-851-5040 www.conwin.com US Headquarters 630-851-4722: European Headquarters: +353-61-472221 Description Features D7 The Connor-Winfield ’s D75J 38 5J 0 .88 84 MH 7 Series are 5x7mm Surface z Mount Temperature Compensated Crystal Controlled Oscillators (TCXO) with a Tri-State LVCMOS output. Through the use of Analog Temperature Compensation, the D75J - Series are capable of holding sub 1-ppm stabilities over the 0 to 70°C temperature range. Model D75J TCXO 3.3V Operation LVCMOS Output Logic Frequency Stability: ±1.0ppm Temperature Range: 0 to 70°C Low Jitter <1pS RMS Tri-State Enable/Disable Function 5x7mm Surface Mount Package Tape and Reel Packaging RoHS Compliant / Lead Free Description Absolute Maximum Ratings Parameter Storage Temperature Supply Voltage (Vcc) Input Voltage Minimum Nominal Maximum Units -55 - 85 °C -0.5 - 6.0 Vdc -0.5 - Vcc+0.5 Vdc Nominal Maximum Units Note Operating Specifications Parameter Minimum Frequencies Available (Fo) 38.88, 50.0 Note MHz Frequency Calibration @ 25 C -1.0 - 1.0 ppm 1 Frequency Stability [±(Fmax – Fmin)/2.Fo] -1.0 - 1.0 ppm 2 Supply Voltage Variation (Vcc ±5%) -0.2 - 0.2 ppm Load Coefficient (±5%) -0.2 - 0.2 ppm - - 0.4 ppm -1.0 - 1.0 ppm/year Static Temperature Hysteresis Aging 0 - 70 C Supply Voltage (Vcc) 3.135 3.3 3.465 Vdc Supply Current (Icc) - - 6 mA - 3 5 ps rms 1 Temperature Range Period Jitter Phase Jitter (BW=12kHz to 20MHz) - 0.5 SSB Phase Noise at 10Hz offset - -70 dBc/Hz SSB Phase Noise at 100Hz offset - -100 dBc/Hz SSB Phase Noise at 1KHz offset - -120 dBc/Hz SSB Phase Noise at 10KHz offset - -140 dBc/Hz SSB Phase Noise at >100KHz offset - -145 dBc/Hz 3 ps rms Input Characteristics For Enable / Disable Function (Pin 8) Parameter Minimum Nominal Maximum Units Note Enable Voltage (High) or open circuit (Vih) 70% Vcc - - Vdc 4 Disable Voltage (Low) Output Tri-stated (Vil) - - 30% Vcc Vdc Minimum Nominal Maximum Units Note - 15 - pF 5 90%Vcc - - Vdc LVCMOS Output Characteristics Parameter LOAD Voltage Current (High) (Voh) (Low) (Vol) - - 10%Vcc Vdc (High) (Ioh) -4 - - mA (Low) (Iol) - - 4 mA 45 50 55 % - - 8 ns Duty Cycle at 50% of Vcc Rise / Fall Time 10% to 90% Note: Bulletin Tx238 Page 1 of 2 1) 2) 3) 4) 01 5) Revision Date Initial calibration @ 25 C. Specifications at time of shipment after 48 hours of operation Frequency stability vs. change in temperature. Frequency change after reciprocal temperature ramped over the operating range. Frequency measured before and after at 25°C. Leave Pad 8 unconnected if enable / disable function is not required. When tri-stated, the output stage is disabled but the oscillator and compensation circuit are still active (current consumption < 1 mA). or best performance it is recommended that the circuit connected to this output should have an equivalent input capacitance of 15pF. 14 Nov 2008 Specifications subject to change without notice. All dimensions in inches. © Copyright 2008 The Connor-Winfield Corporation 2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630-851-4722 Fax: 630-851-5040 www.conwin.com Package Characteristics Package Ordering Information D75J - 038.88MHZ * D75J - 050.0MHZ * Ceramic Surface Mount Package. Environmental Characteristics Vibration: Shock: Soldering: Vibration per Mil Std 883E Method 2007.3 Test Condition A Mechanical Shock per Mil Std 883E Method 2002.4 Test Condition B. SMD product suitable for Convection Reflow soldering. Peak temperature 260 C. Maximum time above 220 C, 60 seconds. Solderability per Mil Std 883E Method 2003 Solderability TCXO SERIES * For the tape and reel option, add -T to the end of the part number. Example: D75J-050.0 MHZ -T Design Recommendations Vcc, should have a large copper area for reduced inductance. Connect a 0.01uF bypass capacitor <0.1”(2.54mm) from the pad. 6 8 9 5 10 4 3 1 Pad Connections Buffer Ground Top View TOP LAYER GROUND LAYER Output Waveform ....... Do not route any traces in the keep out area. It is recommended the next layer under the keep out area is to be ground plane. BOTTOM LAYER Package Layout 0.025(6 Places) (0.635mm) Pin 1 2 4 8 7 6 0.100 (2.54mm) E/D 8 Vcc Supply Voltage 0.040 (1.02mm) (6 Places) 5 Dimensional Tolerance: ±.005 (.127mm) ±.02 (.508mm) Tape and Reel Information 0.037 (0.94mm) DNC DNC 0.051 (1.28mm) 0.030 (0.76mm) 0.100 (2.54mm) 9 0.038 (0.965mm) (4 Places) 3 10 0.295 (7.49mm) 0.197 ±0.006 (5.0mm) D75J 0847 38.88MHz Test Circuit Suggested Pad Layout 0.079 Max. (2.0mm) 0.276 ±0.006 (7.0mm) 0.030 (0.762mm) (4 Places) Ground Connection Do not connect Do not connect Do not connect Ground Output Do not connect Do not connect Tri-state Enable / Disable Supply, Vcc Do not connect 50 Ohm Trace Without Output Vias Buffer OSC 1 Pad 1 2 3 4 5 6 7 8 9 10 Buffer input load should be equivalent to 15pF. 50 Ohm trace Vcc <1”by design 0.010”(0.254mm) Recommended clearance inductance for internal copper flood. Ground, should have a large copper area for reduced inductance. Top View CENTER FREQUENCY Keep Out Area* Top View 6 7 9 5 10 4 Output DNC .01 uF Bypass 1 2 15 pF** 3 0.215 (5.46mm) 0.051 (1.28mm) 1 * Do not route any traces in the keep out area. It is recommended the next layer under the keep out area is to be ground plane. DNC DNC DNC DNC = Do Not Connect E/D = Enable / Disable ** NPO Grade component Solder Profile Temperature 260°C 260°C 220°C 180°C 150°C 1 120°C 0 120 S Max. US Headquarters: 630-851-4722 European Headquarters: +353-61-472221 Specifications subject to change without notice. All dimensions in inches. © Copyright 2008 The Connor-Winfield Corporation Time 10 S 60 S Max. 360 Sec. Max. Bulletin Tx238 Page 2 of 2 Revision Date 01 14 Nov 2008