UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A www.ti.com SLUS191C – FEBRUARY 1997 – REVISED JANUARY 2008 REGULATING PULSE WIDTH MODULATORS FEATURES 1 • • • • • • • • • • DESCRIPTION 8-V to 35-V Operation 5.1-V Reference Trimmed to 1% 100-Hz to 500-kHz Oscillator Range Separate Oscillator Sync Terminal Adjustable Deadtime Control Internal Soft-Start Pulse-by-Pulse Shutdown Input Undervoltage Lockout With Hysteresis Latching PWM to Prevent Multiple Pulses Dual Source/Sink Output Drivers The UC1525A/1527A series of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip +5.1-V reference is trimmed to 1% and the input common-mode range of the error amplifier includes the reference voltage, eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between the CT and the discharge terminals provides a wide range of dead-time adjustment. These devices also feature built-in soft-start circuitry with only an external timing capacitor required. A shutdown terminal controls both the soft-start circuitry and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands. BLOCK DIAGRAM VREF 16 +VIN GROUND 12 3 RT 6 CT 5 13 VC 11 OUTPUT A 14 OUTPUT B 13 VC 11 OUTPUT A 14 OUTPUT B NOR UVLO Lockout Reference Regulator 15 SYNC OSC OUT 4 To Internal Circutry Flip Flop OSC NOR DISCHARGE 7 UC1525A Output Stage COMP COMPENSATION 9 INV INPUT 1 Error Amp VREF R S PWM Latch OR S 50 m A NI INPUT 2 SOFTSTART 8 OR 3 kW SHUTDOWN 10 5 kW UC1527A Output Stage 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1997–2008, Texas Instruments Incorporated UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A www.ti.com SLUS191C – FEBRUARY 1997 – REVISED JANUARY 2008 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (continued) These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor discharged for sub-normal input voltages. This lockout circuitry includes approximately 500 mV of hysteresis for jitter- free operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulse has been terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200 mA. The UC1525A output stage features NOR logic, giving a LOW output for an OFF state. The UC1527A utilizes OR logic which results in a HIGH output level when OFF. ABSOLUTE MAXIMUM RATINGS (1) UCx52xA +VIN Supply voltage 40 VC Collector supply voltage 40 Logic inputs –0.3 to +5.5 Analog inputs –0.3 to +VIN Output current, source or sink 500 Reference output current 50 Oscillator charging current 5 Power dissipation at TA = +25°C (2) 1000 Power dissipation at TC = +25°C (2) 2000 Operating junction temperature –55 to 150 Storage temperature range –65 to 150 Lead temperature (soldering, 10 seconds) (1) (2) UNIT V mA mW °C 300 Values beyond which damage may occur. See Thermal Characteristics table. RECOMMENDED OPERATING CONDITIONS (1) +VIN Input voltage VC Collector supply voltage MIN MAX 8 35 4.5 35 Sink/source load current (steady state) 0 100 Sink/source load current (peak) 0 400 Reference load current 0 20 100 400 Hz 2 150 kΩ 0.001 0.01 µF 0 500 Ω UC1525A, UC1527A –55 125 UC2525A, UC2527A –25 85 UC3525A, UC3527A 0 70 Oscillator frequency range Oscillator timing resistor Oscillator timing capacitorm Dead time resistor range Operating ambient temperature range (1) 2 UNIT V mA °C Range over which the device is functional and parameter limits are assured. Submit Documentation Feedback Copyright © 1997–2008, Texas Instruments Incorporated Product Folder Link(s): UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A www.ti.com SLUS191C – FEBRUARY 1997 – REVISED JANUARY 2008 THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PACKAGE θJA θJC J-16 80-120 28 N-16 90 45 DW-16 45-90 25 PLCC-20 43-75 34 LCC-20 70-80 20 PLCC-20, LCC-20 Q AND L PACKAGES (TOP VIEW) CONNECTION DIAGRAMS 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VREF +VIN Output B VC Ground Output A Shutdown Compensation SYNC OSC Output NC CT RT 4 3 2 1 20 19 18 5 6 17 16 7 15 14 9 10 11 12 13 8 Output B VC NC Ground Output A Discharge Soft Start NC Compensation Shutdown INV Input NI Input SYNC OSC Output CT RT Discharge Soft Start NI Input INV Input NC V REF +V IN DIL-16 J or N PACKAGE (TOP VIEW) NC − No internal connection Copyright © 1997–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A 3 UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A www.ti.com SLUS191C – FEBRUARY 1997 – REVISED JANUARY 2008 ELECTRICAL CHARACTERISTICS +VIN = 20 V, and over operating temperature, unless otherwise specified, TA = TJ PARAMETER TEST CONDITIONS MIN TYP MAX UC152xA, UC252xA 5.05 5.10 5.15 UC352xA 5.0 5.1 5.2 UNIT REFERENCE Output voltage TJ = 25°C Line regulationg VIN = 8 V to 35 V 10 20 Load regulationg IL = 0 mA to 20 mA 20 50 Temperature stability (1) Over operating range 20 V mV 50 UC152xA, UC252xA 5.0 5.2 UC352xA 4.95 5.25 Total output variation (1) Line, load, and temperature Shorter circuit current VREF = 0, TJ = 25°C 80 100 mA Output noise Voltage (1) 10 Hz ≤ 10 kHz, TJ = 25°C 40 200 µVrms TJ = 125°C 20 50 mV (1) Long term stability V OSCILLATOR SECTION (2) Initial accuracy (1) (2) Voltage stability (1) TJ = 25°C (2) Temperature stability VIN = 8 V to 35 V (1) 2% 6% UC152xA, UC252xA 0.3% 1% UC352xA 1% 2% Over operating range 3% Minimum frequency RT = 200 kΩ, CT = 0.1 µF Maximum frequency RT = 2 kΩ, CT = 470 pF 400 Current mirror IRT = 2 mA 1.7 2.0 3.0 3.5 0.3 1.2 Clock amplitude (1) Clock width (1) mA 0.5 1.0 µs 2.0 2.8 V 1.0 2.5 mA UC152xA, UC252xA 0.5 5 mV UC352xA 2 10 1 10 TJ = 25°C Syncronization threshold (1) (2) Sync input current Hz kHz 2.2 (2) (2) 6% 120 Sync voltage = 3.5 V V ERROR AMPLIFIER SECTION (VCM = 5.1 V) Input offset voltage Input bias current Input offset current 1 DC open loop gain RL ≥ 10 MΩ Gain-bandwidth product (1) AV = 0 dB, TJ = 25°C DC transconductanc (1) TJ = 25°C, 30 kΩ ≤ RL ≤ 1 MΩ (3) 60 75 dB 1 2 MHz 1.1 1.5 Low-level output voltage 0.2 High-level output voltage 3.8 5.6 Common mode rejection VCM = 1.5 V to 5.2 V 60 75 Supply voltage rejection VIN = 8 V to 35 V 50 60 (1) (2) 4 mS 0.5 V dB These parameters, although ensured over the recommended operating conditions, are not 100% tested in production. Tested at fOSC = 40 kHz (RT = 3.6 kΩ, CT = 0.01 µF, RD = 0. Approximate oscillator frequency is defined by: f+ (3) µA 1 C Tǒ0.7RT ) 3RDǓ DC transconductance (gM) relates to DC open-loop voltage gain (AV) according to the following equation: AV = gMRL where RL is the resistance from pin 9 to ground. The minimum gM specification is used to calculate minimum AV when the error amplifier output is loaded. Submit Documentation Feedback Copyright © 1997–2008, Texas Instruments Incorporated Product Folder Link(s): UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A www.ti.com SLUS191C – FEBRUARY 1997 – REVISED JANUARY 2008 ELECTRICAL CHARACTERISTICS (continued) +VIN = 20 V, and over operating temperature, unless otherwise specified, TA = TJ PARAMETER TEST CONDITIONS MIN TYP 45% 49% 0.7 0.9 MAX UNIT PWM COMPARATOR Minimum duty-cycle 0% Maximum duty-cycle Zero duty-cycle Input threshold (4) Maximum duty-cycle Input bias current (4) V 3.3 3.6 0.05 1.0 µA µA SHUTDOWN Soft-start current VSD = 0 V, VSS = 0 V Soft-start low level VSD = 2.5 V 25 50 80 0.4 0.7 Shutdown threshold To outputs, VSS = 5.1 V, TJ = 25°C 0.8 1.0 Shutdown input current Shutdown Delay (5) VSD = 2.5 V 0.4 1.0 mA VSD = 2.5 V, TJ = 25°C 0.2 0.5 µs ISINK = 20 mA 0.2 0.4 ISINK = 100 mA 1.0 2.0 0.6 V OUTPUT DRIVERS (each output) (VC = 20 V) Low-level output voltage High-level output voltage ISOURCE = 20 mA 18 19 ISOURCE = 100 mA 17 18 6 7 Undervoltage lockout VCOMP and VSS = High VC OFF Current (6) VC = 35 V Rise Time (5) Fall Time (5) V 8 200 CL = 1 nF, TJ = 25°C 100 600 CL = 1 nF, TJ = 25°C 50 300 VIN = 35 V 14 20 µA ns TOTAL STANDBY CURRENT Supply Current (4) (5) (6) mA Tested at fOSC = 40 kHz (RT = 3.6 kΩ, CT = 0.01 µF, RD = 0 Ω. These parameters, although ensured over the recommended operating conditions, are not 100% tested in production. Collector off-state quiescent current measured at pin 13 with outputs low for UC1525A and high for UC1527A. UC1525A Error Amplifier 15 +VIN Q3 Q4 Q1 Inv Input Q2 1 to PWM Comparator NI Input 2 200 mA 100 mA 100 W 5.8 V 9 Copyright © 1997–2008, Texas Instruments Incorporated Comp Submit Documentation Feedback Product Folder Link(s): UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A 5 UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A www.ti.com SLUS191C – FEBRUARY 1997 – REVISED JANUARY 2008 PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS +VIN 13 +VC Q7 Q5 Q9 Q10 Q4 11 14 +VREF Q6 Q1 5 kW Clock Q2 Q3 10 kW 10 kW F/F Output Q8 Q11 Q6 Ommitted In UC1527A 2 kW PWM Figure 1. UC1525A Output Circuit (1/2 circuit shown) Q1 +VSUPPLY To Output Filter R1 R2 13 +VC A 11 UC1525A B 14 GND 12 Return Figure 2. Grounded Driver Outputs For Single-Ended Supplies For single-ended supplies, the driver outputs are grounded. The VC termainal is switched to ground by the totem-pole source transistors on alternate oscillator cycles. 6 Submit Documentation Feedback Copyright © 1997–2008, Texas Instruments Incorporated Product Folder Link(s): UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A www.ti.com SLUS191C – FEBRUARY 1997 – REVISED JANUARY 2008 PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS (continued) +15 V 13 Q1 +VC T1 11 A 30 W D1 UC1525A Q2 B 14 GND 30 W D2 12 D1, D2: UC3611 Return Figure 3. Output Drivers With Low Source Impedance The low source impedance of the output drivers provides rapid charging of power FET input capacitance while minimizing external components. VIN = 20 V, TA = 25°C Saturation Voltage − V 4 3 2 Source = VO − VOH 1 Sink = VOL 0 0.1 .1 .2 1 Output Current, Source or Sink − A Figure 4. UC1525A Output Saturation Characteristics. +VSUPPLY R1 C1 13 +VC A 11 R2 R3 GND T1 C2 UC1525A B Q1 14 Q2 12 Return Figure 5. Conventional Push-Pull Bipolar Design In conventional push-pull bipolar designs, forward base drive is controlled by R1–R3. Rapid turn-off times for the power devices are achieved with speed-up capacitors C1 and C2. Copyright © 1997–2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A 7 UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A www.ti.com SLUS191C – FEBRUARY 1997 – REVISED JANUARY 2008 PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS (continued) +VSUPPLY Q1 T1 C1 13 +VC R1 A 11 UC1525A Q2 30 W B 14 GND C2 R2 12 Return D1, D2: UC3611 Figure 6. Low Power Transformers Low power transformers can be driven by the UC1525A. Automatic reset occurs during dead time, when both ends of the primary winding are switched to ground. VREF 16 Q1 Q5 Q8 7.4 kW RT 6 CT 5 Q3 Q6 Q9 2 kW 14 kW Q10 Q11 Ramp To PWM SYNC 3 DISCHARGE 7 2 kW 25 kW Q14 400 mA Blanking To Outout 5 pF 23 kW Q4 Q2 1 kW GND Q7 1 kW Q12 Q13 3 kW 250 kW 12 Clock Figure 7. UC1525A Oscillator Schematic 8 Submit Documentation Feedback Copyright © 1997–2008, Texas Instruments Incorporated Product Folder Link(s): UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A www.ti.com SLUS191C – FEBRUARY 1997 – REVISED JANUARY 2008 PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS (continued) Shutdown Options (See Block Diagram) Since both the compensation and soft-start terminals (Pins 9 and 8) have current source pull-ups, either can readily accept a pull-down signal which only has to sink a maximum of 100 A to turn off the outputs. This is subject to the added requirement of discharging whatever external capacitance may be attached to these pins. An alternate approach is the use of the shutdown circuitry of Pin 10 which has been improved to enhance the available shutdown options. Activating this circuit by applying a positive signal on Pin 10 performs two functions; the PWM latch is immediately set providing the fastest turn-off signal to the outputs; and a 150-A current sink begins to discharge the external soft-start capacitor. If the shutdown command is short, the PWM signal is terminated without significant discharge of the soft-start capacitor, thus, allowing, for example, a convenient implementation of pulse-by-pulse current limiting. Holding Pin 10 high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turn-on upon release. Pin 10 should not be left floating as noise pickup could conceivably interrupt normal operation. All transitions of the voltage on pin 10 should be within the time frame of one clock cycle and not repeated at a frequency higher than 10 clock cycles. Oscillator Charge Time vs RT and CT Oscillator Discharge Time vs RT CT 500 100 50 20 Ω CT = 1 nF CT = 2 nF CT = 5 nF CT = 0.1 µF CT = .02 µF CT = .05 µF CT = .01 µF RD − Dead Time Resistance − RT − Timing Resistance − k Ω 200 10 5 6 2 5 RT 200 100 CT RD = 0 1 2 7 RD CT = 1 nF CT = 2 nF CT = 5 nF 400 C = .01 µF T CT = .02 µF CT = .05 µF 300 CT = 0.1 µF 0 0.2 5 10 20 50 100 200 1ms 2ms 5ms10ms 0.5 1 Charge Time − ms 2 5 10 20 50 100 200 Charge Time − ms Figure 8. Figure 9. Maximum Value RD vs Minimum Value RT Error Amplifier Voltage Gain and Phase vs Frequency 500 80 400 25°C −55°C 300 200 Max RD For a Given RT, Min RT For a Given RD 100 0 2 4 6 8 10 Minimum Recommended RT − kW Figure 10. Copyright © 1997–2008, Texas Instruments Incorporated 12 60 RL = ∞ RL = 1 MΩ RL = 300 kΩ VIN = 20 V, TJ = 25°C Voltage Gain RL = 100 kΩ 40 RL = 30 kΩ 20 0 −180° Phase 100 1k 10 k 100 k 1M −270° −360° 10 M Open-Loop Phase Open-Loop Voltage Gain − dB Maximum recommended RD 125°C f − Frequency − Hz Figure 11. Submit Documentation Feedback Product Folder Link(s): UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A 9 UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A www.ti.com SLUS191C – FEBRUARY 1997 – REVISED JANUARY 2008 PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS (continued) VREF Reference Regulator 16 Clock 0.1 0.1 3 kW SYNC 10 kW RT 0.1 Flip/ Flop A 11 3 6 1.5 kW Ramp Out A Oscillator Deadtime 3.6 kW .009 VC 13 4 PWM Adj. +VIN 15 1 k, 1 W (2) 7 B 100 W 14 5 .001 Out B Comp 0.1 1 = VOS 2 = I(+) 3 = I(−) − V/I Meter + 1 2 3 1 2 3 10 kW 0.1 PWM 9 Gnd 12 50 mA 2 3 1 2 3 Soft-Start 8 1 5 mF 1 E/A 2 5 kW 5 kW 5 kW 10 VREF Shutdown D.U.T. Figure 12. Lab Test Fixture 10 Submit Documentation Feedback Copyright © 1997–2008, Texas Instruments Incorporated Product Folder Link(s): UC1525A, UC1527A UC2525A, UC2527A UC3525A, UC3527A PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) 5962-89511012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-89511012A 5962-89511032A ACTIVE LCCC FK 20 1 TBD Call TI Call TI -55 to 125 596289511032A UC1525AL/ 883B 5962-8951103EA ACTIVE CDIP J 16 1 TBD Call TI Call TI -55 to 125 5962-8951103EA UC1525AJ/883B 5962-89511042A ACTIVE LCCC FK 20 1 TBD Call TI Call TI -55 to 125 5962-89511042A UC1527AL/ 883B 5962-8951104EA ACTIVE CDIP J 16 1 TBD Call TI Call TI -55 to 125 5962-8951104EA UC1527AJ/883B UC1525AJ ACTIVE CDIP J 16 25 TBD A42 N / A for Pkg Type -55 to 125 UC1525AJ UC1525AJ883B ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8951103EA UC1525AJ/883B UC1525AL ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 UC1525AL UC1525AL883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 596289511032A UC1525AL/ 883B UC1527AJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 UC1527AJ UC1527AJ883B ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8951104EA UC1527AJ/883B UC1527AL883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-89511042A UC1527AL/ 883B UC2525ADW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -25 to 85 UC2525ADW UC2525ADWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -25 to 85 UC2525ADW UC2525ADWTR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -25 to 85 UC2525ADW Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) UC2525ADWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -25 to 85 UC2525ADW UC2525AJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -25 to 85 UC2525AJ UC2525AN ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -25 to 85 UC2525AN UC2525ANG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -25 to 85 UC2525AN UC2525BDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -25 to 85 UC2525BDW UC2525BDWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -25 to 85 UC2525BDW UC2525BN ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -25 to 85 UC2525BN UC2525BNG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -25 to 85 UC2525BN UC2527AN ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 UC2527AN UC2527ANG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 UC2527AN UC3525ADW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3525ADW UC3525ADWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3525ADW UC3525ADWTR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3525ADW UC3525ADWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3525ADW UC3525AJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type 0 to 70 UC3525AJ UC3525AN ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3525AN UC3525ANG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3525AN UC3525AQ ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR 0 to 70 UC3525AQ Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish MSL Peak Temp (2) Op Temp (°C) Top-Side Markings (3) (4) UC3525AQG3 ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR 0 to 70 UC3525AQ UC3527AJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type 0 to 70 UC3527AJ UC3527AN ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3527AN UC3527ANG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 UC3527AN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. 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OTHER QUALIFIED VERSIONS OF UC1525A, UC1527A, UC2525A, UC2525AM, UC3525A, UC3525AM, UC3527A, UC3527AM : Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 • Catalog: UC3525A, UC3527A, UC2525A, UC3525AM, UC3525A, UC3527AM, UC3527A • Military: UC2525AM, UC1525A, UC1525A, UC1527A, UC1527A NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications Addendum-Page 4 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device UC2525ADWTR Package Package Pins Type Drawing SOIC DW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.7 2.7 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UC2525ADWTR SOIC DW 16 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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