TI DS26C31MQML

DS26C31MQML
DS26C31MQML CMOS Quad TRI-STATE Differential Line Driver
Literature Number: SNOSAS2
DS26C31MQML
CMOS Quad TRI-STATE® Differential Line Driver
General Description
The DS26C31 is a quad differential line driver designed for
digital data transmission over balanced lines. The DS26C31
meets all the requirements of EIA standard RS-422 while retaining the low power characteristics of CMOS. The DS26C31
is compatible with EIA standard RS-422; however, one exception in test methodology is taken . This enables the construction of serial and terminal interfaces while maintaining
minimal power consumption.
The DS26C31 accepts TTL or CMOS input levels and translates these to RS-422 output levels. This part uses special
output circuitry that enables the drivers to power down without
loading down the bus. This device has enable and disable
circuitry common to all four drivers. The DS26C31 is pin compatible to the AM26LS31 and the DS26LS31.
All inputs are protected against damage due to electrostatic
discharge by diodes to VCC and ground.
Features
■
■
■
■
■
■
TTL input compatible
Outputs will not load line when VCC = 0V
Meets the requirements of EIA standard RS-422
Operation from single 5V supply
TRI-STATE outputs for connection to system buses
Low quiescent current
Ordering Information
NS Part Number
SMD Part Number
DS26C31ME/883
5962–9163901M2A
DS26C31MJ/883
DS26C31MW/883
NS Package Number
Package Description
E20A
20LD LCC
5962–9163901MEA
J16A
16LD Ceramic DIP
5962–9163901MFA
W16A
16LD Ceramic Flatpack
Connection Diagrams
20163001
Top View
See NS Package Number J16A, W16A
20163012
Top View
20-Lead Ceramic Leadless Chip Carrier (E)
See NS Package Number E20A
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2010 National Semiconductor Corporation
201630
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DS26C31MQML CMOS Quad TRI-STATE Differential Line Driver
October 26, 2010
DS26C31MQML
Logic Diagram
20163002
Truth Table
ENABLE ENABLE Input Non-Inverting
Output
L
H
X
Z
Z
All other
L
L
H
combinations of
H
H
L
enable inputs
L = Low logic state
X = Irrelevant
H = High logic state
Z = TRI-STATE (high impedance)
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Inverting
Output
2
DS26C31MQML
Absolute Maximum Ratings (Note 1, Note 2)
Supply Voltage (VCC)
DC Input Voltage (VI)
DC Output Voltage (VO)
Clamp Diode Current (IIK, IOK)
DC Output Current, per pin (IO)
DC VCC or Gnd Current, per pin (ICC)
Storage Temperature Range (TStg)
Lead Temperature (TL)
−0.5V to 7.0V
−1.5V to VCC +0.5V
−0.5V to 7V
±20 mA
±150 mA
±150 mA
−65°C ≤ TA ≤ +150°C
260°C
Soldering, 4 sec.
Operating Conditions
Min
4.50
0
−55
Supply Voltage (VCC)
DC Input or Output Voltage (VI, VO)
Operating Temperature Range (TA)
Max
5.50
VCC
+125
Units
V
V
°C
Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup
Description
Temp °C
1
Static tests at
+25
2
Static tests at
+125
3
Static tests at
-55
4
Dynamic tests at
+25
5
Dynamic tests at
+125
6
Dynamic tests at
-55
7
Functional tests at
+25
8A
Functional tests at
+125
8B
Functional tests at
-55
9
Switching tests at
+25
10
Switching tests at
+125
11
Switching tests at
-55
12
Settling time at
+25
13
Settling time at
+125
14
Settling time at
-55
3
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DS26C31MQML
DS26C31M Electrical Characteristics
DC Parameters
Symbol
Parameter
Conditions
Notes
Min
Max
2.0
Units
Subgroups
V
1, 2, 3
V
1, 2, 3
V
1, 2, 3
V
1, 2, 3
V
1, 2, 3
VIH
Logical "1" Input Voltage
VIL
Logical "0" Input Voltage
VOH
Logical "1" Output Voltage
VI = VIH or VIL,
VCC = 4.5V, IO = -20mA
VOL
Logical "0" Output Voltage
VI = VIH or VIL,
IO = 20mA, VCC = 4.5V
VT
Differential Output Voltage
RL = 100Ω, VCC = 4.5V
(Note 4)
|VT| − |VT |
Difference in Differential Output
RL = 100Ω, VCC = 4.5V
(Note 4)
0.4
V
1, 2, 3
VOS
Common Mode Output Voltage
RL = 100Ω, VCC = 5.5V
(Note 4)
3.0
V
1, 2, 3
|VOS−VOS |
Diff in Common Mode Output
RL = 100Ω, VCC = 5.5V
(Note 4)
0.4
V
1, 2, 3
II
Input Current
VI = VCC, Gnd, VIH, or VIL,
VCC = 5.5V
±1.0
µA
1, 2, 3
ICC
Quiescent Power Supply Current IO = 0µA, VI = VCC or Gnd,
VCC = 5.5V
(Note 5)
500
µA
1, 2, 3
(Note 5)
2.1
mA
1, 2, 3
±5.0
µA
1, 2, 3
-150
mA
1, 2, 3
100
µA
1, 2, 3
-100
µA
1, 2, 3
Max
Units
Subgroups
Figure 2
14
ns
9, 10, 11
Figure 2
14
ns
9, 10, 11
0.8
IO = 0µA, VI = 2.4V or 0.5V,
VCC = 5.5V
IOZ
TRI-STATEOutput Leakage
Current
VO = VCC or Gnd, Enable = VIL,
VCC = 5.5V, Enable = VIH
ISC
Output Short Circuit Current
VI = VCC or Gnd, VCC = 5.5V
IOff
Output Leakage Current "Power VCC = 0V, VO = 6V
Off"
VCC = 0V, VO = 0V
2.5
0.5
(Note 4),
(Note 6)
2.0
-30
AC Parameters - Propagation Delay Time Figure 1
The following conditions apply, unless otherwise specified.
Symbol
Parameter
tPLH
Input to Output Prop Delay
tPHL
Input to Output Prop Dalay
VCC = 5V, tR ≤ 6ns, tF ≤ 6ns
Conditions
Skew
Notes
Min
3.0
ns
9, 10, 11
tTLH
Output Rise Time
Figure 4
(Note 7)
14
ns
9, 10, 11
tTHL
Output Fall Time
Figure 4
14
ns
9, 10, 11
tPZH
Output Enable Time
Figure 3
22
ns
9, 10, 11
tPZL
Output Enable Time
Figure 3
28
ns
9, 10, 11
tPHZ
Output Disable Time
Figure 3
(Note 8)
12
ns
9, 10, 11
tPLZ
Output Disable Time
Figure 3
(Note 8)
14
ns
9, 10, 11
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: Unless otherwise specified, all voltages are referenced to ground. All currents into device pins are positive, all currents out of device pins are negative.
Note 3: Unless otherwise specified, min/max limits apply across the recommended operating temperature range.
Note 4: See EIA Specification RS-422 for exact test conditions.
Note 5: Measured per input. All other inputs at VCC or GND.
Note 6: This is the current sourced when a high output is shorted to ground. Only one output at a time should be shorted.
Note 7: Skew is defined as the difference in propagation delays between complimentary outputs at the 50% point.
Note 8: Output disable time is the delay from ENABLE or ENABLE being switched to the output transistors turning off.
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4
DS26C31MQML
Typical Performance Characteristics
Differential Propagation Delay
vs Temperature
Differential Propagation Delay
vs Power Supply Voltage
20163014
20163015
Differential Skew vs
Temperature
Differential Skew vs Power
Supply Voltage
20163016
20163017
Differential Transition Time
vs Temperature
Differential Transition Time
vs Power Supply Voltage
20163018
20163019
5
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DS26C31MQML
Complementary Skew vs
Temperature
Complementary Skew vs
Power Supply Voltage
20163020
20163021
Differential Output Voltage
vs Output Current
Differential Output Voltage
vs Output Current
20163022
20163023
Output High Voltage vs
Output High Current
Output High Voltage vs
Output High Current
20163024
20163025
Output Low Voltage vs
Output Low Current
Output Low Voltage vs
Output Low Current
20163026
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20163027
6
DS26C31MQML
Supply Current
vs Temperature
Output Low Voltage vs
Output Low Current
20163026
20163028
Output Low Voltage vs
Output Low Current
Supply Current
vs Temperature
20163027
20163028
Supply Current vs
Power Supply Voltage
No Load Supply Current
vs Data Rate
20163030
20163029
Loaded Supply Current
vs Data Rate
Output Short Circuit Current
vs Temperature
20163031
20163032
7
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DS26C31MQML
Output Short Circuit Current
vs Power Supply Voltage
20163033
AC Test Circuit and Switching Time
Waveforms
20163003
Note: C1 = C2 = C3 = 40 pF (Including Probe and Jig Capacitance), R1 = R2 = 50Ω, R3 = 500Ω.
FIGURE 1. AC Test Circuit
20163004
FIGURE 2. Propagation Delays
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8
DS26C31MQML
20163005
FIGURE 3. Enable and Disable Times
20163007
Input pulse; f = 1 MHz, 50%; tr ≤ 6 ns, tf ≤ 6 ns
FIGURE 4. Differential Rise and Fall Times
Typical Applications
Two-Wire Balanced System, RS-422
20163009
*RT is optional although highly recommended to reduce reflection.
9
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DS26C31MQML
Revision History
Released
10/26/2010
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Revision
A
Section
Changes
New Release, Corporate format
10
1 MDS data sheets converted into one Corp. data
sheet format. MNDS26C31M-X Rev 0B0 will be
archived.
DS26C31MQML
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Ceramic Leadless Chip Carrier (E)
NS Package Number E20A
16-Lead Ceramic Dual-In-Line Package (J)
NS Package Number J16A
11
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DS26C31MQML
16-Lead Ceramic Flatpak Package (W)
NS Package Number W16A
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12
DS26C31MQML
Notes
13
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DS26C31MQML CMOS Quad TRI-STATE Differential Line Driver
Notes
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