SCG4600
Synchronous Clock
Generators
PLL
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630-851-4722
Fax: 630-851-5040
www.conwin.com
Bulletin
Page
Revision
Date
Issued By
SG028
1 of 12
P01
19 July 02
MBatts
General Description
Features
The SCG4600 is a digital phase locked loop generating
CML outputs from an intrinsically low jitter voltage
controlled crystal oscillator.
The SCG4600 can lock to one of two external 8 kHz
references, which is selectable using the SELAB input
select pin. The unit has an acquisition time of about 1.5
seconds and it is tolerant of different reference duty
cycles.
The SCG4600 includes an alarm output that
indicates deviations from normal operation. If a Lossof-Reference (LOR) or Loss-of-Lock (LOL) is detected
the alarm with indicate the need for a reference
rearrangement. If both references A and B are absent
the module will enter Free Run operation. The
FRstatus pin will indicate that the module is in Free
Run operation. Frequency stability during Free Run
operation is guaranteed to ±20 PPM. Additionally the
Free Run mode may be entered manually.
The package dimensions are 1.05" x 1.03" x .375"
(maximum) on a 4 layer FR4 board with J-Leads. Parts
are assembled using high temperature solder to
withstand 180°C surface mount reflow processes.
• Phase Locked Output
Frequency Control
• Intrinsically Low Jitter
Crystal Oscillator
• CML Outputs
• Dual 8 kHz
References
• LOR & LOL Alarm.
• Force Free Run
Function
• Automatic Free Run
Operation on Loss of
Both References A &
B
• Input Duty Cycle
Tolerant
• 3.3VDC Power Supply
Block Diagram
Figure 1
Alarm
Q
Ref A
Ref B
8 kHz Phase
Aligner
Analog Filter
DPFD
38.88 MHz VCXO
OC-12 PLL
QN
1/N
SEL AB
Absolute Maximum Rating
Table 1
Symbol
Parameter
Minimum
Nominal
Maximum
Units
Notes
Vcc
Power Supply Voltage
-0.5
-
+4.0
Volts
1.0
Vi
Input Voltage
-0.5
-
+5.5
Volts
1.0
Ts
Storage Temperature
-40.0
-
+85
°C
1.0
Operating Specifications
Table 2
Symbol
Parameter
Minimum
Nominal
Maximum
Units
Notes
Vcc
Power Supply Voltage
3.135
3.3
3.465
Volts
2.0
Icc
Power Supply Current
-
200
-
mA
To
Temperature Range
0
-
70
°C
Fo
Available Output Frequencies -
622.08
155.52
-
MHz
MHz
Ffr
Free Run Frequency
-
20
ppm
Frefa
Reference Frequency A
-
8
-
kHz
Frefb
Reference Frequency B
-
8
-
kHz
Fcap
Capture/pull-in range
-25
-
25
ppm
Fbw
Jitter Filter Bandwidth
-
-
3
Hz
Tjtol
Input Jitter Tolerance
-
-
6.25
µs
Taq
Acquisition Time
-
1.4
-
s
4.0
Trf
Output Rise and Fall Time
-
100
-
ps
5.0
DC
Output Duty Cycle (20% 80%) 45
-
55
%
MTIEsr
MTIE @ Synchronization
Rearrangement
50
-
ns
-20
-
3.0
NOTES:
1.0 Operation of the device at these or any other condition beyond those listed under Operating Specifications is not implied.
Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.
2.0 Requires external regulation and supply decoupling. (2.2 uF, 330 pF)
3.0 3db loop response.
4.0 From a 20 PPM step in reference frequency
5.0 CML outputs ac coupled into 50-ohm load to VCC.
Preliminary Data Sheet #: SG028
Page 2 of 12
Rev: P01
Date: 07/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Input And Output Characteristics
Table 3
Symbol
Parameter
Minimum
Nominal
Maximum
Units
Notes
CMOS Input and Output Characteristics
Vih
High Level Input Voltage
2.0
-
5.5
V
Vil
Low Level Input Voltage
0.0
-
0.8
V
Tio
I/O to Output Valid
-
-
10
ns
Cl
Output Capacitance
-
-
10
pF
Voh
High Level Output Voltage
2.4
-
-
V
Vol
Low Level Output Voltage
-
-
0.4
V
Tir
Input Reference Pulse Width
25.72
-
-
ns
-
800
1200
mV
CML Output Characteristics
Vod
Differential Output Voltage
5.0
Input Selection / Output Response
Table 4
ENABLE
SELAB
INPUTS
REFA
REFB
FR
FRstatus
OUTPUTS
ALARM
Q
QN
1
0
X
X
X
X
1
X
X
X
X
1
X
X
X
X
HZ
HZ
X
X
0
0
X
X
X
1
1
1
X
X
FR
0
0
0
A
A
0
0
0
X
X
RA
0
0
1
A
A
0
0
0
X
X
RB
0
0
0
NA
A
0
0
1
X
X
U
0
0
1
NA
A
0
0
0
X
X
RB
0
0
1
A
NA
0
0
1
X
X
U
0
0
0
A
NA
0
0
0
X
X
RA
0
0
X
NA
NA
0
1
1
X
X
FR
RESET
NOTES:
A
Active
FR Free Run Mode
NA Not Active
HZ High Impedance
NOTE
FR
RA Locked to Reference A
RB Locked to Reference B
U
Unstable (due to conditions shown, switch to active reference
or Free Run)
X
Don’t care
Jitter Generation Specifications
Table 5
Frequency (MHz)
155.52
SONET Jitter BW 12 kHz - 1.3 MHz
pS (RMS)
2.2 Typ.
SONET Jitter BW 12 kHz - 5 MHz
pS (RMS)
622.08
1.9 Typ.
Preliminary Data Sheet #: SG028
Page 3 of 12
Rev: P01
Date: 07/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Pin Description
Table 6
Pin #
All SCG4600 Models
Pin Name
Pin Information
Note
1
ENABLE
CML Enable / CMOS Tri-State (Enable = 0, Disable = 1)
9.0
2
TCK
No Connection, Internal Factory Programming Input.
8.0
3
TDO
No Connection, Internal Factory Programming Input.
8.0
4
REFA
CMOS Reference Frequency Input.
5
SELAB
Input Reference Select Pin. (REFA = 0, REFB = 1)
9.0
6
RESET
RESET. (RESET = 1)
9.0
7
REFB
CMOS Reference Frequency Input.
8
GND
Ground.
9
FRstatus
Free Run Status. (FR = 1)
10
Vcc
Supply Voltage relative to ground.
11
N/C
No Connection.
12
ALARM
Loss of Reference / Lock alarm. (Alarm = 1)
13
FR
Force Free Run. (Phase Lock = 0, Free Run = 1)
9.0
14
TDI
No Connection, Internal Factory Programming Input.
8.0
15
TMS
No Connection, Internal Factory Programming Input.
8.0
16
QN
Negative Differential CML Output.
10.0
17
GND
Ground.
18
Q
Positive Differential CML Output.
8.0
10.0
NOTES
8.0 Do not connect pin
9.0 Input pulled to ground
10.0 CML Outputs are internally AC coupled
Circuit Board Footprint Recommendations
Mechanical Dimensions
Figure 2
Figure 3
1.050 MAX [26.67mm]
0.855
0.100
1.030 [26.16mm]
MAX.
.100 [2.54mm]
0.045
0.055
PIN 18
1.080
0.980
PIN 1
.018 [.46mm]
.950 [24.13mm]
MAX.
0.880
0.450 [11.43mm]
MAX.
0.100
.090 [2.29mm]
Preliminary Data Sheet #: SG028
Page 4 of 12
Rev: P01
Date: 07/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Switch from A to B when both are good signals
Figure 4
Ref A
Ref B
LOL portion of
Alarm is
blanked
Alarm
0.5 sec
Sel A/B
New Reference
Qualification time
Switch from A to B when Reference B is lost
Figure 5
Ref A
Ref B
~5ns
Alarm
Sel A/B
Preliminary Data Sheet #: SG028
Page 5 of 12
Rev: P01
Date: 07/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Switch from A to B after Reference A is lost
Figure 6
Ref A
Ref B
LOL Portion
of Alarm is
Blanked
Alarm
125 - 250 µs
Sel A/B
New Reference
Qualification time
Switch from A to B when A is out of range
Figure 7
Ref A
Out of
Range
Ref B
In
Range
Alarm
LOL Portion
of Alarm is
Blanked
Sel A/B
New Reference
Qualification time
Preliminary Data Sheet #: SG028
Page 6 of 12
Rev: P01
Date: 07/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Switch from A to B when B is out of range
Figure 8
Ref A
In
Range
Ref B
Out of
Range
Alarm
LOL Portion
of Alarm is
Blanked
Sel A/B
New Reference
Qualification time
Preliminary Data Sheet #: SG028
Page 7 of 12
Rev: P01
Date: 07/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Typical 622.08 MHz MTIE Measurement
Figure 9
MTIE
(seconds)
10.0E-9
1.0E-9
100.0E-12
100.0E-3
1.0E+0
10.0E+0
100.0E+0
1.0E+3
10.0E+3
Observation Window (Tau)
(seconds)
Typical 622.08 MHz TDEV Measurement
Figure 10
TDEV
(seconds)
1.0E-9
100.0E-12
10.0E-12
100.0E-3
1.0E+0
10.0E+0
100.0E+0
1.0E+3
Tau
(seconds)
Preliminary Data Sheet #: SG028
Page 8 of 12
Rev: P01
Date: 07/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Suggested Differential Output Termination
Figure 13
3.3 VDC
3.3 VDC
3.3 VDC
50
Vcc
Vcc
Q
SCG4600
CML
OUTPUT
D
50 OHM Transmission Line
CML
INPUT
QN
GND
DN
50 OHM Transmission Line
GND
50
3.3 VDC
3.3 VDC
Vcc - 2 VDC
3.3 VDC
50
Vcc
Vcc
Q
SCG4600
CML
OUTPUT
D
50 OHM Transmission Line
LVPECL
INPUT
QN
GND
DN
50 OHM Transmission Line
GND
50
Vcc - 2 VDC
3.3 VDC
3.3 VDC
Vcc
Vcc
Q
SCG4600
CML
OUTPUT
QN
GND
D
50 OHM Transmission Line
LVDS
INPUT
100
DN
50 OHM Transmission Line
GND
Note: Driving a LVDS receiver, LVDS input must be internally biased into common mode range.
LVDS input must be capable of receiving a differential voltage of 1.2 Vpp
Preliminary Data Sheet #: SG028
Page 9 of 12
Rev: P01
Date: 07/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Ordering Information
SCG{XXXX}-{FFF.FFF}{M}
XXXX equals a specific model (4600)
FFF.FFF equals the CML Output frequency (155.52, 622.08 MHz)
M equals MHZ and is added to all part numbers
Example: To order an SCG4600 with an CML Output of 622.08 MHz,
Order part number SCG4600-622.08M
Please contact Connor-Winfield for other frequencies that may be available.
Preliminary Data Sheet #: SG028
Page 10 of 12
Rev: P01
Date: 07/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Preliminary Data Sheet #: SG028
Page 11 of 12
Rev: P01
Date: 07/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Revision
Revision Date
Note
P00
01/17/01
Preliminary informational release
P01
7/19/02
Added new frequency & refomatted