CSD87312Q3E www.ti.com SLPS333 – NOVEMBER 2012 Dual 30-V N-Channel NexFET™ Power MOSFETs FEATURES . 1 • • • • • • Common Source Connection ZZZWLFRP Ultra Low Drain to Drain On-Resistance Space Saving SON 3.3 x 3.3mm Plastic Package Optimized for 5V Gate Drive Low Thermal Resistance x Avalanche Rated x x Pb Free Terminal Plating x RoHS x Compliant x Halogen Free x x APPLICATIONS x +DORJHQ)UHH • Adaptor/USB Input Protection for Notebook PCs and Tablets x DESCRIPTION The CSD87312Q3E is a 30V common-source, dual N-channel device designed for adaptor/USB input protection. This SON 3.3 x 3.3mm device has low drain to drain on-resistance that minimizes losses and offers low component count for space constrained multi-cell battery charging applications. TEXT ADDED FOR SPACING Top View Top View D1 UNIT Drain to Source Voltage 30 V Qg Gate Charge Total (4.5V) 6.3 nC Qgd Gate Charge Gate to Drain RDD(on) Drain to Drain On Resistance (Q1+Q2) VGS(th) Threshold Voltage 0.7 nC VGS = 4.5V 31 mΩ VGS = 8V 27 mΩ 1.0 V ORDERING INFORMATION Device Package Media : CSD87312Q3E SON 3.3 x 3.3mm Plastic Package : 13-Inch Reel Qty Ship 2500 Tape and Reel ABSOLUTE MAXIMUM RATINGS TA = 25°C VALUE UNIT VDS Drain to Source Voltage 30 V VGS Gate to Source Voltage +10/-8 V ID Continuous Drain Current, TC = 25°C(1) 27 A IDM Pulsed Drain Current (2) 45 A PD Power Dissipation 2.5 W TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, single pulse ID = 24A, L = 0.1mH, RG = 25Ω 29 mJ (1) Typical R =63°C/W on 1in² (2 oz.) on 0.060" thick FR4PCB (2) Pulse duration ≤300μs, duty cycle ≤2% TEXT ADDED FOR SPACING VGS vs. RDDon D2 S D1 6/36ದ 6(37(0%(5 VDS D2 D1 D1 PRODUCT SUMMARY TYPICAL VALUE TA = 25°C 60 D2 G y FOR SPACING TEXT ADDED Circuit Image RDS(on) - On-State Resistance (mΩ) • • • TC = 25°C Id = 7A TC = 125ºC Id = 7A 55 T 50 P 45 40 35 30 25 20 0 2 4 6 8 VGS - Gate-to- Source Voltage (V) 10 G001 &RS\ULJKWk7H[DV,QVWUXPHQWV,QFRUSRUDWHG 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated CSD87312Q3E SLPS333 – NOVEMBER 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, ID = 250μA IDSS Drain to Source Leakage Current VGS = 0V, VDS = 24V IGSS Gate to Source Leakage Current VDS = 0V, VGS = +10/-8V VGS(th) Gate to Source Threshold Voltage VDS = VGS, ID = 250μA RDD(on) gfs 30 0.8 V 1 μA 100 nA 1.0 1.3 V Drain to Drain On Resistance (Q1 + Q2) VGS = 4.5V, ID = 7A 31 38 mΩ VGS = 8V, ID = 7A 27 33 mΩ Transconductance VDS = 15V, ID = 7A 39 S Dynamic Characteristics (1) Ciss Input Capacitance 960 1250 pF Coss Output Capacitance Crss Reverse Transfer Capacitance 190 247 pF 12 16 RG Series Gate Resistance pF 5 10 Ω Qg Qgd Gate Charge Total (4.5V) 6.3 8.2 nC Gate Charge Gate to Drain 0.7 Qgs Gate Charge Gate to Source nC 1.9 nC Qg(th) Gate Charge at Vth Qoss Output Charge 1.0 nC 4.0 td(on) nC Turn On Delay Time 7.8 ns tr Rise Time 16 ns td(off) Turn Off Delay Time 17 ns tf Fall Time 2.9 ns VGS = 0V, VDS = 15V, f = 1MHz VDS = 15V, ID = 7A VDS = 15V, VGS = 0V VDS = 15V, VGS = 4.5V, IDS = 7A, RG = 2Ω Diode Characteristics (1) VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time (1) ISD = 7A, VGS = 0V 0.8 VDS= 15V, IF = 7A, di/dt = 300A/μs 1 V 5.3 nC 12.2 ns All Dynamic and Diode Characteristics were measured with respect to one of the two drains, with the other left floating. THERMAL CHARACTERISTICS (TA = 25°C unless otherwise stated) MAX UNIT RθJC Thermal Resistance Junction to Case (1) PARAMETER 4.2 °C/W RθJA Thermal Resistance Junction to Ambient (1) (2) 63 °C/W (1) (2) 2 MIN TYP RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated CSD87312Q3E www.ti.com SLPS333 – NOVEMBER 2012 GATE GATE DRAIN DRAIN Max RθJA = 63°C/W when mounted on 1 inch2 (6.45 cm2) of 2oz. (0.071-mm thick) Cu. Max RθJA = 165°C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu. SOURCE SOURCE M0137-02 M0137-01 TYPICAL MOSFET CHARACTERISTICS (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 60 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) 100 80 60 40 VGS =8V VGS =6V VGS =4.5V 20 0 0 1 2 3 4 VDS - Drain-to-Source Voltage (V) Figure 2. Saturation Characteristics Copyright © 2012, Texas Instruments Incorporated 5 G001 VDS = 5V 40 20 TC = 125°C TC = 25°C TC = −55°C 0 0 1 2 3 4 VGS - Gate-to-Source Voltage (V) 5 G001 Figure 3. Transfer Characteristics Submit Documentation Feedback 3 CSD87312Q3E SLPS333 – NOVEMBER 2012 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 10000 ID = 7A VDS =15V 8 1000 C − Capacitance (pF) VGS - Gate-to-Source Voltage (V) 10 6 4 100 10 2 0 0 2 4 6 8 10 Qg - Gate Charge (nC) 12 1 14 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 0 3 6 G001 Figure 4. Gate Charge TEXT ADDED FOR SPACING G001 TEXT ADDED FOR SPACING RDS(on) - On-State Resistance (mΩ) VGS(th) - Threshold Voltage (V) 30 60 ID = 250uA 1.25 1 0.75 0.5 0.25 0 −75 −25 25 75 125 TC - Case Temperature (ºC) TC = 25°C Id = 7A TC = 125ºC Id = 7A 55 50 45 40 35 30 25 20 175 0 G001 Figure 6. Threshold Voltage vs. Temperature TEXT ADDED FOR SPACING 10 G001 TEXT ADDED FOR SPACING VGS = 4.5V VGS = 8V ID =7A 1.5 1.25 1 0.75 0.5 0.25 −75 4 6 8 VGS - Gate-to- Source Voltage (V) 100 ISD − Source-to-Drain Current (A) 1.75 2 Figure 7. On-State Resistance vs. Gate-to-Source Voltage 2 Normalized On-State Resistance 27 Figure 5. Capacitance 1.5 −25 25 75 125 TC - Case Temperature (ºC) 175 G001 Figure 8. Normalized On-State Resistance vs. Temperature 4 9 12 15 18 21 24 VDS - Drain-to-Source Voltage (V) Submit Documentation Feedback TC = 25°C TC = 125°C 10 1 0.1 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 VSD − Source-to-Drain Voltage (V) 1 G001 Figure 9. Typical Diode Forward Voltage Copyright © 2012, Texas Instruments Incorporated CSD87312Q3E www.ti.com SLPS333 – NOVEMBER 2012 TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 100 1ms 10ms 100ms 1s DC IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) 1000 100 10 1 0.1 Single Pulse Typical RthetaJA =130ºC/W(min Cu) 0.01 0.01 0.1 1 10 VDS - Drain-to-Source Voltage (V) 50 TC = 25ºC TC = 125ºC 10 1 0.01 0.1 TAV - Time in Avalanche (mS) G001 Figure 10. Maximum Safe Operating Area 1 G001 Figure 11. Single Pulse Unclamped Inductive Switching TEXT ADDED FOR SPACING IDS - Drain- to- Source Current (A) 40.0 35.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0 −50 −25 0 25 50 75 100 125 TC - Case Temperature (ºC) 150 175 G001 Figure 12. Maximum Drain Current vs. Temperature Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 5 CSD87312Q3E SLPS333 – NOVEMBER 2012 www.ti.com MECHANICAL DATA Q3E Package Dimensions DIM MILLIMETERS MIN MAX A 0.850 1.050 b 0.280 0.400 c 0.150 0.250 c1 0.150 0.250 d 0.940 1.040 d1 0.160 0.260 d2 0.150 0.250 d3 0.250 0.350 D1 3.200 3.400 D2 2.650 2.750 E 3.200 3.400 E1 3.200 3.400 E2 1.750 1.850 e 0.400 θ 0° K Notes: 1. Pin 2. Pin 3. Pin 4. Pin 6 0.650 TYP L 0.500 0.300 Typ 1-4: Drain 1 5: Gate 6-8: Drain 2 9: Source Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated CSD87312Q3E www.ti.com SLPS333 – NOVEMBER 2012 Recommended PCB Pattern Recommended Stencil Opening For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 7 CSD87312Q3E SLPS333 – NOVEMBER 2012 www.ti.com 1.75 ±0.10 Q3E Tape and Reel Information 4.00 ±0.10 (See Note 1) Ø 1.50 +0.10 –0.00 3.60 1.30 3.60 5.50 ±0.05 12.00 +0.30 –0.10 8.00 ±0.10 2.00 ±0.05 M0144-01 Notes: 1. 10 sprocket hole pitch cumulative tolerance ±0.2 2. Camber not to exceed 1mm IN 100mm, noncumulative over 250mm 3. Material:black static dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified) 5. Thickness: 0.30 ±0.05mm 6. MSL1 260°C (IR and Convection) PbF Reflow Compatible 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing CSD87312Q3E ACTIVE VSON DPB 8 CSD87312Q3E-ASY PREVIEW VSON DPB 8 2500 Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) Pb-Free (RoHS Exempt) CU NIPDAU Level-1-260C-UNLIM -55 to 150 TBD Call TI Call TI -55 to 150 87312E (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 5-Feb-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device CSD87312Q3E Package Package Pins Type Drawing VSON DPB 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 3.6 B0 (mm) K0 (mm) P1 (mm) 3.6 1.2 4.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Feb-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD87312Q3E VSON DPB 8 2500 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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