DRV8800 DRV8801 SLVS855F – JULY 2008 – REVISED JANUARY 2012 www.ti.com DMOS FULL-BRIDGE MOTOR DRIVERS Check for Samples: DRV8800, DRV8801 FEATURES 1 • • • • • • • • 2 • • Low ON-Resistance [Rds(ON)] Outputs Overcurrent Protection Motor Lead Short-to-Supply Protection Short-to-Ground Protection Low-Power Mode Synchronous Rectification Diagnostic Output Internal Undervoltage Lockout (UVLO) Crossover-Current Protection 16-Pin QFN With PowerPAD™ Package APPLICATIONS • • Printers Industrial Automation DESCRIPTION/ORDERING INFORMATION Designed to control dc motors by using pulse width modulation (PWM), the DRV8800/DRV8801 is capable of peak output currents up to ±2.8 A and operating voltages up to 36 V. The PHASE and ENABLE inputs provide dc motor speed and direction control by applying external pulse-width modulation (PWM) and control signals. Internal synchronous rectification control circuitry provides lower power dissipation during PWM operation. Internal circuit protection includes motor lead short-to-supply/short-to-ground, thermal shutdown with hysteresis, undervoltage monitoring of VBB and VCP, and crossover-current protection. The DRV8800/DRV8801 is supplied in a thin-profile 16-pin QFN (RTY) PowerPAD™ package, providing enhanced thermal dissipation. The devices are lead free (Pb free). ORDERING INFORMATION TA PACKAGE (1) (2) Plastic QFN 16 (S-PQFP-16) – RTY –40°C to 85°C TSSOP - PWP (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING DRV8800RTYR DRV8800 DRV8800RTYT DRV8800 DRV8801RTYR DRV8801 DRV8801RTYT DRV8801 DRV8800PWP DRV8800 DRV8800PWPR DRV8800 DRV8801PWP DRV8801 DRV8801PWPR DRV8801 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2012, Texas Instruments Incorporated DRV8800 DRV8801 SLVS855F – JULY 2008 – REVISED JANUARY 2012 www.ti.com DRV8801 RTY PACKAGE (TOP VIEW) nFAULT VPROPI VCP 14 13 VCP 13 15 VREG 14 MODE 1 nFAULT 15 16 MODE 16 DRV8800 RTY PACKAGE (TOP VIEW) nSLEEP 3 10 CP1 nSLEEP 3 10 CP1 ENABLE 4 9 OUT- ENABLE 4 9 OUT- 8 CP2 VBB 11 7 2 SENSE GND 6 CP2 OUT+ 11 5 2 MODE 2 GND 8 GND VBB 12 7 1 SENSE PHASE 6 GND OUT+ 12 5 1 NC PHASE NC – Do not connect TERMINAL FUNCTIONS TERMINAL NO. 2 NAME DRV8800 DESCRIPTION DRV8801 1 PHASE PHASE Phase logic input for direction control 2 GND GND Ground 3 nSLEEP nSLEEP Sleep logic input 4 ENABLE ENABLE Enable logic input 5 NC MODE 2 No connect (DRV8800), Mode 2 logic input (DRV8801) 6 OUT+ OUT+ DMOS full-bridge output positive 7 SENSE SENSE Sense power return 8 VBB VBB Load supply voltage 9 OUT- OUT- DMOS full-bridge output negative 10 CP1 CP1 Charge-pump capacitor 1 11 CP2 CP2 Charge-pump capacitor 2 12 GND GND Ground 13 VCP VCP Reservoir capacitor 14 VREG VPROPI Regulated voltage (DRV8800), Winding current proportional voltage output (DRV8801) 15 nFAULT nFAULT Fault open-drain output 16 MODE MODE 1 Mode logic input PowerPAD PowerPAD Exposed pad for thermal dissipation connect to GND pins Copyright © 2008–2012, Texas Instruments Incorporated DRV8800 DRV8801 SLVS855F – JULY 2008 – REVISED JANUARY 2012 www.ti.com DRV8800 PWP PACKAGE (TOP VIEW) DRV8801 PWP PACKAGE (TOP VIEW) nFAULT 1 16 NC MODE 2 15 VREG PHASE 3 14 VCP GND 4 13 GND nSLEEP 5 12 CP2 ENABLE 6 11 CP1 OUT+ 7 10 OUT- SENSE 8 9 VBB nFAULT 1 16 MODE 2 MODE 1 2 15 VPROPI PHASE 3 14 VCP GND 4 13 GND nSLEEP 5 12 CP2 ENABLE 6 11 CP1 OUT+ 7 10 OUT- SENSE 8 9 VBB NC – Do not connect TERMINAL FUNCTIONS TERMINAL NO. NAME DRV8800 DESCRIPTION DRV8801 1 nFAULT nFAULT Fault open-drain output 2 MODE MODE 1 Mode logic input 3 PHASE PHASE Logic input for direction control 4 GND GND Ground 5 nSLEEP nSLEEP Sleep logic input 6 ENABLE ENABLE Enable logic input 7 OUT+ OUT+ DMOS full-bridge output positive 8 SENSE SENSE Sense power return 9 VBB VBB Load supply voltage 10 OUT- OUT- DMOS full-bridge output negative 11 CP1 CP1 Charge-pump capacitor 1 12 CP2 CP2 Charge-pump capacitor 2 13 GND GND Ground 14 VCP VCP Reservoir capacitor 15 VREG VPROPI Regulated voltage (DRV8800), Winding current proportional voltage output (DRV8801) 16 NC MODE 2 No connect (DRV8800), Mode 2 logic input (DRV8801) PowerPAD PowerPAD Exposed pad for thermal dissipation connect to GND pins Copyright © 2008–2012, Texas Instruments Incorporated 3 DRV8800 DRV8801 SLVS855F – JULY 2008 – REVISED JANUARY 2012 www.ti.com Figure 1. DRV8800 TYPICAL APPLICATION DIAGRAM + - 4 Copyright © 2008–2012, Texas Instruments Incorporated DRV8800 DRV8801 SLVS855F – JULY 2008 – REVISED JANUARY 2012 www.ti.com Figure 2. DRV8801 TYPICAL APPLICATION DIAGRAM + - Copyright © 2008–2012, Texas Instruments Incorporated 5 DRV8800 DRV8801 SLVS855F – JULY 2008 – REVISED JANUARY 2012 www.ti.com Figure 3. DRV8800 FUNCTIONAL BLOCK DIAGRAM .1 uf CP1 CP2 VBB VCP .1 uf Charge Pump VREG Optional VBB Low-Side Gate Supply .22 uf Bias Supply MODE 100 uf PHASE .1 uf OUT+ M ENABLE VDD Control Logic OUT- 3.3K 3.3K nSLEEP SENSE nFAULT UVLO Motor lead Protection STB STG TSD VBB OUT+ OUTSENSE GND GND PAD 6 Copyright © 2008–2012, Texas Instruments Incorporated DRV8800 DRV8801 SLVS855F – JULY 2008 – REVISED JANUARY 2012 www.ti.com Figure 4. DRV8801 FUNCTIONAL BLOCK DIAGRAM .1 uf CP1 VPROPI X5 CP2 VBB VCP SENSE .1 uf Charge Pump VBB MODE 1 Bias Supply MODE 2 PHASE 100 uf .1 uf OUT+ M Control Logic ENABLE VDD OUT3.3K 3.3K nSLEEP SENSE nFAULT UVLO STB Motor lead Protection STG TSD VBB OUT+ OUTSENSE GND GND PAD Copyright © 2008–2012, Texas Instruments Incorporated 7 DRV8800 DRV8801 SLVS855F – JULY 2008 – REVISED JANUARY 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN VBB Load supply voltage VSense MAX (2) 40 Output current 2.8 Sense voltage ±500 VBB to OUTx OUTx to SENSE Logic input voltage (2) VDD ESD rating –0.3 Continuous total power dissipation TA Operating free-air temperature range TJ Maximum junction temperature Tstg Storage temperature range (1) (2) V A mV 36 V 36 V 7 V ±2 kV 500 V Human-Body Model (HBM) Charged-Device Model (CDM) UNIT See Dissipation Ratings Table –40 –40 85 °C 190 °C 125 °C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. THERMAL INFORMATION DRV8800/01 THERMAL METRIC DRV8800/01 RTY PWP 16 PINS 16 PINS θJA Junction-to-ambient thermal resistance (1) 38.1 43.9 θJCtop Junction-to-case (top) thermal resistance (2) 36.7 30.8 θJB Junction-to-board thermal resistance (3) 16.1 25.3 0.3 1.1 (4) ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter (5) 16.2 25 θJCbot Junction-to-case (bottom) thermal resistance (6) 4.1 5.6 (1) (2) (3) (4) (5) (6) UNITS °C/W The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. RECOMMENDED OPERATING CONDITIONS VIN Input voltage, VBB TA Operating free-air temperature 8 Submit Documentation Feedback MIN NOM MAX 8 32 38 V 85 °C –40 UNIT Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): DRV8800 DRV8801 DRV8800 DRV8801 SLVS855F – JULY 2008 – REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN fPWM < 50 kHz IBB Motor supply current TYP 6 Charge pump on, Outputs disabled VIL VIH VIL IIH IIL IIH IIL IIH IIL 0.8 2.7 nSLEEP input voltage 0.8 <1.0 20 ≤–2.0 20 VIN = 2 V 40 100 VIN = 0.8 V 16 40 VIN = 2.7 V 27 50 VIN = 0.8 V <1 10 VIN = 2 V PHASE, MODE input current VIN = 0.8 V ENABLE input current nSLEEP input current VOL nFAULT output voltage Isink = 1 mA VBBNFR VBB nFAULT release 8 V < VBB < 40 V VIHys Input hysteresis, except nSLEEP Rds(ON) RSENSE/ISense voltage trip Vf Body diode forward voltage tpd Propagation delay time tCOD Crossover delay DAGain Differential AMP gain –20 0.4 100 Output ON resistance VTRP 10 2 PHASE, ENABLE, MODE input voltage μA V V μA μA μA V 12 13.8 V 500 800 mV Source driver, IOUT = –2.8 A, TJ = 25°C 0.48 Source driver, IOUT = –2.8 A, TJ = 125°C 0.74 Sink driver, IOUT = 2.8 A, TJ = 25°C 0.35 Sink driver, IOUT = 2.8 A, TJ = 125°C 0.52 SENSE connected to ground through some resistance 500 0.85 mV 1.4 Sink diode, If = 2.8 A 1.4 PWM, Change to source or sink ON 600 PWM, Change to source or sink OFF 100 Ω 0.7 Source diode, If = –2.8 A Sense = 0.1 V to 0.4 V UNIT mA 3.2 Sleep mode VIH MAX V ns 500 ns 5 V/V Protection Circuitry VUV UVLO threshold IOCP Overcurrent threshold VBB increasing tOCP Overcurrent protection period TJW Thermal warning temperature Temperature increasing TJWHys Thermal warning hysteresis Recovery = TJW – TJWHys TJTSD Thermal shutdown temperature Temperature increasing 6.5 7.5 3 Recovery = TJTSD – TJTSDHys TJTSDHys Thermal shutdown hysteresis Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): DRV8800 DRV8801 V A 1.2 ms 160 °C 15 °C 175 °C 15 °C Submit Documentation Feedback 9 DRV8800 DRV8801 SLVS855F – JULY 2008 – REVISED JANUARY 2012 www.ti.com SLEEP ENABLE PHASE MODE VBB VOUT+ 0 VBB VOUT- 0 IOUTX 0 A 1 2 3 4 5 6 7 VIN 1 8 9 VIN 5 6 7 OUT+ OUT- 3 2 OUT+ OUT- 4 8 9 A Charge Pump and VREG power on delay (~200 us) Figure 5. PWM Control Timing 10 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): DRV8800 DRV8801 DRV8800 DRV8801 SLVS855F – JULY 2008 – REVISED JANUARY 2012 www.ti.com VOUT+ VOUT- High-Z IPEAK IOUTx IOCP Enable, Source or Sink BLANK Charge Pump Counter tBLANK tOCP NFAULT Motor Lead Short Condition Normal DC Motor Capacitance Figure 6. Overcurrent Control Timing FUNCTIONAL DESCRIPTION Device Operation The DRV8800/DRV8801 is designed to drive one dc motor. The current through the output full-bridge switches and all N-channel DMOS are regulated with a fixed off-time PWM control circuit. Logic Inputs It is recommended to use a high-value pullup resistor when logic inputs are pulled up to VDD. This resistor limits the current to the input in case an overvoltage event occurs. Logic inputs are nSLEEP, MODE, PHASE, and ENABLE. Voltages higher than 7 V on any logic input can cause damage to the input structure. VREG (DRV8800 Only) This output represents a measurement of the internal regulator voltage. This pin should be left disconnected. A voltage of approximately 7.5 V can be measured at this pin. VPROPI (DRV8801 Only) This output offers an analog voltage proportional to the winding current. Voltage at this terminal is five times greater than the motor winding current (VPROPI = 5×I). VPROPI is meaningful only if there is a resistor connected to the SENSE pin. If SENSE is connected to ground, VPROPI measures 0 V. During slow decay, VPROPI outputs 0 V. VPROPI can output a maximum of 2.5 V, since at 500 mV on SENSE, the H-bridge is disabled. Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): DRV8800 DRV8801 Submit Documentation Feedback 11 DRV8800 DRV8801 SLVS855F – JULY 2008 – REVISED JANUARY 2012 www.ti.com Charge Pump The charge pump is used to generate a supply above VBB to drive the source-side DMOS gates. A 0.1-μF ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1-μF ceramic monolithic capacitor, CStorage, should be connected between VCP and VBB to act as a reservoir to run the high-side DMOS devices. The VCP voltage level is internally monitored and, in the case of a fault condition, the outputs of the device are disabled. Shutdown As a measure to protect the device, faults caused by very high junction temperatures or low voltage on VCP disable the outputs of the device until the fault condition is removed. At power on, the UVLO circuit disables the drivers. Low-Power Mode Control input nSLEEP is used to minimize power consumption when the DRV8800/DRV8801 is not in use. This disables much of the internal circuitry, including the internal voltage rails and charge pump. nSLEEP is asserted low. A logic high on this input pin results in normal operation. When switching from low to high, the user should allow a 1-ms delay before applying PWM signals. This time is needed for the charge pump to stabilize. • MODE 1 (MODE on the DRV8800) Input MODE 1 is used to toggle between fast-decay mode and slow-decay mode. A logic high puts the device in slow-decay mode. • MODE 2 (DRV8801 only) MODE 2 is used to select which set of drivers (high side versus low side) is used during the slow-decay recirculation. MODE 2 is meaningful only when MODE 1 is asserted high. A logic high on MODE 2 has current recirculation through the high-side drivers. A logic low has current recirculation through the low-side drivers. Braking The braking function is implemented by driving the device in slow-decay mode (MODE 1 pin is high) and deasserting the enable to low. Because it is possible to drive current in both directions through the DMOS switches, this configuration effectively shorts out the motor-generated BEMF as long as the ENABLE chop mode is asserted. The maximum current can be approximated by VBEMF/RL. Care should be taken to ensure that the maximum ratings of the device are not exceeded in worse-case braking situations – high-speed and high-inertia loads. Diagnostic Output The nFAULT pin signals a problem with the chip via an open-drain output. A motor fault, undervoltage condition, or TJ > 160°C drives the pin active low. This output is not valid when nSLEEP puts the device into minimum power dissipation mode (i.e., nSLEEP is low). nFAULT stays asserted (nFAULT = L) until VBB reaches VBBNFR to give the charge pump headroom to reach its undervoltage threshold. nFAULT is a status-only signal and does not affect any device functionality. The H-bridge portion still operates normally down to VBB = 8 V with nFAULT asserted. Thermal Shutdown (TSD) Two die-temperature monitors are integrated on the chip. As die temperature increases toward the maximum, a thermal warning signal is triggered at 160°C. This fault drives the nFAULT low, but does not disable the operation of the chip. If the die temperature increases further, to approximately 175°C, the full-bridge outputs are disabled until the internal temperature falls below a hysteresis of 15°C. 12 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): DRV8800 DRV8801 DRV8800 DRV8801 SLVS855F – JULY 2008 – REVISED JANUARY 2012 www.ti.com Control Logic Table (1) PINS (1) (2) OPERATION PHASE ENABLE MODE 1 MODE 2 nSLEEP OUT+ OUT- 1 1 X X 1 H L Forward 0 1 X X 1 L H Reverse X 0 1 0 1 L L Brake (slow decay) 1 0 0 1 1 L H Fast-decay synchronous rectification (2) 0 0 0 X 1 H L Fast-decay synchronous rectification (2) X X X X 0 Z Z Sleep mode X = Don’t care, Z = high impedance To prevent reversal of current during fast-decay synchronous rectification, outputs go to the high-impedance state as the current approaches 0 A. Overcurrent Protection The current flowing through the high-side and low-side drivers is monitored to ensure that the motor lead is not shorted to supply or ground. If a short is detected, the full-bridge outputs are turned off, flag nFAULT is driven low, and a 1.2-ms fault timer is started. After this 1.2-ms period, tOCP , the device is then allowed to follow the input commands and another turnon is attempted (nFAULT becomes high again during this attempt). If there is still a fault condition, the cycle repeats. If after tOCP expires it is determined the short condition is not present, normal operation resumes and nFAULT is deasserted. Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): DRV8800 DRV8801 Submit Documentation Feedback 13 DRV8800 DRV8801 SLVS855F – JULY 2008 – REVISED JANUARY 2012 www.ti.com APPLICATION INFORMATION Power Dissipation First-order approximation of power dissipation in the DRV8800/DRV8801 can be calculated by examining the power dissipation in the full-bridge during each of the operation modes. DRV8800/DRV8801 utilize synchronous rectification. During the decay cycle, the body diode is shorted by the low-Rds(ON) driver, which in turn reduces power dissipation in the full-bridge. In order to prevent shoot through (high-side and low-side drivers on the same side are ON at the same time), DRV8800/DRV8801 implement a 500-ns typical crossover delay time. During this period, the body diode in the decay current path conducts the current until the DMOS driver turns on. High current and high ambient temperature applications should take this into consideration. In addition, motor parameters and switching losses can add power dissipation that could affect critical applications. Drive Current This current path is through the high-side sourcing DMOS driver, motor winding, and low-side sinking DMOS driver. Power dissipation I2R loses in one source and one sink DMOS driver, as shown in Equation 1. 2 PD = I (RDS(on)Source + RDS(onSink)) (1) DRV8800 VBB 1 3 2 1 Drive Current 2 Fast decay with synchronous rectification (reverse) 3 Slow decay with synchronous rectification (brake) 14 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): DRV8800 DRV8801 DRV8800 DRV8801 SLVS855F – JULY 2008 – REVISED JANUARY 2012 www.ti.com DRV8801 VBB 4 1 3 2 1 Drive Current 2 Fast decay with synchronous rectification (reverse) 3 Slow decay with synchronous rectification (brake) Low Side 4 Slow decay with synchronous rectification (brake) High Side Figure 7. Current Path Fast Decay With Synchronous Rectification This decay mode is equivalent to a phase change where the opposite drivers are switched on. When in fast decay, the motor current is not allowed to go negative (direction change). Instead, as the current approaches zero, the drivers turn off. The power calculation is the same as the drive current calculation (see Equation 1). Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): DRV8800 DRV8801 Submit Documentation Feedback 15 DRV8800 DRV8801 SLVS855F – JULY 2008 – REVISED JANUARY 2012 www.ti.com Slow-Decay SR (Brake Mode) In slow-decay mode, both low-side sinking drivers turn on, allowing the current to circulate through the H-bridge’s low side (two sink drivers) and the load. Power dissipation I2R loses in the two sink DMOS drivers: 2 PD = I (2 ´ RDS(on)Sink) (2) SENSE A low-value resistor can be placed between the SENSE pin and ground for current-sensing purposes. To minimize ground-trace IR drops in sensing the output current level, the current-sensing resistor should have an independent ground return to the star ground point. This trace should be as short as possible. For low-value sense resistors, the IR drops in the PCB can be significant, and should be taken into account. NOTE When selecting a value for the sense resistor, SENSE does not exceed the maximum voltage of ±500 mV. The H-bridge is disabled and enters recirculation while motor winding current is above a SENSE voltage equal or greater than 500 mV. Ground A ground power plane should be located as close to the DRV8800/DRV8801 as possible. The copper ground plane directly under the PowerPAD package makes a good location. This pad can then be connected to ground for this purpose. Layout The printed circuit board (PCB) should use a heavy ground plane. For optimum electrical and thermal performance, the DRV8800/DRV8801 must be soldered directly onto the board. On the underside of the DRV8800/DRV8801 is a PowerPAD package, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB. For more information on this technique, please refer to document SLMA002. The load supply pin, VBB, should be decoupled with an electrolytic capacitor (typically 100 μF) in parallel with a ceramic capacitor placed as close as possible to the device. The ceramic capacitors between VCP and VBB, connected to VREG, and between CP1 and CP2 should be as close to the pins of the device as possible, in order to minimize lead inductance. 16 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): DRV8800 DRV8801 PACKAGE OPTION ADDENDUM www.ti.com 5-Jan-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) DRV8800PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DRV8800PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DRV8800RTYR ACTIVE QFN RTY 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DRV8800RTYT ACTIVE QFN RTY 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DRV8801PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DRV8801PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DRV8801RTYR ACTIVE QFN RTY 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DRV8801RTYT ACTIVE QFN RTY 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 5-Jan-2012 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF DRV8801 : • Automotive: DRV8801-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) DRV8800PWPR HTSSOP PWP 16 2000 330.0 12.4 DRV8800RTYR QFN RTY 16 3000 330.0 DRV8800RTYT QFN RTY 16 250 180.0 DRV8801PWPR HTSSOP PWP 16 2000 DRV8801RTYR QFN RTY 16 DRV8801RTYT QFN RTY 16 6.9 5.6 1.6 8.0 12.0 Q1 12.4 4.25 4.25 1.15 8.0 12.0 Q2 12.4 4.25 4.25 1.15 8.0 12.0 Q2 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8800PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 DRV8800RTYR QFN RTY 16 3000 367.0 367.0 35.0 DRV8800RTYT QFN RTY 16 250 210.0 185.0 35.0 DRV8801PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 DRV8801RTYR QFN RTY 16 3000 367.0 367.0 35.0 DRV8801RTYT QFN RTY 16 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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