DAVICOM DM9008AEP

DM9008AEP Product Brief
Ethernet Controller with General Processor Interface
June 2008 Rev.1.0
The DM9008A is a fully integrated and cost-effective low pin count Ethernet
controller with a general processor interface, a Medial Access Control (MAC), a
10Base-T PHY and 16K Byte SRAM. It is designed with low power and high
performance process that support 3.3V with 5V IO tolerance.
The DM9008A supports 8-bit and 16-bit data interfaces to internal memory accesses
for various processors. The DM9008A also supports full duplex mode
The PHY of the DM9008A can interface to the UTP3, 4, 5 in 10Base-T that is fully
compliant with the IEEE 802.3 Spec.. The HP Auto-MDIX function of PHY is also
supported to improve the media connection in convenience.
Block Diagram
Specifications
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48-pin LQFP
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Supports processor interface: byte/word of I/O command to internal memory data
operation
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Comply to 10BASE-T of IEEE 802.3 with
HP Auto-MDIX
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Supports back pressure mode for half-duplex mode flow control
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Support 100M Fiber interface.
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IEEE802.3x flow control for full-duplex mode
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Supports wakeup frame, link status change and magic packet events for remote wake up
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Integrated 16K Byte SRAM
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Build in 3.3V to 2.5V regulator
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Supports early Transmit
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Supports automatically load vendor ID and
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Optional EEPROM configuration
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Very low power consumption mode:
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Power reduced mode (cable detection)
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Power down mode
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Selectable TX drivers for 1:1 or 1.25:1 transformers for additional power reduction.
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Compatible with 3.3V and 5.0V tolerant I/O
product ID from EEPROM
Application
VoIP CPE (ATA, IP Phone, Video Phone)
IP STB, IPC, Internet Radio
Ordering Information
Part Number
DM9008AEP
Pin Count
48
Package
LQFP
(Pb-Free)
DAVICOM Semiconductor, Inc.
No.6, Li-Hsin Rd.VI, Science Park, Hsin-Chu, Taiwan, R.O.C.
TEL: 886-3-5798797
FAX: 886-3-5646929
E-mail: sales@davicom.com.tw