TI UCC28051DG4

UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
TRANSITION MODE PFC CONTROLLER
FEATURES
D Transition Mode PFC Controller for Low
D
D
D
D
D
D
D
D
D
APPLICATIONS
D Switch-Mode Power Supplies for Desktops,
Implementation Cost
Industry Pin Compatibility With Improved
Feature Set
Improved Transient Response With
Slew-Rate Comparator
Zero Power Detect to Prevent OVP During
Light Load Conditions
Accurate Internal VREF for Tight Output
Regulation
Two UVLO Options
Overvoltage Protection (OVP),
Open-Feedback Protection and Enable
Circuits
± 750-mA Peak Gate Drive Current
Low Start-Up and Operating Currents
Lead (Pb)-Free Packages
D
D
Monitors, TVs and Set Top Boxes (STBs)
AC Adapter Front-End Power Supplies
Electronic Ballasts
DESCRIPTION
The UCC38050 and UCC38051 are PFC
controllers for low-to-medium power applications
requiring compliance with IEC 1000-3-2 harmonic
reduction standard. It is designed for controlling a
boost preregulator operating in transition mode
(also referred to as boundary conduction mode or
critical conduction mode operation). It features a
transconductance voltage amplifier for feedback
error processing, a simple multiplier for
generating a current command proportional to the
input
voltage,
a
current-sense
(PWM)
comparator, PWM logic and a totem-pole driver
for driving an external FET.
SIMPLIFIED APPLICATION DIAGRAM
UCC38050
1
VO_SNS VCC
2
COMP
3
MULTIN
4
CS
8
DRV
7
GND
6
ZCD
5
UDG−02125
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2009, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
description (continued)
In the transition mode operation, the PWM circuit is self-oscillating with the turn-on being governed by an
inductor zero-current detector (ZCD pin) and the turn-off being governed by the current-sense comparator.
Additionally, the controller provides features such as peak current limit, default timer, overvoltage protection
(OVP) and enable.
The UCC38050 and UCC38051, while being pin compatible with other industry controllers providing similar
functionality, offer many feature enhancements and tighter specifications, leading to an overall reduction in
system implementation cost. The system performance is enhanced by incorporation of zero power detect
function which allows the controller output to shut down at light load conditions without running into overvoltage.
The device also features innovative slew rate enhancement circuits which improve the large signal transient
performance of the voltage error amplifier. The low start-up and operating currents of the device results in low
power consumption and ease of start-up. Highly accurate internal bandgap reference leads to tight regulation
of output voltage in normal and OVP conditions, resulting in higher system reliability. The enable comparator
ensures that the controller is off if the feedback sense path is broken or if the input voltage is very low.
There are two key parameteric differences between UCC38050 and UCC38051. The UVLO turn-on threshold
of UCC38050 is 15.8 V while for UCC38051 it is 12.5 V. Secondly, the gM amplifier’s source current for
UCC38050 is typically 1.3 mA while for UCC38051 it is 300 μA. The higher UVLO turn-on threshold of the
UCC38050 allows quicker and easier start-up with a smaller VCC capacitance while the lower UVLO turn-on
threshold of UCC38051 allows the operation of the PFC chip to be easily controlled by the downsteam PWM
controller in two-stage power converters. The UCC38050 gM amplifier also provides a full 1.3-mA typical source
current for faster start-up and improved transient response when output is low either at start-up or during
transient conditions. The UCC38051 scales this source current back down to 300- μA typical source current to
gradually increase the error voltage preventing a step increase in line currents at start-up but still provides good
transient response. The UCC38051 is suitable for multiple applications including AC adapters where a
two-stage power conversion is needed. The UCC38050 is suitable for applications such as electronic ballasts
where there is no down-stream PWM conversion and the advantages of smaller VCC capacitor and improved
transient response can be realized.
Devices are available in either the industrial temperature range of –40°C to 105°C (UCC2805x) or commercial
temperature range of 0°C to 70°C (UCC3805x). Package offerings are 8-pin SOIC (D) or 8-pin PDIP (P)
packages.
ORDERING INFORMATION
TA = TJ
−40°C
40°C to 105°C
0°C to 70°C
(1)
2
Packaged Devices(1)
UVLO Threshold
Voltage ON/OFF
(V)
gM Amplifier
Source Current
(μA)
SOIC-8 (D)
PDIP-8 (P)
15.8 / 9.7
−1300
UCC28050D
UCC28050P
12.5 / 9.7
−300
UCC28051D
UCC28051P
15.8 / 9.7
−1300
UCC38050D
UCC38050P
12.5 / 9.7
−300
UCC38051D
UCC38051P
D (SOIC-8) package is available taped and reeled. Add R suffix to device type (e.g.
UCC28050DR) to order quantities of 2,500 devices per reel.
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UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
CONNECTION DIAGRAM
D or P PACKAGE
(TOP VIEW)
VO_SNS 1
8
VCC
COMP 2
7
DRV
MULTIN 3
6
GND
CS 4
5
ZCD
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UCCx805x
UNIT
Supply voltage, VCC
(Internally clamped)
20
V
Input current into VCC clamp
IDD
30
Input current
ZCD
±10
Gate drive current (peak), IDRV
DRV
±750
Input voltage range, VCC
VO_SNS, MULTIN, CS
Maximum negative voltage
VO_SNS, MULTIN, DRV, CS
−0.5
D package
650
mW
1
W
Power dissipation at TA= 50°C
5
P package
Operating junction temperature range, TJ
−55 to 150
Storage temperature, Tstg
−65 to 150
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
mA
V
°C
C
300
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to
GND. Currents are positive into, negative out of the specified terminal.
THERMAL RATINGS
RθJA
Max. thermal resistance junction to ambient
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SO8 (D)
DIP (P)
UNIT
150
100
°C/WV
3
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
ELECTRICAL CHARACTERISTICS
TA = 0_C to 70_C for the UCC3805x, –40_C to 105_C for the UCC2805x, TA = TJ, VCC = 12 V.
supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VCC operating voltage
UNITS
18
Shunt voltage
IVCC = 25 mA
18
19
20
Supply current, off
VCC = VCC turn−on threshold –300 mV
Supply current, disabled
VO_SNS = 0.5 V
75
125
2
4
Supply current, on
75 kHz,
Supply current, dynamic operating
75 kHz,
CL = 0 nF
4
6
CL = 1 nF
5
7
V
μA
mA
UVLO
PARAMETER
VCC turn
turn-on
on threshold
TEST CONDITIONS
TYP
MAX
15.4
15.8
16.4
UCCx8051
12.0
12.5
13.0
9.4
9.7
10.0
UCCx8050
5.8
6.3
6.8
UCCx8051
2.3
2.8
3.3
VCC turn-off threshold
UVLO hysteresis
MIN
UCCx8050
UNITS
V
voltage amplifier (VO_SNS)
PARAMETER
Input voltage (VREF)
TEST CONDITIONS
UCC3805x
UCC2805x
MIN
2.46
2.45
TYP
MAX
2.50
2.50
Input bias current
VCOMP high
VO_SNS = 2.1 V
VCOMP low
VO_SNS = 2.55 V
0.5
μA
1.80
2.45
130
TJ = 25 _C,
VCOMP= 3.5 V
60
90
VO_SNS = 2.1 V,
VCOMP= 3.5 V
−0.2
−1.0
UCCx8051
VO_SNS = 2.1 V,
VCOMP= 2.5 V
−200
−300
VO_SNS = 2.7 V
VCOMP= 3.5 V
0.2
1.0
Sink current
V
5.5
UCCx8050
gM
Source current
4.5
UNITS
2.54
2.55
V
μS
mA
−400
μA
mA
over voltage protection / enable
PARAMETER
TEST CONDITIONS
UCCx8050
Overvoltage reference
UCCx8051
Hysteresis
Enable threshold
MIN
TYP
MAX
VREF + VREF + VREF +
0.165
0.190
0.210
VREF + VREF + VREF +
0.150
0.180
0.210
UNITS
V
UCCx8050
UCCx8051
175
150
200
180
225
210
mV
UCCx8050
0.62
0.67
0.72
V
UCCx8051
0.18
0.23
0.28
V
0.05
0.10
0.20
V
TYP
MAX
UNITS
Enable hysteresis
multiplier
PARAMETER
Multiplier gain constant (k)
TEST CONDITIONS
VMULTIN = 0.5 V,
Dynamic input range, VMULTIN INPUT
Dynamic input range, COMP INPUT
Input bias current, MULTIN
4
COMP = 3.5 V
MIN
0.43
0.65
0 to 2.5
2.5 to 3.8
0 to 3.5
2.5 to 4.0
0.1
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0.87
1/V
V
V
1.0
μA
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
ELECTRICAL CHARACTERISTICS
TA = 0_C to 70_C for the UCC3805x, –40_C to 105_C for the UCC2805x, TA = TJ, VCC = 12 V.
zero power
PARAMETER
Zero power comparator threshold(1)
TEST CONDITIONS
Measured on VCOMP
MIN
2.1
TYP
MAX
2.3
UNITS
2.5
V
zero current detect
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input threshold (rising edge) (1)
1.5
1.7
2.0
V
Hysteresis(1)
250
350
450
mV
5
6
0.30
0.65
0.90
200
400
Input high clamp
I = 3 mA
Input low clamp
I = −3 mA
Restart time delay
V
V
μs
current sense comparator
PARAMETER
Input bias current
Input offset
TEST CONDITIONS
voltage(1)
Delay to output
MIN
CS = 0 V
TYP
MAX
1.0
μA
10
mV
300
450
ns
1.70
1.80
V
−10
CS to DRV
Maximum current sense threshold voltage
1.55
UNITS
0.1
PFC gate driver
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Ω
GT1 pull up resistance
IOUT = –125 mA
5
12
GT1 pull down resistance
IOUT = 125 mA
2
10
Ω
GT1 output rise time
CLOAD = 1 nF,
RLOAD = 10 Ω
25
75
ns
CLOAD = 1 nF,
RLOAD = 10 Ω
10
50
ns
GT1 output fall time
(1) Ensured by design. Not production tested.
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5
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
BLOCK DIAGRAM
2.7/2.5 V
+
0.67/0.57 V
0.23/0.15 V
V0_SNS
2.5 V
COMP
MULTIN
ENABLE
VREF
GOOD
2
PWM
+
ZERO
POWER
DETECT
3
2.3 V
8
VCC
R
Q
7
DRV
S
Q
6
GND
5
ZCD
TIMER
+
+
40 kW
CS
REF
OVP
x
x MULT
+
UVLO
+
VREFAND
BIAS REG
INT. BIAS
gm VOL.
ERROR AMP
1
VREF
OVP
+
4
1.7/1.4 V
5 pF
UDG−02008
PIN DESCRIPTIONS
VO_SNS (Pin 1): This pin senses the boost regulator output voltage through a voltage divider. Internally, this
pin is the inverting input to the transconductance amplifier (with a nominal value of 2.5 V) and also is input to
the OVP comparator. Additionally, pulling this pin below the ENABLE threshold turns off the output switching,
ensuring that the gate drive is held off while the boost output is pre-charging and also ensuring no runaway if
feedback path is open.
COMP (Pin 2): Output of the transconductance error amplifier. Loop compensation components are connected
between this pin and ground. The output current capability of this pin is 10-μA under normal conditions, but
increases to about 1-mA when the differential input is greater than the specified values in the specifications
table. This voltage is one of the inputs to the multiplier, with a dynamic input range of 2.5 V to 3.8 V. During zero
power or overvoltage conditions, this pin goes below 2.5 V nominal. When it goes below 2.3 V, the zero power
comparator is activated which prevents the gate drive from switching.
MULTIN (Pin 3): This pin senses the instantaneous boost regulator input voltage through a voltage divider. The
voltage acts as one of the inputs to the internal multiplier. Recommended operating range is 0 V to 2.5 V at high
line.
PIN DESCRIPTIONS (continued)
CS (Pin 4): This pin senses the instantaneous switch current in the boost switch and uses it as the internal ramp
for PWM comparator. The internal circuitry filters out switching noise spikes without requiring external
components. In addition, an external R-C filter may be required to suppress the noise spikes. An internal clamp
on the multiplier output terminates the switching cycle if this pin voltage exceeds 1.7 V. Additional external
filtering may be required. CS threshold is approximately equal to:
6
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UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
V CS ^ 0.67 (COMP * 2.5 V) ǒMULTIN ) V OFFSETǓ
VOFFSET is approximately 75 mV to improve the zero crossing distortion.
ZCD (Pin 5): This pin is the input for the zero current detect comparator. The boost inductor current is indirectly
sensed through the bias winding on the boost inductor. The ZCD pin input goes low when the inductor current
reaches zero and that transition is detected. Internal active voltage clamps are provided to prevent this pin from
going below ground or too high. If zero current is not detected within 400 μs, a reset timer sets the latch and
gate drive.
GND (Pin 6): The chip reference ground. All bypassing elements are connected to ground pin with shortest loops
feasible.
DRV (Pin 7): The gate drive output for an external boost switch. This output is capable of delivering up to 750-mA
peak currents during turn-on and turn-off. An external gate drive resistor may be needed to limit the peak current
depending on the VCC voltage being used. Below the UVLO threshold, the output is held low.
VCC (Pin 8): The supply voltage for the chip. This pin should be bypassed with a high-frequency capacitor
(greater than 0.1-μF) and tied to GND. The UCC38050 has a wide UVLO hysteresis of approximately 6.3 V that
allows use of lower value supply capacitor on this pin for quicker and easier start-up. The UCC38051 has a
narrow UVLO hysteresis with of about 2.8 V and a start-up voltage of about 12.5 V for applications where the
operation of the PFC device needs to be controlled by a downstream PWM controller.
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7
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
BLOCK DESCRIPTION
UVLO and Reference Block
This block generates a precision reference voltage used to obtain tightly controlled UVLO threshold. In addition
to generating a 2.5-V reference for the non-inverting terminal of the gM amplifier, it generates the reference
voltages for blocks such as OVP, enable, zero power and multiplier. An internal rail of 7.5 V is also generated
to drive all the internal blocks.
Error Amplifier
The voltage error amplifier in UCC3805x is a transcoductance amplifier with a typical transconductance value
of 90 μS. The advantage in using a transconductance amplifier is that the inverting input of the amplifier is solely
determined by the external resistive-divider from the output voltage and not the transient behavior of the
amplifier itself. This allows the VO_SNS pin to be used for sensing over voltage conditions.
The sink and source capability of the error amplifier is approximately 10 μA during normal operation of the
amplifier. But when the VO_SNS pin voltage is beyond the normal operating conditions (VO_SNS >1.05 × VREF,
VO_SNS < 0.88 × VREF), additional circuitry to enhance the slew-rate of the amplifier is activated. Enhanced
slew-rate of the compensation capacitor results in a faster start-up and transient response. This prevents the
output voltage from drifting too high or too low, which can happen if the compensation capacitor were to be
slewed by the normal slewing current of 10-μA. When VO_SNS rises above the normal range, the enhanced
sink current capability is in excess of 1 mA. When VO_SNS falls below the normal range, the UCC38050 can
source more than 1 mA and the UCC38051 sources approximately 300 μA. The limited source current in the
UCC38051 helps to gradually increase the error voltage on the COMP pin preventing a step increase in line
current. The actual rate of increase of VCOMP depends on the compensation network connected to the COMP
pin.
Zero Current Detection and Re-Start Timer Blocks
When the boost inductor current becomes zero, the voltage at the power MOSFET drain end falls. This is
indirectly sensed with a secondary winding that is connected to the ZCD pin. The internal active clamp circuitry
prevents the voltage from going to a negative or a high positive value. The clamp has the sink and source
capability of 10 mA. The resistor value in series with the secondary winding should be chosen to limit the ZCD
current to less than 10 mA. The rising edge threshold of the ZCD comparator can be as high as 2.0 V. The
auxiliary winding should be chosen such that the positive voltage (when the power MOSFET is off) at the ZCD
pin is in excess of 2.0 V.
The restart timer attempts to set the gate drive high in case the gate drive remains off for more than 400 μs
nominally. The minimum guaranteed time period of the timer is 200 μs. This translates to a minimum switching
frequency of 5 kHz. In other words, the boost inductor value should be chosen for switching frequencies greater
than 5 kHz.
Enable Block
The gate drive signal is held low if the voltage at the VO_SNS pin is less than the ENABLE threshold. This feature
can be used to disable the converter by pulling VO_SNS low. If the output feedback path is broken, VO_SNS
is pulled to ground and the output is disabled to protect the power stage.
8
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UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
BLOCK DESCRIPTION (continued)
Zero Power Block
When the output of the gM amplifier goes below 2.3 V, the zero power comparator latches the gate drive signal
low. The slew rate enhancement circuitry of the gM amplifier that is activated during overvoltage conditions slews
the COMP pin to about 2.4 V. This ensures that the zero power comparator is not activated during transient
behavior (when the slew rate enhancement circuitry is enhanced).
Multiplier Block
The multiplier block has two inputs. One is the error amplifier output voltage (VCOMP), while the other is VMULTIN
which is obtained by a resistive divider from the rectified line. The multiplier output is approximately
0.67 × VMULTIN × (VCOMP−2.5 V). There is a positive offset of about 75 mV to the VMULTIN signal because this
improves the zero-crossing distortion and hence the THD performance of the controller in the application. The
dynamic range of the inputs can be found in the electrical characteristics table.
Overvoltage Protection (OVP) Block
The OVP feature in the part is not activated under most operating conditions because of the presence of the
slew rate enhancement circuitry present in the error amplifier. As soon as the output voltage reaches to about
5% to 7% above the nominal value, the slew rate enhancement circuit is activated and the error amplifier output
voltage is pulled below the dynamic range of the multiplier block. This prevents further rise in output voltage.
If the COMP pin is not pulled low fast enough, and the voltage rises further, the OVP circuit acts as a second
line of protection. When the voltage at the VO_SNS pin is more than 7.5% of the nominal value
( >(VREF+0.190)), the OVP feature is activated. It stops the gate drive from switching as long as the voltage at
the VO_SNS pin is above the nominal value (VREF). This prevents the output dc voltage from going above 7.5%
of the nominal value designed for, and protects the switch and other components of the system like the boost
capacitor.
Transition Mode Control
The boost converter, the most common topology used for power factor correction, can operate in two modes
– continuous conduction code (CCM) and discontinuous conduction mode (DCM). Transition mode control, also
referred to as critical conduction mode (CRM) or boundary conduction mode, maintains the converter at the
boundary between CCM and DCM by adjusting the switching frequency.
The CRM converter typically uses a variation of hysteretic control with the lower boundary equal to zero current.
It is a variable frequency control technique that has inherently stable input current control while eliminating
reverse recovery rectifier losses. As shown in Figure 1, the switch current is compared to the reference signal
(output of the multiplier) directly. This control method has the advantage of simple implementation and still can
provide very good power factor correction.
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9
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
TYPICAL APPLICATION DIAGRAM
RUP
−
RAC1
+
RG1
L
COUT
RB
RZC
RS1
RO1
2.7/2.5 V
V REF
OVP
+
INT. BIAS
CB
UVLO
VREF AND
BIAS REG
+
VCC
+
0.67/0.57 V (50)
0.23/0.15 V (51)
VO_SNS
ENABLE
V REF
GOOD
gM E/A
REF
8
OVP
1
2.5 V
RO2
x
÷ MULT
x
+
COMP
7
PWM
+
R
Q
S
Q
DRV
2
MULTIN
CV1
ZERO
POWER
DETECT
3
CV2
RV1
RAC2
RV1
2.3 V
CS
TIMER
+
+
40 k Ω
4
CAC1
CS1
GND
6
ZCD
1.7 V/1.4 V
5
5 pF
UDG−02008
10
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UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
APPLICATION INFORMATION
L
VAC
D
Q
C
Load
RIAC
IAC
ZCD
X
÷ MULT
X
IMO
+
S
Q
Gate Driver
Logic
R
VEA
+
VREF
UDG−02124
Figure 1. Basic Block Diagram of CRM Boost PFC
The power stage equations and the transfer functions of the CRM are the same as the CCM. However,
implementations of the control functions are different. Transition mode forces the inductor current to operate
just at the border of CCM and DCM. The current profile is also different and affects the component power loss
and filtering requirements. The peak current in the CRM boost is twice the amplitude of CCM leading to higher
conduction losses. The peak-to-peak ripple is twice the average current which affects MOSFET switching
losses and magnetics ac losses.
IAVERAGE
(a) CCM
IPEAK
IAVERAGE
(b) DCM
IPEAK
IAVERAGE
Note: Operating Frequency >> 120 Hz
(C) CRM
UDG−02123
Figure 2. PFC Inductor Current Profiles
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11
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
APPLICATION INFORMATION
For low to medium power applications up to approximately 300 W, the CRM boost has an advantage in losses.
The filtering requirement is not severe and therefore is not a disadvantage. For medium to higher power
applications, where the input filter requirements dominate the size of the magnetics, the CCM boost is a better
choice due to lower peak currents (which reduces conduction losses) and lower ripple current (which reduces
filter requirements). The main tradeoff in using CRM boost is lower losses due to no reverse recovery in the
boost diode vs. higher ripple and peak currents.
Design Procedure
For a selected VOUT and minimum switching frequency, the following equations outline the design guidelines
for power stage component selection. Refer to the typical application diagram for reference designators.
Inductor Selection
In the transition mode control, the inductor value needs to be calculated to start the next switching cycle at zero
current. The time it takes to reach zero depends on line voltage and inductance and as shown in equation (1),
L determines the converter’s frequency range.
L+
ǒVAC(min)Ǔ
2
ǒVOUT * Ǹ2
2
F s(min)
V OUT
V AC(min)
Ǔ
P IN
(1)
where
D VAC = RMS line voltage
D VAC(min) = minimum AC line voltage
D PIN = maximum input power averaged over the ac line period
I L(rms) +
P IN
Ǹ2
I L(peak) + 2
V AC(min)
(2)
I L(peak)
Ǹ6
(3)
MOSFET Selection
The main switch selection is driven by the amount of power dissipation allowable. It is important to choose a
device that minimizes gate charge and capacitance and minimizes the sum of switching and conduction losses
at a given frequency.
I Q(rms_crm) +
Ǹ
ǒ
1* 4
6
Ǔ
Ǹ2
ǒ
V AC(min)
9p
Ǔ
V OUT
V Q(max) + V OUT
12
IL PEAK(crm)
(4)
(5)
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UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
APPLICATION INFORMATION
Diode Selection
The effects of the reverse recovery current in the diode can be eliminated with relatively little negative impact
to the system. The diode selection is based on reverse voltage, forward current, and switching speed.
I D(avg) + I OUT(avg)
I D(rms) + I L(peak)
(6)
Ǹ
Ǹ2 V
AC
p V OUT
(7)
V D(peak) + V OUT
(8)
Capacitor Selection
The hold-up time is the main requirement in determining the output capacitance. ESR and the maximum RMS
ripple current rating may also be important especially at higher power levels.
C OUT(min) +
ǒ2
ǒǒ
t HOLDUPǓ
P OUT
ǒ
2
V OUTǓ * V OUT(min)
Ǔ
Ǔ
2
(9)
where:
D VOUT(min) = minimum regulator input voltage for operation
I C(rms) +
Ǹǒ
I L(peak)Ǔ
2
Ǹ2
p
V AC(max)
V OUT
ǒ Ǔ
P OUT
*
V OUT
2
) (ac rms load currents)
2
(10)
Multiplier Set-Up
Select RAC1 and RAC2 so that their ratio uses the full dynamic range of the multiplier input at the peak line voltage
yet, their values are small enough to make the effects of the multiplier bias current negligible. In order to use
the maximum range of the multiplier, select the divider ratio so that VMULTIN evaluated at the peak of the
maximum ac line voltage is the maximum of the minimum dynamic input range of MULTIN, which is 2.5 V.
Choose RAC1 so that it has at least 100-μA at the peak of the minimum ac operating line voltage.
ǒ
Ǔ
Ǹ2
R AC1
+
V
*1
2.5 AC(max)
R AC2
(11)
In extreme cases, switching transients can contaminate the MULTIN signal and it can be beneficial to add
capacitor CAC1. Select the value of CAC1 so that the corner frequency of the resulting filter is greater than the
lowest switching frequency. Keep in mind that the low corner frequency of this filter may compromise the overall
power factor.
www.ti.com
13
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
APPLICATION INFORMATION
Sense Resistor Selection
The current sense resistor value must be chosen to limit the output power and it must also use the full dynamic
range of the multiplier during normal steady state operation. The value of RS1 is thus selected for maximum
power operation at low ac line voltage conditions. In order to use the full dynamic range, set the VSENSE
threshold as a function of the dynamic input range of VCOMP and the peak of the minimum MULTIN voltage.
R S1 +
ǒCOMP(MAX) * COMP(MIN)Ǔ ǒMULTIN(PEAK)@VAC(min) * 0.075Ǔ
0.67
2
Ǹ2
P IN(max)
V AC(min)
(12)
where:
D COMP(MAX) = 3.8 V
D COMP(MIN) = 2.5 V
D MULTIN (PEAK)@VAC(min) + Ǹ2
V AC(min)
ǒ
Ǔ
R AC2
R AC2 ) R AC1
If the exact value RS1 is not available. RS2 and RS3 can be added for further scaling. The CS pin already has
an internal filter for noise due to switching transients. Additional filtering at switching transient frequencies can
be achieved by adding CS1.
Output Voltage Sense Design
Select the divider ratio of RO1 and RO2 to set the VO_SNS voltage to 2.5 V at the desired output voltage. The
current through the divider should be at least 200 μA.
Voltage Loop Design
How well the voltage control loop is designed directly impacts line current distortion. UCC38050 employs a
transconductance amplifier (gM amp) with gain scheduling for improved transient response (refer to Figure 14.
gM Amplifier Output Current vs. Current Sense Voltage). Integral type control at low frequencies is preferred
here because the loop gain varies considerably with line conditions. The largest gain occurs at maximum line
voltage. If the power factor corrector load is dc-to-dc switching converter, the small signal model of the controller
and the power factor corrector, from COMP to PFC output voltage is given by:
^
V OUT(s)
^
V COMP(s)
+
k1
V OUT(avg)
ǒVACǓ
R S1
2
k CRM
C OUT
where:
D VOUT = small signal variations in VOUT
^
D VCOMP = small signal variations in VCOMP
D k1 = multiplier gain = 0.65
D kCRM = peak to average factor = 2
^
14
www.ti.com
1
S
(13)
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
APPLICATION INFORMATION
A controller that has integral control at low frequencies requires a zero near the crossover frequency in order
to be stable. The resulting gM amplifer configuration is shown in Figure 3.
VOUT
+
CV1
CV2
RV1
VREF
UDG−02122
Figure 3. gM Amplifier Configuration
The compensator transfer function is:
AV +
1 ) ǒR V1
gM
C V1 ) C V2
s
ǒ ǒ
1)
R V1
C V1
sǓ
ƪC V1 C V2ƫ
ƪC V1)C V2ƫ
Ǔ Ǔ
s
(14)
where gM = dc transconductance gain = 100 μs
The limiting factor of the gain is usually the allowable third harmonic distortion, though other harmonics can
dominate. The crossover frequency of the control loop will be much lower than twice the ac line voltage. In order
to choose the compensator dynamics, determine the maximum allowable loop gain at twice the line frequency
and solve for capacitor CV2. This also determines the crossover frequency.
C V2 +
ǒ
V AC(max)
4p f AC
V
f CO + pAC
Ǹ
Ǔ ǒ
C V2
2
V OUT(avg) R S1
V OUT
gM
k (crm)
gM k1
R S1 k(cmr)
k1
C OUT(max loop gain @ 2 f
AC)
C OUT
Ǔ
(15)
(16)
Select CV1 so that the low frequency zero is one-tenth of the crossover frequency.
C V1 + 9 C V2
(17)
Select RV1 so that the pole is at the crossover frequency.
[
1
2 p f CO C V2
(18)
www.ti.com
15
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
Bias Current
The bias voltage is supplied by a bias winding on the inductor. Select the turns ratio so that sufficient bias voltage
can be achieved at low ac line voltage. The bias capacitor must be large enough to maintain sufficient voltage
with ac line variations. Be sure to connect a 0.1-μF bypass capacitor between the VCC pin and the GND pin
as close to the integrated circuit as possible. For wide line variations, a resistor, RB, is necessary in order to
permit clamping action. The bias voltage should also be clamped with an external zener diode to a maximum
of 18 V.
Zero Current Detection
The zero current detection activates when the ZCD voltage falls below 1.4 V. The bias winding can provide the
necessary voltage. This pin has a clamp at approximately 5 V. Add a current limiting resistor, RZC, to keep the
maximum current below 1 mA.
16
www.ti.com
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
REFERENCE DESIGN
A reference design is discussed in 100-W Universal Line Input PFC Boost Converter Using the UCC38050, TI
Literature No. SLUU134. The UCC38050 is used for the off-line power factor corrected pre-regulator with
operation over a universal input range of 85 V to 265 V with a 400 Vdc regulated output. The schematic is shown
in Figure 4 and the board layout for the reference design is shown in Figure 5. Refer to the document for further
details.
+
+
+
Figure 4. Universal Line Input 100-W Boost Converter Reference Design Schematic
Figure 5. Reference Design Board Layout
www.ti.com
17
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
TEMPERATURE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
6
4.0
ICC = ON
75 kHZ, 1 nF
ICC − Supply Current − mA
5
3.0
2.5
2.0
UCC38050
1.5
UCC38051
ICC − Supply Current − mA
3.5
1.0
0.5
4
8
12
VCC − Supply Voltage − V
16
ICC = ON
75 kHZ, No Load
3
2
ICC = ON
No Switching
1
0
−50
0
0
4
20
−25
UVLO THRESHOLDS
vs
TEMPERATURE
2.60
UVLO ON
(UCCx8050)
18
2.58
16
VREF − Reference Voltage − V
VUVLO − UVLO Threshold VOltage − V
125
REFERENCE VOLTAGE
vs
TEMPERATURE
20
UVLO ON
(UCCx8051)
14
12
UVLO OFF
10
8
6
UVLO HYSTERESIS (UCCx8050)
4
0
25
50
75
TJ − Temperature − °C
100
2.54
2.52
2.50
2.48
2.46
2.42
UVLO HYSTERESIS (UCCx8051)
−25
2.56
2.44
2
125
2.40
−50
−25
0
25
50
75
TJ − Temperature − °C
Figure 9
Figure 8
18
100
Figure 7
Figure 6
0
−50
75
0
25
50
TJ − Temperature − °C
www.ti.com
100
125
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
TYPICAL CHARACTERISTICS
CURRENT SENSE INPUT THRESHOLD
vs
MULTIPLIER INPUT VOLTAGE
1.800
COMP = 3.75 V
VCS − CS Input Voltage − V
1.6
COMP = 3.5 V
1.4
1.2
COMP = 3.25 V
1.0
0.8
0.6
COMP = 3 V
COMP = 2.5 V
0.4
0.2
0.0
COMP = 2.75 V
0
0.5
1.0
1.5
2.0
2.5
VMULTIN − Multiplier Input Voltage− V
VCS(max)− Maximum Current Sense Threshold − V
1.8
3.0
MAXIMUM CURRENT SENSE THRESHOLD
vs
TEMPERATURE
1.775
1.750
1.725
1.700
1.675
1.650
1.625
1.600
1.575
1.550
−50
−25
100
125
100
125
Figure 11
Figure 10
TRANSCONDUCTANCE
vs
TEMPERATURE
CS TO OUTPUT DELAY TIME
vs
TEMPERATURE
120
450
400
gM − Transconductance − μS
tDELAY − Cureent Sense to Output Delay Time − ns
0
25
50
75
TJ − Temperature − °C
350
300
250
200
150
110
100
90
80
100
70
50
0
−50
−25
0
25
50
75
TJ − Temperature − °C
100
125
60
−50
−25
0
25
50
75
TJ − Temperature − °C
Figure 13
Figure 12
www.ti.com
19
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
TYPICAL CHARACTERISTICS
gM AMPLIFIER OUTPUT CURRENT
vs
OUTPUT SENSE VOLTAGE
gM AMPLIFIER OUTPUT CURRENT
vs
OUTPUT SENSE VOLTAGE
(SMALL SIGNAL VIEW)
0.012
ICOMP − gM Amplifier Output Current − mA
ICOMP − gM Amplifier Output Current − mA
1.5
1.0
0.5
UCCx8051
0
−0.5
UCCx8050
−1.0
−1.5
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
0.008
0.004
0
−0.004
−0.008
−0.012
2.40
VVO_SNS − Output Sense Voltage − V
2.45
2.50
2.55
2.60
VVO_SNS − Output Sense Voltage − V
Figure 15
Figure 14
OVERVOLTAGE PROTECTION THRESHOLDS
vs
TEMPERATURE
VOLTAGE AMPLIFIER OUTPUT
vs
TIME (UCC38050)
2.80
5.5
2.75
5.0
VSENSE
4.5
4.0
3.5
3.0
VAO
2.5
VOVP − OVP Threshold Voltage − V
VCOMP − Voltage Amplifier Output − V
CLOAD = 10 nF
2.65
OVP ON
2.60
2.55
OVP OFF
2.50
2.45
2.0
2.40
−50
1.5
25 μs / div
−25
0
25
50
75
TJ − Temperature − °C
Figure 17
Figure 16
20
2.70
www.ti.com
100
125
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
TYPICAL CHARACTERISTICS
ZERO CURRENT DETECTION CLAMP
RESTART TIME
vs
TEMPERATURE
CURRENT vs VOLTAGE
10
600
8
500
tRESTART − Restart Time − μs
IZCD − ZCD Current − mA
6
4
2
0
−2
−4
−6
400
300
200
100
−8
−10
0
1
2
3
4
5
6
0
7
−50
−25
0
VZCD − ZCD Voltage − V
100
125
Figure 19
Figure 18
OUTPUT SATURATION VOLTAGE
vs
SOURCE CURRENT
OUTPUT SATURATION VOLTAGE
vs
SINK CURRENT
8
2.5
VCC = 12 V
VCC = 12 V
VOUT(sat) − Output Saturation Voltage − V
VOUT(sat) − Output Saturation Voltage − V
25
50
75
TJ − Temperature − °C
7
6
5
4
3
2
1
2.0
1.5
1.0
0.5
0
0
100
200
300
400
500
600
700
800
ISOURCE − Source Current − mA
Figure 20
0
0
100
200 300 400 500 600
ISINK − Sink Current − mA
700
800
Figure 21
www.ti.com
21
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
0.050 (1,27)
8
0.010 (0,25)
5
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
4
0.010 (0,25)
0°− 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047/E 09/01
NOTES: A.
B.
C.
D.
22
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
www.ti.com
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
MECHANICAL DATA
P (PDIP)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
www.ti.com
23
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
UCC28050D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
28050
UCC28050DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
28050
UCC28050DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
28050
UCC28050DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
28050
UCC28050P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
28050
UCC28050PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
28050
UCC28051D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
28051
UCC28051DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
28051
UCC28051DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
28051
UCC28051DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 105
28051
UCC28051P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 105
28051
UCC28051PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 105
28051
UCC38050D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
38050
UCC38050DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
38050
UCC38050DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
38050
UCC38050DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
38050
UCC38050P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
38050
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
UCC38050PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
38050
UCC38051D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
38051
UCC38051DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
38051
UCC38051P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
38051
UCC38051PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
38051
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
UCC28050DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
UCC28051DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
UCC38050DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC28050DR
SOIC
D
8
2500
340.5
338.1
20.6
UCC28051DR
SOIC
D
8
2500
340.5
338.1
20.6
UCC38050DR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
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