TI TNETA1585

TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
D
D
D
D
D
D
D
D
D
Single-Chip Scheduler for Scheduling
Available Bit Rate (ABR) Connections
Used With the TNETA1575 to Provide a
Complete Solution for Segmentation and
Reassembly of Data on ABR Connections
as Specified in the Asynchronous Transfer
Mode (ATM) Forum’s Traffic Management
4.0 Document (TM4.0) and ITU-TI.371
Supports Scheduling of Variable-Bit-Rate
Non-Real Time (VBR-nrt) Using
Host-Programmable Peak Cell Rate (PCR),
Sustained Cell Rate (SCR), and Maximum
Burst Size (MBS)
On-Chip Self-Sorting FIFO-Based
Scheduler Used to Schedule the
Transmission of Cells for All Connections
Simultaneously Supports Both Virtual Path
(VP) and Virtual Channel (VC) Level ABR
Traffic Management
Provides Scheduling for up to 2047 ABR
Connections Required for Large-Scale LAN
Emulation Installations
On-Chip Processors Implement the
End-System Behavior as Defined in TM4.0,
Providing a High-Performance and Flexible
Solution to Track Future Standards
On-Chip Instruction RAMs Hold the
Microcode for the Source and Destination
Processors, Providing Fast Execution of
Code on Chip
Configuration Support for All Primary and
Optional TM4.0 Parameters, Providing
Maximum Implementation Flexibility
D
D
D
D
D
D
D
D
D
Supports TM4.0-Defined Resource
Management (RM)-Cell Formats and
Provides the RM-Cell Payload and
Information on How to Configure the
RM-Cell Header to the Segmentation and
Reassembly (SAR) Device
Supports Out-of-Rate Forward and
Backward RM-Cell Generation to Prevent
Deadlock Situations When the Rates of
Sources and Destinations Are Driven to or
Below a Minimum Cell Rate of 10 Cells Per
Second
Processes Received RM Cells, Maintaining
Parameters and Variables in Accordance
With TM4.0
Hardware Assistance Is Provided for 1/ACR
Calculations That Support Scheduling
Operations to Maximize Performance
Hardware Assistance Is Provided for 15-Bit
Floating-Point To/From Integer
Conversions to Maximize Performance
UTOPIA Level-1 Revision-2.01 Receive
(Observe-Only) Cell Interface
Internal 8-Cell Receive FIFO
Receive-Cell Interface Can Be Programmed
to Operate as Either a Physical (PHY-Layer)
Interface or as a SAR/Switch (ATM-Layer)
Interface.
Supports Boundary Scan Through a
Five-Wire JTAG Interface in Accordance
With IEEE Std 1149.1-1990 (Includes IEEE
Std 1149.1a-1993) IEEE Standard TestAccess-Port and Boundary-Scan
Architecture
description
The TNETA1585 is an asynchronous transfer mode (ATM) programmable traffic management scheduler device
that is used with a segmentation and reassembly (SAR) device to provide a flexible, high-performance solution
for the available bit rate (ABR) service category. Its programmability enables it to support other special modes
including variable-bit-rate non-real-time (VBR-nrt) service category and virtual-path (VP)-level ABR in addition
to and simultaneously with ABR. Combining the TNETA1585 with the TNETA1575 provides a high-performance
solution for classical LAN-to-ATM backbone applications, including high-performance networking hubs.
This data sheet provides information on the device hardware specifications that includes device interfaces,
timing diagrams, electrical characteristics, terminal and package information, and an overview of device
operation. All information on the TNETA1585 data structures, configuration, and features is provided in the
TNETA1585 Programmer’s Reference Guide, literature number SDNU016.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
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8
9
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13
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15
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19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
NC – No internal connection
2
PMWE
NC
PMOE
PMDATA31
V CC
PMDATA30
PMDATA29
PMDATA28
GND
PMDATA27
PMDATA26
PMDATA25
V CC(5V)
PMDATA24
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
SCDATA29 45
VCC 46
SCDATA28 47
SCDATA27 48
SCDATA26 49
GND 50
SCDATA25 51
SCDATA24 52
SCDATA23 53
VCC(5V) 54
SCDATA22 55
SCDATA21 56
NC 57
GND 58
SCDATA20 59
SCDATA19 60
NC 61
SCDATA18 62
VCC 63
SCDATA17 64
SCDATA16 65
SCDATA15 66
GND 67
SCDATA14 68
SCDATA13 69
SCDATA12 70
VCC 71
NC 72
SCDATA11 73
SCDATA10 74
SCDATA9 75
NC 76
GND 77
SCDATA8 78
SCDATA7 79
VCC(5V) 80
SCDATA6 81
SCDATA5 82
SCDATA4 83
GND 84
SCDATA3 85
SCDATA2 86
SCDATA1 87
SCDATA0 88
TDI
TDO
TMS
TCK
GND
TRST
TESTMODE
VCC(5V)
CONFIG
RXDATA0
VCC
RXDATA1
NC
RXDATA2
GND
RXDATA3
NC
RXDATA4
RXDATA5
RXDATA6
VCC(5V)
RXDATA7
RXSOC
RXCLAV
RXEN
RXCLK
GND
NC
CLOCK
NC
SCSEL
NC
SCAD5
SCAD4
SCAD3
SCAD2
VCC
SCAD1
SCAD0
GND
SCWE
SCOE
SCDATA31
SCDATA30
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
NC
NC
GND
NC
PMAD15
PMAD15
V CC
PMAD14
PMAD13
PMAD12
GND
PMAD11
NC
PMAD10
PMAD9
V CC
NC
PMAD8
PMAD7
PMAD6
GND
PMAD5
PMAD4
PMAD3
V CC
PMAD2
PMAD1
NC
PMAD0
GND
PGF PACKAGE
( TOP VIEW )
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PMDATA23
PMDATA22
GND
PMDATA21
PMDATA20
PMDATA19
VCC
PMDATA18
PMDATA17
PMDATA16
GND
PMDATA15
NC
PMDATA14
PMDATA13
VCC
NC
PMDATA12
PMDATA11
PMDATA10
GND
PMDATA9
PMDATA8
PMDATA7
VCC(5 V)
PMDATA6
PMDATA5
NC
PMDATA4
GND
PMDATA3
NC
PMDATA2
PMDATA1
VCC
PMDATA0
COPFULL
DAX
GND
TCCX
RCCX
RESET
VCC
INTR
TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
35
30
25
20
15
10
5
1
45
155
50
150
55
145
60
140
65
135
70
130
75
125
90
95
100
105
110
115
120
NC
NC
GND
NC
PMAD15
PMAD15
V CC
PMAD14
PMAD13
PMAD12
GND
PMAD11
PMAD10
PMAD9
V CC
PMAD8
PMAD7
PMAD6
GND
PMAD5
PMAD4
PMAD3
V CC
PMAD2
PMAD1
PMAD0
GND
PMWE
PMOE
PMDATA31
V CC
PMDATA30
PMDATA29
PMDATA28
GND
PMDATA27
PMDATA26
PMDATA25
VCC(5V)
PMDATA24
PMDATA22
PMDATA23
85
PMDATA19
PMDATA20
PMDATA21
GND
80
INTR
V CC
RESET
RCCX
TCCX
GND
DAX
COPFULL
PMDATA0
V CC
PMDATA1
PMDATA2
PMDATA3
GND
PMDATA4
PMDATA5
PMDATA6
VCC(5V)
PMDATA7
PMDATA8
PMDATA9
GND
PMDATA10
PMDATA11
PMDATA12
SCDATA1
SCDATA0
40
V CC
PMDATA13
PMDATA14
PMDATA15
GND
PMDATA16
PMDATA17
PMDATA18
V CC
SCDATA29
V CC
SCDATA28
SCDATA27
SCDATA26
GND
SCDATA25
SCDATA24
SCDATA23
VCC(5V)
SCDATA22
SCDATA21
GND
SCDATA20
SCDATA19
SCDATA18
V CC
SCDATA17
SCDATA16
SCDATA15
GND
SCDATA14
SCDATA13
SCDATA12
V CC
SCDATA11
SCDATA10
SCDATA9
GND
SCDATA8
SCDATA7
VCC(5V)
SCDATA6
SCDATA5
SCDATA4
GND
SCDATA3
SCDATA2
RXEN
RXCLAV
RXSOC
RXDATA7
V CC(5V)
RXDATA6
RXDATA5
RXDATA4
RXDATA3
GND
RXDATA2
RXDATA1
V CC
RXDATA0
CONFIG
V CC(5V)
TESTMODE
TRST
GND
TCK
TMS
TDO
TDI
SCDATA30
SCDATA31
SCOE
SCWE
GND
SCAD0
SCAD1
V CC
SCAD2
SCAD3
SCAD4
SCAD5
SCSEL
NC
CLOCK
GND
RXCLK
PCM PACKAGE
(TOP VIEW)
NC – No internal connection
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
Terminal Functions
slave interface
TERMINAL
I/O
RESET
STATE
29–32
34–35
I (TTL)
I
SCDATA31–
SCDATA31
SCDATA0
43–45
47–49
1 3
51–53
55 56
55–56
59
60
59–60
62
64–66
68 0
68–70
73–75
73 75
78–79
78
79
81–83
85–88
39 41
39–41
43–45
43 45
47–49
51–52
54–56
54
56
58 60
58–60
62 64
62–64
66–68
70–71
73–75
73
75
77 80
77–80
I/O
(TTL/
CMOS)
Hi Z
Hi-Z
SCOE
42
38
I (TTL)
I
Slave-control output enable. SCOE is active low. When SCOE and SCSEL are
low, TNETA1585 reads are enabled.
SCSEL
31
28
I (TTL)
I
Slave-control select. SCSEL is active low. SCSEL enables the slave-control
interface.
SCWE
41
37
I (TTL)
I
Slave-control write enable. SCWE is active low. When SCWE and SCSEL are
low, TNETA1585 writes are enabled.
NAME
NO.
PGF
NO.
PCM
SCAD5 SCAD0
SCAD5–SCAD0
33–36
38–39
DESCRIPTION
Slave control address.
Slave-control
address SCAD5–SCAD0
SCAD5 SCAD0 consists of a 6-bit
6 bit address.
address
Slave control data.
data SCDATA31–SCDATA0
SCDATA31 SCDATA0 consists of 32-bit
32 bit data.
data
Slave-control
coprocessor interface
TERMINAL
4
NAME
NO.
PGF
NO.
PCM
I/O
RESET
STATE
DESCRIPTION
CLOCK
29
26
I (TTL)
I
Clock. The RCCX, TCCX, and DAX inputs are clocked into the device on the
rising edge of the clock input. This clock also is used as an operating clock
source for the TNETA1585.
Low
Receive-FIFO full indication. COPFULL provides an indication of the status of
the receive UTOPIA interface FIFO. When the PHY/ATM input is low, COPFULL
goes high when the receive UTOPIA interface FIFO is full. When the PHY/ATM
input is high, COPFULL goes high when the FIFO is within 4 bytes of being full.
COPFULL
96
88
O
(CMOS)
DAX
95
87
I (TTL)
I
Data-availability indication. DAX provides an indication to the device when data
is available on a particular channel or when the SAR has completed
segmentation of queued packets.
INTR
89
81
O
(CMOS)
High
Local interrupt. INTR provides an interrupt indication from the traffic
coprocessor to the SAR.
RCCX
92
84
I (TTL)
I
Receive-cell status indication. RCCX provides an indication to the device that
a cell has been received on the UTOPIA interface along with the receive channel
number assigned to the cell.
RESET
91
83
I (TTL)
I
Reset. When low, RESET resets the device.
TCCX
93
85
I (TTL)
I
Transmit-cell status indication. TCCX provides an indication to the device that
a cell has been transmitted from the SAR along with the channel number of that
cell.
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TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
Terminal Functions (Continued)
receive-UTOPIA interface
TERMINAL
NAME
NO.
PGF
NO.
PCM
I/O
RESET
STATE
DESCRIPTION
RXCLK
26
24
I (TTL)
I
Receive clock. RXCLK is the data transfer/synchronization clock for
synchronizing transfers on RXDATA.
RXDATA7
RXDATA7–
RXDATA0
22
20–18
20
18
16
14
12
10
20
18–15
13–12
10
I (TTL)
I
Receive data
data. Eight-bit
Eight bit data lines.
lines RXDATA7 is the most significant bit.
bit
RXCLAV
24
22
I (TTL)
I
Receive-cell available. RXCLAV is an indication that a transfer of a complete
cell can be accepted.
RXEN
25
23
I (TTL)
I
Receive enable. RXEN indicates to the TNETA1585 when RXDATA contains
a valid byte.
RXSOC
23
21
I (TTL)
I
Receive start of cell. RXSOC is received by the device when RXDATA contains
the first valid byte of the cell.
parameter-memory interface
TERMINAL
I/O
RESET
STATE
DESCRIPTION
155
153–151
149–147
145–143
141 139
141–139
137–135
137
135
O (CMOS)
Low
Parameter-memory
y address. PMAD15–PMAD0 provides a 16-bit
physical address to the parameter memory.
PMDATA31
PMDATA31–
PMDATA0
143
141 139
141–139
137 135
137–135
133–131
133
131
129–127
125–123
121
119 118
119–118
115–113
115 113
111–109
107–106
104
102
100–99
100
99
97
131
129–127
125–123
121 119
121–119
117–115
117 115
113–111
109–107
105–103
10 103
101–99
101 99
97–95
97 95
93–91
89
I/O
(TTL/CMOS)
Low
Parameter-memory
y data. PMDATA31–PMDATA0 provides 32-bit data
to/from the parameter memory.
PMWE
146
133
O (CMOS)
High
Parameter-memory write enable. The address and data are valid when
PMWE is low.
PMAD15
172
156
O (CMOS)
High
Inverse of PMAD15. PMAD15 can be used with PMAD15 to provide
SRAM bank switching.
PMOE
144
132
O (CMOS)
High
Parameter-memory output enable. The PMAD15–PMAD0 address is
valid when PMOE is low. Data is read into the TNETA1585 on the rising
edge of PMOE.
NAME
NO.
PGF
NO.
PCM
PMAD15
PMAD15–
PMAD0
171
169–167
165
163–162
159–157
155 153
155–153
151
150
151–150
148
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• DALLAS, TEXAS 75265
5
TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
Terminal Functions (Continued)
boundary-scan interface
TERMINAL
NAME
NO.
PGF
NO.
PCM
I/O
RESET
STATE
TCK
4
4
I (TTL)
I
Test clock. TCK is used to clock the test-access-port (TAP) operation.
TDI
1
1
I (TTL)
I
Test data input. TDI is used to shift serial test data and instruction into the device
during TAP operation.
TDO
2
2
O
(CMOS)
Hi-Z
Test data output. TDO is used to shift serial test data and instructions out of the
device during TAP operation.
TMS
3
3
I (TTL)
I
Test mode select. TMS is used to control the state of the TAP controller.
TRST
6
6
I (TTL)
I
Test reset. TRST asynchronously forces the TAP controller to a known state.
DESCRIPTION
DESCRIPTION
miscellaneous signals
TERMINAL
NAME
NO.
PGF
NO.
PCM
I/O
RESET
STATE
CONFIG
9
9
I (TTL)
I
This terminal must be tied low during normal operation.
TESTMODE
7
7
I (TTL)
I
Test/normal mode. TESTMODE selects test mode when high and normal
operation when low.
power and ground
TERMINAL
6
DESCRIPTION
NAME
NO.
PGF
NO.
PCM
GND
5, 15, 27, 40,
50, 58, 67, 77,
84, 94, 103,
112, 122, 130,
138, 147, 156,
166, 174
5, 14, 25, 36,
46, 53, 61, 69,
76, 86, 94,
102, 110, 118,
126, 134, 142,
150, 158
Ground. GND is the 0-V reference for the device.
NC
13, 17, 28, 30,
32, 57, 61, 72,
76, 101, 105,
116, 120, 145,
149, 160, 164,
173, 175, 176
27, 157, 159,
160
No internal connection. NC terminals have no internal connections. For potential
functionality additions, it is recommended that these terminals not be connected to any
signal, power, or ground connection.
VCC
11, 37, 46, 63,
71, 90, 98,
117, 126, 142,
152, 161, 170
11, 33, 42, 57,
65, 82, 90,
106, 114, 130,
138, 146, 154
Supply voltage. VCC is the 3.3-V (with respect to GND) supply for the functional logic
gates.
VCC(5V)
8, 21, 54, 80,
108, 134
8, 19, 50, 72,
98, 122
Supply voltage. VCC(5 V) is the 5-V secondary supply voltage for the clamp diodes of
5-V tolerant input and output buffers. The clamp diodes provide protection for the
buffers in a 5-V switching environment.
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TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
detail description
The TNETA1585 device contains the following interfaces:
•
•
•
•
COPI interface:
Slave-control interface
Coprocessor interface
Receive-UTOPIA interface
Parameter-memory interface
JTAG interface
COPI interface
The traffic-coprocessor interface (COPI) provides the means of communication between the TNETA1585 and
the master device. It consists of the slave interface and the coprocessor interface.
slave-control interface
The slave-control (SC) interface consists of a 32-bit data bus, a 6-bit address bus, an output-enable terminal
(SCOE), a write-enable terminal (SCWE), and a select terminal (SCSEL). When used with the TNETA1575 SAR
device, the TNETA1585 slave-control interface is mapped into the SAR’s control-memory space starting at
address 10000h and extending to address 1FFFFh. This equates to a total address space of 64K 32-bit words
with 64 locations applicable to the TNETA1585. The TNETA1575 uses its select terminal to choose between
its control memory and the TNETA1585. The TNETA1585 is a slave to all to-and-from transfers. These are
initiated by the master device that is a SAR or switch port controller.
Table 1 lists the slave registers that are directly accessible through the slave interface. A heading specifies the
slave-interface addresses as control-memory addresses because of the TNETA1575 mapping of the
TNETA1585. Each register is either host associated or SAR associated.
The host accesses the host-associated registers through the SAR and are used by the host to initialize the
TNETA1585 and to configure the TNETA1585’s other internal-data structures and associated parameter
memory. The host has access to the TNETA1585’s other internal-data structures and associated parameter
memory through the host-associated read address, read data, write address, and write data registers as
described in the TNETA1585 Programmer’s Reference Guide, literature number SDNU016.
The SAR-associated registers are used by the SAR to obtain information related to the scheduling of cells. The
next-cell register indicates when one of the TNETA1585 scheduled connections is ready to transmit and what
type of cell to transmit. It also provides information on how to build the associated cell’s header. In addition, if
the SAR is instructed by the TNETA1585 to transmit an RM cell for ABR connections, the SAR obtains the
properly formatted RM-cell payload from one of the RM-cell-contents FIFOs of the TNETA1585.
POST OFFICE BOX 655303
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7
TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
slave-control interface (continued)
Table 1. Slave-Control Interface Register Map
DESCRIPTION
HOST/SAR
ASSOCIATED
R/W
CONTROL
MEMORY ADDRESS
(TNETA1575)
PCI OFFSET
ADDRESS
(TNETA1575)
Next-cell register
SAR
R
h10000
h40000
RM-cell-contents FIFO A
SAR
R
h10001
h40004
RM-cell-contents FIFO B
SAR
R
h10002
h40008
RM-cell-contents FIFO C
SAR
R
h10003
h4000C
RM-cell-contents FIFO D
SAR
R
h10004
h40010
Reserved
N/A
N/A
h10005–7
h40014–1C
Configuration register
Host
R/W
h10008
h40020
Status register
Host
R
h10009
h40024
Interrupt-mask register
Host
R/W
h1000A
h40028
Schedule-on register
Host
W
h1000B
h4002C
Schedule-off register
Host
W
h1000C
h40030
Read-address register
Host
R/W
h1000D
h40034
Read-data register
Host
R
h1000E
h40038
Write-address register
Host
R/W
h1000F
h4003C
Write-data register
Host
W
h10010
h40040
Clock-frequency register
Host
R/W
h10011
h40044
Revision-number register
Host
R
h10012
h40048
ACR-low register
Host
R
h10013
h4004C
ACR-OK register
Host
R
h10014
h40050
h40054–64
Reserved
N/A
N/A
h10015–19
General-purpose registers
Host
R/W
h1001A–1D
h40068–74
Reserved
N/A
N/A
h100IE–3F
h40078–FC
The following describes the SAR-associated registers with respect to what the TNETA1575 requires of the
interface. However, these registers can be used by other COPI-compliant ATM-layer devices to assist in the
scheduling of cells and the generation of RM cells.
next-cell register
The TNETA1575 uses the next-cell register to determine if one of the TNETA1585’s scheduled connections is
ready to transmit and, if so, which channel and what type of cell (i.e., data, forward RM, backward RM). This
register is read only.
READY
CELL COUNT
RESERVED
CHANNEL NUMBER
CLP
CELL TYPE
3
2–0
BIT
31
30–26
25–15
14–4
Bit 31 (ready). The TNETA1585 sets bit 31 to indicate that the contents of the register are valid and ready to
read.
Bits 30–26 (cell count). This field indicates the number of cells (minus one) that are to be sent by the SAR for
this particular channel. A zero entry tells the SAR to send a single cell and an all-ones entry tells the SAR to
send 32 cells.
8
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SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
(next-cell register continued)
Bits 14–4 (channel number). This field contains the channel number that the cell(s) is sent on.
Bit 3 (CLP). This field contains the cell-loss-priority indication that the SAR should insert in the outgoing cell’s
header.
Bits 2–0 (cell type). This field indicates the source of cell(s) to be sent. Several options are available for outgoing
cells, and this field, along with the CLP bit, indicates where the cell should be obtained. If the cell type is an RM
cell, then the SAR must obtain the RM-cell payload from one of the RM-cell-contents FIFOs through the slave
interface. If the cell type is data, then the SAR must obtain data from its own transmit buffers. Details are
provided in Table 2:
Table 2. Next-Cell Register Cell-Type Definition
CLP
CELL TYPE
INDICATION
BIT 2
BIT 1
BIT 0
0
0
0
0
In-rate VC-level RM cell from RM-cell-contents FIFO A
0
0
0
1
In-rate VC-level RM cell from RM-cell-contents FIFO B
0
0
1
0
In-rate data cell
0
0
1
1
Reserved
0
1
0
0
In-rate VP-level RM cell from RM-cell-contents FIFO A
0
1
0
1
In-rate VP-level RM cell from RM-cell-contents FIFO B
0
1
1
0
Reserved
0
1
1
1
Reserved
1
0
0
0
Out-of-rate VC-level RM cell from RM-cell-contents
FIFO C
1
0
0
1
Out-of-rate VC-level RM cell from RM-cell-contents
FIFO D
1
0
1
0
Out-of-rate data cell
1
0
1
1
Reserved
1
1
0
0
Out-of-rate VP-level RM cell from RM-cell-contents
FIFO C
1
1
0
1
Out-of-rate VP-level RM cell from RM-cell-contents
FIFO D
1
1
1
0
Reserved
1
1
1
1
Reserved
If an RM cell is sent, the TNETA1575 reads the payload portion for the cell from the appropriate FIFO, using
12 sequential accesses to the associated control-memory location.
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RM-cell-contents FIFO A
When the TNETA1575 reads the next-cell register and an indication is given that an RM cell should be sent from
the RM-cell-contents FIFO A, the TNETA1575 must make 12 accesses to control-memory location 10001h to
fetch one entire cell payload. The data that is returned by the TNETA1585 is in big-endian format as follows:
Byte 0 (31–24)
Byte 1 (23–16)
Byte 2 (15–8)
Byte 3 (7–0)
The ordering and formatting of data (as it is sequentially read from this register) is:
Word 0 – Bytes 0, 1, 2, 3
Word 1 – Bytes 0, 1, 2, 3
•
•
•
RM-cell-contents FIFO B
When the TNETA1575 reads the next-cell register and an indication is given that an RM cell should be sent from
the RM-cell-contents FIFO B, the TNETA1575 must make 12 accesses to control-memory location 10002h to
fetch one entire cell payload. The data that is returned by the TNETA1585 is in big-endian format as follows:
Byte 0 (31–24)
Byte 1 (23–16)
Byte 2 (15–8)
Byte 3 (7–0)
The ordering and formatting of data (as it is sequentially read from this register) is:
Word 0 – Bytes 0, 1, 2, 3
Word 1 – Bytes 0, 1, 2, 3
•
•
•
RM-cell-contents FIFO C
When the TNETA1575 reads the next-cell register and an indication is given that an RM cell should be sent from
the RM-cell-contents FIFO C, the TNETA1575 must make 12 accesses to control-memory location 10003h to
fetch one entire cell payload. The data that is returned by the TNETA1585 is in big-endian format as follows:
Byte 0 (31–24)
Byte 1 (23–16)
Byte 2 (15–8)
Byte 3 (7–0)
The ordering and formatting of data (as it is sequentially read from this register) is:
Word 0 – Bytes 0, 1, 2, 3
Word 1 – Bytes 0, 1, 2, 3
•
•
•
10
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RM-cell-contents FIFO D
When the TNETA1575 reads the next-cell register and an indication is given that an RM cell should be sent from
the RM-cell contents FIFO D, the TNETA1575 must make 12 accesses to control-memory location 10004h to
fetch one entire cell payload. The data that is returned by the TNETA1585 is in big-endian format as follows:
Byte 0 (31–24)
Byte 1 (23–16)
Byte 2 (15–8)
Byte 3 (7–0)
The ordering and formatting of data (as it is sequentially read from this register) is:
Word 0 – Bytes 0, 1, 2, 3
Word 1 – Bytes 0, 1, 2, 3
•
•
•
coprocessor interface
The coprocessor interface consists of a group of unidirectional serial channels through which real-time
information concerning the transmission and reception of cells by the SAR/switch port is passed between the
TNETA1585 and the SAR/switch port. Reset and interrupt capabilities also are provided by the coprocessor
interface. The unidirectional serial-interface implementation by the TNETA1575 SAR is described below.
Similar requirements apply when interfacing to a different SAR device or a switch port. The coprocessor
interface consists of:
Received cell-indication interface (RCCX)
Transmitted cell-indication interface (TCCX)
Data-availability interface (DAX)
COP full-indication interface (COPFULL)
received-cell-indication interface (RCCX)
A serial-bit interface allows the TNETA1575 to signal to the TNETA1585 that a cell has been received on the
UTOPIA interface on a particular channel. This interface is necessary to avoid duplicating the hardware that
is used to resolve a virtual path identifier (VPI) or virtual channel identifier (VCI) to a channel number. When a
cell is received, the VPI/VCI value from the header is extracted by the TNETA1575 and is used as a key in a
lookup algorithm to resolve its associated channel number. When the lookup is complete, the TNETA1575
passes relevant information to the TNETA1585 by sending a 13-bit frame formatted as follows:
Channel number (12–2)
Good/bad cell indicator (1)
Framing (0)
Bits 12–2 (channel number). These bits indicate on which of the 2K channels the last cell was received.
Bit 1 (good/bad cell indicator). This bit indicates whether or not the last cell passed the lookup test or if it should
be discarded. The bit is encoded as follows:
BIT 1
INDICATION
0
Cell is good (VPI/VCI was found in the lookup)
1
Cell should be discarded
Bit 0 (framing). This bit is set to a 1 to denote the start of a frame.
The frame is transmitted to the TNETA1585 through the RCCX terminal starting with bit 0. When a frame is not
actively being transmitted, the RCCX terminal is driven to a 0.
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SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
transmitted-cell-indication interface (TCCX)
A single-bit interface allows the TNETA1575 to signal to the TNETA1585 that a cell will be transmitted on a
particular channel. This interface can be used to facilitate statistics processing in the TNETA1585 and to aid
in ATM Forum ABR scheduling. When the TNETA1575 determines that it has the data to send a cell, it
simultaneously sends an 18-bit frame to the TNETA1585 that is formatted as follows. The information reflected
by this interface confirms the information reflected in the next-cell register, if the TNETA1575 is transmitting a
TNETA1585 scheduled cell.
CHANNEL
NUMBER
CLP
INDICATOR
CELL TYPE
17–7
6
5–3
SCHEDULING
SOURCE
SEND
ACKNOWLEDGE
FRAMING
1
0
BIT
2
Bits 17–7 (channel number). These bits indicate which one of the 2K channels transmitted the last cell.
Bit 6 (CLP). This field contains the cell-loss-priority indication that was inserted in the outgoing cell’s header.
Bits 5–3 (cell type). This field indicates what type of cell was sent. This field, along with the CLP bit, indicates
the origin of the cell sent. Details are provided in Table 3.
Table 3. TCCX Cell-Type Definition
CLP
CELL TYPE
INDICATION
BIT 2
BIT 1
BIT 0
0
0
0
0
In-rate VC-level RM cell from RM-cell-contents FIFO A
0
0
0
1
In-rate VC-level RM cell from RM-cell-contents FIFO B
0
0
1
0
In-rate data cell
0
0
1
1
Reserved
0
1
0
0
In-rate VP-level RM cell from RM-cell-contents FIFO A
0
1
0
1
In-rate VP-level RM cell from RM-cell-contents FIFO B
0
1
1
0
Reserved
0
1
1
1
Reserved
1
0
0
0
Out-of-rate VC-level RM cell from RM-cell-contents
FIFO C
1
0
0
1
Out-of-rate VC-level RM cell from RM-cell-contents
FIFO D
1
0
1
0
Out-of-rate data cell
1
0
1
1
Reserved
1
1
0
0
Out-of-rate VP-level RM cell from RM-cell-contents
FIFO C
1
1
0
1
Out-of-rate VP-level RM cell from RM-cell-contents
FIFO D
1
1
1
0
Reserved
1
1
1
1
Reserved
Bit 2 (scheduling source). This bit indicates whether the cell was scheduled directly from the TNETA1575
scheduler table or if it was scheduled by the TNETA1585. This bit is encoded as follows:
BIT 2
12
INDICATION
0
Scheduler-table scheduled cell
1
TNETA1585 scheduled cell
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transmitted-cell-indication interface (TCCX) (continued)
Bit 1 (send acknowledge). This bit indicates whether the SAR will send a cell. The bit is encoded as follows:
BIT 1
INDICATION
0
Cell will not be sent.
1
Cell will be sent.
Bit 0 (framing). This bit is set to a 1 to denote the start of a frame.
The frame is transmitted to the coprocessor through the TCCX terminal starting with bit 0. When a frame is not
actively being transmitted, the TCCX terminal is driven to a 0.
data-availability interface (DAX)
A single-bit interface allows the TNETA1575 to signal to the TNETA1585 when data is available or unavailable
on a particular channel. A 13-bit frame is sent to the TNETA1585 for a particular channel only when its
data-availability status changes (i.e., when the host writes to the transmit-queue register to notify the
TNETA1575 that a packet has been queued, or if the TNETA1575 completes segmentation of the last packet
on a particular channel). The frame is formatted as follows:
Channel number (12–2)
Data available/unavailable (1)
Framing (0)
Bits 12–2 (channel number). These bits indicate which one of the 2K channels has available or unavailable data.
Bit 1 (data available/unavailable). This field indicates the new status of the segmentation queue for the given
channel number. This field is encoded as follows:
BIT 1
INDICATION
0
All data has been segmented (data unavailable).
1
New data has been added (data available).
Bit 0 (framing). This bit is set to a 1 to denote the start of a frame.
The frame is transmitted to the TNETA1585 through the DAX terminal starting with bit 0. When a frame is not
actively being transmitted, the DAX terminal is driven to a 0.
COP full-indication interface (COPFULL)
A single-bit interface allows the TNETA1585 to signal to the TNETA1575 the status of the TNETA1585’s
receive-UTOPIA-interface FIFO. When in ATM mode (CONFIG = 0), this output goes high when the
receive-UTOPIA-interface FIFO is full. When in PHY mode (CONFIG = 1), this output goes high when the FIFO
is within four bytes of being full.
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TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
TNETA1585-to-TNETA1575 interconnection
Figure 1 shows the interconnection of the TNETA1575 SAR and the TNETA1585 traffic management scheduler.
PMAD15
PMOE
CMAD(15–0)
PMWE
SRAM
64K × 32 or
32K × 32
PMAD(15––0)
SRAM
64K × 32 or
32K × 32
PMDA(31––0)
Parameter Memory
SELLO
Control Memory
SCAD(5–0)
SCOE
SCWE
SCSEL
RESET
INTR
TCCX
RCCX
DAX
COPFULL
TNETA1575
SAR
RXDATA(7–0)
RXSOC
8
ATM CLK
TX UTOPIA
AD
TNETA1585
Traffic Management
Scheduler
RXCLAV
RXCLK
RXEN
CTRL
Local Bus
PCI Bus
SCDATA(31–0)
Figure 1. TNETA1585 Interconnection to TNETA1575
receive-UTOPIA interface
The TNETA1585 receives ATM cells through a receive-UTOPIA level-1 interface with cell-level handshake only.
This interface is configurable as either an 8-bit PHY or ATM interface. The ATM mode is chosen when the
TNETA1585 interfaces with a framer (such as the TNETA1500). The PHY mode is chosen when the
TNETA1585 interfaces with a switch port. The operation of this dual PHY/ATM interface requires connection
of the UTOPIA signals to the appropriate input terminals of the TNETA1585.
In both modes, the receive UTOPIA interface on the TNETA1585 monitors only, i.e., the device does not actively
participate in the UTOPIA protocol. If the system is to work correctly, a fully compliant UTOPIA-peer device is
required. This interface is designed so that the TNETA1585 could be connected as a peer to the TNETA1575,
which are both then connected to an ATM (e.g., switch port) or PHY device.
14
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receive-UTOPIA interface (continued)
In ATM mode, the TNETA1585 receive-UTOPIA interface behaves as an RX UTOPIA, monitoring incoming cells
from a framer such as the TNETA1500 into the reassembly interface of a SAR device such as the TNETA1575.
An external clock input provides for data transfers/synchronization between the TNETA1585 receive-UTOPIA
and TNETA1500 interfaces.
In PHY mode, the TNETA1585 receive-UTOPIA interface behaves as a TX UTOPIA of a PHY device, monitoring
incoming cells from a switching element into the reassembly interface of a SAR device such as the TNETA1575.
An external clock input provides for data transfers/synchronization between the TNETA1585 receive-UTOPIA
and ATM switching-element TX UTOPIA interfaces.
The receive-UTOPIA interface operates as a synchronous 8-bit (byte-wide) data path. The interface functions
with cell-level handshaking. The maximum clock speed supported by this interface is 33 MHz.
receive-UTOPIA interface in PHY mode
The receive-UTOPIA interface on the TNETA1585 operates as the TX UTOPIA interface in a PHY device when
the TNETA1585 is operating in PHY mode.
This cell interface works on the low-to-high transition of RXCLK to sample and generate signals.
TNETA1585
SIGNAL NAME
UTOPIA
SIGNAL NAME
RXCLK
TXCLK
RXDATA7–RXDATA0
TXDATA7–TXDATA0
RXSOC
TXSOC
RXEN
TXEnb
RXCLAV
TXClav
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SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
connecting the TNETA1585 to the UTOPIA bus in PHY mode (see Figure 2)
TNETA1575
PHY mode
ATMCLK1 (82)
ATMCLK2 (64)
RESCLK (66)
TXClk
TXData
RESDATA7–RESDATA0 (72–75, 77–80)
TXSoc
RESSOC (70)
TXEnb
Switch Port
or Other
PHY Layer
Devices
RESEN (67)
TXFull/TXClav
TXPrty
RESCLAV (69)
RESPAR (71)
RESPERR (81)
RXClk
SEGCLK (95)
RXData
SEGDATA7–SEGDATA0 (84–87, 89–92)
RXSoc
RXEnb
RXClav
RXPrty
SEGSOC (97)
SEGEN (96)
SEGCLAV (98)
SEGPAR (94)
PHY/ATM (83)
UTOPIA
Bus
VCC
CLOCK (26)
TNETA1585†
PHY mode
RXCLK (24)
TXData7–TXData0
RXDATA7–RXDATA0 (10, 12–13, 15–18, 20)
TXSoc
RXSOC (21)
TXClav
TXEnb
RXCLAV (22)
RXEN (23)
CONFIG (9)
GND
† Terminal numbers are for the
PCM package.
Figure 2. UTOPIA Bus Connections In PHY Mode
16
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TNETA1585
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SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
receive-UTOPIA interface in ATM mode
The receive-UTOPIA interface on the TNETA1585 functions as the RX UTOPIA interface in an ATM device
when the TNETA1585 is operating in ATM mode.
This receive-cell interface works on the low-to-high transition of RXCLK to sample and generate signals.
TNETA1585
SIGNAL NAME
UTOPIA
SIGNAL NAME
RXCLK
RXCLK
RXDATA7–RXDATA0
RXDATA7–RXDATA0
RXSOC
RXSOC
RXCLAV
RXClav
RXEN
RXEnb
connecting the TNETA1585 to the UTOPIA bus in ATM mode (see Figure 3)
TNETA1575
ATM mode
TNETA1500
(120) RCKI
(92–95, 98–101) RD7–RD0
(117) RXCELL
(118) RXFE
(119) RRE
(65) TCKI
(68–71, 74–77) TD7–TD0
(63) TXCELL
(61) TXAF
(64) TWE
ATMCLK1 (82)
ATMCLK2 (64)
RESCLK (66)
RXClk
RXData
RESDATA7–RESDATA0 (72–75, 77–80)
RESSOC (70)
RESEN (67)
RESCLAV (69)
RESPAR (71)
RESPERR (81)
SEGCLK (95)
SEGDATA7–SEGDATA0 (84–87, 89–92)
SEGSOC (97)
SEGEN (96)
SEGCLAV (98)
SEGPAR (94)
RXSoc
RXClav
RXEnb
TXClk
TXData
TXSoc
TXClav
TXEnb
PHY/ATM (83)
UTOPIA
Bus
GND
CLOCK (26)
TNETA1585†
ATM mode
RXCLK (24)
RXData7–RXData0
RXDATA7–RXDATA0 (10, 12–13, 15–18, 20)
RXSOC (21)
RXSoc
RXClav
RXCLAV (22)
RXEN (23)
CONFIG (9)
† Terminal numbers are for the
PCM package.
GND
Figure 3. UTOPIA Bus Connections in ATM Mode
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TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
parameter-memory interface
The parameter-memory interface on the TNETA1585 is used for interface to the external SRAM containing the
connection-state information and parameters required per channel. The interface consists of a 32-bit data bus,
a 16-bit address bus, an output-enable terminal, and a write-enable terminal. The interface also provides an
additional address terminal (PMAD15) that can be used with address terminal (PMAD15) to provide support
for SRAM bank switching. This allows the user to use two 32K × 32 banks of SRAM instead of one 64K × 32
bank by using PMAD15 and PMAD15 as chip selects. The TNETA1585 is designed to operate with a 15 ns or
faster asynchronous SRAM. The total SRAM requirement for parameter memory to support 2K connections
is 32K × 32.
The parameter-memory information is accessed by the host via the slave interface. Details of the parameters
in parameter memory are found in the TNETA1585 Programmer’s Reference Guide, literature number
SDNU016.
JTAG interface
The TNETA1585 supports boundary scan through a five-wire JTAG interface in accordance with IEEE Std
1149.1-1990 (includes IEEE Std 1149.1a-1993) IEEE Standard Test-Access Port and Boundary-Scan
Architecture.
The maximum operating frequency is 10 MHz for the JTAG interface.
JTAG instruction set
The TNETA1585 supports the following instructions:
INSTRUCTION
OP CODE (BINARY FORMAT)
EXTEST
000
IDCODE
100
SAMPLE/PRELOAD
001
BYPASS
111
INTERNAL SCAN
010
HIGH Z
101
idcode
18
VARIANT
PART NUMBER
MANUFACTURER
LSB
Bit number
31–28
Binary code
0000
27–12
11–1
0
TBD
00000010111
1
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SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4 V
Supply voltage range, VCC(5V) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Input voltage range, standard TTL, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input voltage range, 5-V tolerant TTL, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC(5V) + 0.5 V
Output voltage range, standard TTL, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, 5-V tolerant TTL, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to VCC + 0.5 V
Input clamp current, TTL, IIK (VI < 0 or VI > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the GND terminals.
2. Applies for external input and bidirectional buffers without hysteresis. VI > VCC does not apply to fail-safe terminals. Use V > VCC(5V)
for 5-V tolerant terminals.
3. Applies for external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals. Use VO > VCC(5V) for 5-V tolerant
terminals.
recommended operating conditions
MIN
NOM
MAX
VCC
VCC(5V)
Supply voltage
Commercial
3
3.3
3.6
V
Supply voltage, 5-V tolerant TTL
Commercial
4.5
5
5.5
V
VI
Input voltage
VO
Output voltage
VIH
High level input voltage
High-level
VIL
Low level input voltage
Low-level
TTL
0
5-V tolerant TTL
0
TTL
0
5-V tolerant TTL‡
0
TTL
2
5-V tolerant TTL
2
TTL
0
VCC(5V)
0.8
5-V tolerant TTL
0
0.8
0
70
TA
Operating free-air temperature
‡ VCC must be applied to drive the output to a high-impedance state (Z) for 5-V tolerant operation.
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VCC
VCC(5V)
VCC
VCC
VCC
UNIT
V
V
V
V
°C
19
TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
06
VCC – 0.6
5 V tolerant TTL
5-V
IOH = 8 mA
IOH = 4 mA
VCC – 0.6
06
TTL
IOL = 8 mA
IOL = 4 mA
0.4
5 V tolerant TTL
5-V
IOL = 8 mA
IOL = 4 mA
0.4
Low level output voltage
Low-level
High level input current
High-level
IIL
input
Low-level in
ut current
IOZ
High-impedance-state
High-im
edance-state out
output
ut current
MAX
TTL
High level output voltage
High-level
IIH
MIN
IOH = 8 mA
IOH = 4 mA
TTL
5-V tolerant TTL
TTL
5-V tolerant TTL
UNIT
V
0.4
V
0.4
VI = VIH (max),
VI = VIH (min)
See Note 4
VI = VIL (min),
See Note 5
±1
–760
±1
±1
TTL
±20
5-V tolerant TTL
±20
µA
µA
µA
NOTES: 4. These specifications apply only when the pulldown terminator is turned off.
5. These specifications apply only when the pullup terminator is turned off.
recommended power-supply sequencing for mixed-voltage devices
The recommended power-supply sequencing in a mixed-voltage system is as follows:
•
•
When the power supply is being turned on, all 3.3-V and 5-V supplies should start ramping from 0 V and
reach 95 percent of their end-point values within a 25-ms time window. All bus contention between the
TNETA1585 and external devices is eliminated by the end of the 25-ms time window. The preferred
order of supply ramping is to ramp the 3.3-V supply followed by the 5-V supply. This order is not
mandatory, but it allows a larger cumulative number of power-supply on events than the reverse order.
When the power supply is being turned off, all 3.3-V and 5-V supplies should start ramping from steady
state values and reach 5 percent of these values within a 25-ms time window. All bus contention
between the TNETA1585 and external devices is eliminated by the end of the 25-ms time window. The
preferred order of supply ramping is to ramp down the 5-V supply followed by the 3.3-V supply. This
order is not mandatory, but it allows a larger cumulative number of power-supply off events than the
reverse order.
If these precautions and guidelines are not followed, the TNETA1585 device may experience failures.
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
operating characteristics over recommended operating conditions (see Figure 4)
parameter-memory interface – write operation
NO.
MIN
MAX
1
td(PMAD)
Delay time, from CLOCK↑ to PMAD15–PMAD0 valid
PARAMETER
5
12
UNIT
ns
2
td(PMDATA)
Delay time, from CLOCK↑ to PMDATA31–PMDATA0 valid
5
12
ns
3
td(PMOE)
Delay time, from CLOCK↑ to PMOE↑
5
13
ns
4
td(PMWE)1
Delay time, from CLOCK↓ to PMWE↓
7
15
ns
5
td(PMWE)2
Delay time, from CLOCK↓ to PMWE↑
7
15
ns
CLOCK
(input)
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎ
Î
1
PMAD15–
PMAD0
(output)
Valid
2
PMDATA31–
PMDATA0
(output)
Z
Z
Valid
3
PMOE
(output)
4
5
PMWE
(output)
Figure 4. Parameter-Memory Interface – Write Operation
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
operating characteristics over recommended operating conditions (see Figure 5)
parameter-memory interface (write operation)
data bus enable and disable times
NO.
MIN
MAX
1
ten(CH-PE)
Enable time, from CLOCK↑ to PMDATA31–PMDATA0 enabled
PARAMETER
8
20
ns
1
tdis(CH-PZ)
Disable time, from CLOCK↑ to PMDATA31–PMDATA0 disabled (Z state)
3
9
ns
CLOCK
(input)
PMAD15–
PMAD0
(output)
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
1
PMDATA31–
PMDATA0
(output)
Z
2
Valid
Z
PMOE
(output)
PMWE
(output)
Figure 5. Parameter-Memory Interface (Write Operation) – Data Bus Enable and Disable Times
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
timing requirements (see Figure 6)
parameter-memory interface – read operation
NO.
MIN
MAX
UNIT
1
tsu(PMDATA)
Setup time, PMDATA31–PMDATA0 valid before CLOCK↑
3
ns
2
th(PMDATA)
Hold time, PMDATA31–PMDATA0 valid after CLOCK↑
2
ns
operating characteristics over recommended operating conditions (see Figure 6)
parameter-memory interface – read operation
NO.
PARAMETER
MIN
MAX
UNIT
3
td(PMAD)
Delay time, from CLOCK↑ to PMAD15–PMAD0 valid
5
12
ns
4
td(PMOE)
Delay time, from CLOCK↑ to PMOE↓
5
13
ns
CLOCK
(input)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
PMDATA31–
PMDATA0
(input)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
2
1
Valid
3
PMAD15–
PMAD0
(output)
Valid
4
PMOE
(output)
PMWE
(output)
H
Figure 6. Parameter-Memory Interface – Read Operation
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
timing requirements (see Figure 7)
receive-UTOPIA interface
NO.
MIN
MAX
UNIT
1
tsu(RXCLAV)
Setup time, RXCLAV low before RXCLK↑
10
ns
2
tsu(RXSOC)
Setup time, RXSOC high before RXCLK↑
10
ns
3†
tsu(RXDATA)
Setup time, RXDATA7–RXDATA0 valid before RXCLK↑
11
ns
4‡
th(RXCLAV)
Hold time, RXCLAV low after RXCLK↑
2
ns
5
th(RXSOC)
Hold time, RXSOC high after RXCLK↑
1
ns
6
th(RXDATA)
Hold time, RXDATA7–RXDATA0 valid after RXCLK↑
1
ns
† This 11-ns minimum setup time deviates from the 10-ns minimum setup time specified in the UTOPIA level-1 revision1-2.01 specification.
‡ This 2-ns minimum hold time deviates from the 1-ns minimum hold time specified in the UTOPIA level-1 revision1-2.01 specification.
RXCLK
(input)
5
2
RXSOC
(input)
RXDATA7 –
RXDATA0
(input)
Byte 53
ÎÎÎÎÎ
ÎÎÎÎÎ
6
3
Byte 1
Byte 2
Byte 3
4
RXCLAV
(input)
1
Figure 7. Receive-UTOPIA Interface
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Byte 4
Byte 5
TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
timing requirements (see Figure 8)
slave interface – read operation
NO.
MIN
MAX
UNIT
1
tsu(SCAD)
Setup time, SCAD5–SCAD0 valid before CLOCK↑
17
ns
2†
tsu(SCSEL)
Setup time, SCSEL low before CLOCK↑
13
ns
3
tsu(SCWE)
Setup time, SCWE high before CLOCK↑
6
ns
4†
tsu(SCOE)
Setup time, SCOE low before CLOCK↑
13
ns
5
th(SCAD)
Hold time, SCAD5–SCAD0 valid after CLOCK↑
1
ns
6‡
th(SCSEL)
Hold time, SCSEL low after CLOCK↑
3
ns
7
th(SCWE)
Hold time, SCWE high after CLOCK↑
1
ns
2
ns
8‡
th(SCOE)
Hold time, SCOE low after CLOCK↑
† These measurements are taken with the data enabled 4 ns before the rising edge of the clock.
‡ These measurements are taken with the data disabled at the time of the rising edge of the clock.
operating characteristics over recommended operating conditions (see Figure 8)
slave interface – read operation
NO.
MIN
MAX
9
td(SCDATA)1
Delay time, from SCAD5–SCAD0 to SCDATA31–SCDATA0 valid
PARAMETER
5
13
UNIT
ns
10
td(SCDATA)2
Delay time, from SCSEL↓ to SCDATA31–SCDATA0 enabled
3
10
ns
11
td(SCDATA)3
Delay time, from SCOE↓ to SCDATA31–SCDATA0 enabled
4
11
ns
12
td(SCDATA)4
Delay time, from SCSEL↑ to SCDATA31–SCDATA0 disabled
4
9
ns
13
td(SCDATA)5
Delay time, from SCOE↑ to SCDATA31–SCDATA0 disabled
4
9
ns
CLOCK
(input)
SCAD5–
SCAD0
(input)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎ
ÎÎ
1
Valid
9
SCDATA31–
SCDATA0
(output)
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
5
Z
Z
Valid
11
8
13
4
SCOE
(input)
6
10
12
2
SCSEL
(input)
7
3
SCWE
(input)
Figure 8. Slave Interface – Read Operation
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
timing requirements (see Figure 9)
slave interface – write operation
NO.
MIN
MAX
UNIT
1
tsu(SCAD)
Setup time, SCAD5–SCAD0 valid before CLOCK↑
7
ns
2
tsu(SCDATA)
Setup time, SCDATA31–SCDATA0 valid before CLOCK↓
0
ns
3
tsu(SCWE)
Setup time, SCWE low before CLOCK↑
5
ns
4
tsu(SCSEL)
Setup time, SCSEL low before CLOCK↑
5
ns
5
tsu(SCOE)
Setup time, SCOE high before CLOCK↓
5
ns
6
th(SCAD)
Hold time, SCAD5–SCAD0 valid after CLOCK↑
0
ns
7
th(SCDATA)
Hold time, SCDATA31–SCDATA0 valid after CLOCK↓
7
ns
8
th(SCWE)
Hold time, SCWE low after CLOCK↑
4
ns
9
th(SCSEL)
Hold time, SCSEL low after CLOCK↑
0
ns
10
th(SCOE)
Hold time, SCOE high after CLOCK↓
2
ns
CLOCK
(input)
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
1
SCAD5–
SCAD0
(input)
6
Valid
7
2
SCDATA31–
SCDATA0
(input)
3
Valid
8
SCWE
(input)
4
9
SCSEL
(input)
5
10
SCOE
(input)
Figure 9. Slave Interface – Write Operation
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
timing requirements (see Figure 10)
coprocessor interface (TCCX)
NO.
MIN
1
tsu(TCCX)
Setup time, TCCX high before CLOCK↑
2
th(TCCX)
Hold time, TCCX valid after CLOCK↑
MAX
UNIT
10
ns
1
ns
CLOCK
(input)
1
TCCX
(input)
2
Send
ACK
Frame
Scheduler
Source
Cell Type (3 bits)
CLP
DMA Number
(11 Bits)
Figure 10. TCCX Interface
timing requirements (see Figure 11)
coprocessor interface (RCCX)
NO.
MIN
1
tsu(RCCX)
Setup time, RCCX high before CLOCK↑
2
th(RCCX)
Hold time, RCCX valid after CLOCK↑
MAX
UNIT
10
ns
1
ns
CLOCK
(input)
1
RCCX
(input)
2
DMA Number (11 bits)
GCI
Frame
Figure 11. RCCX Interface
timing requirements (see Figure 12)
coprocessor interface (DAX)
NO.
MIN
1
tsu(DAX)
Setup time, DAX high before CLOCK↑
2
th(DAX)
Hold time, DAX valid after CLOCK↑
MAX
UNIT
10
ns
1
ns
CLOCK
(input)
1
DAX
(input)
Frame
2
DMA Number (11 bits)
DAV
Figure 12. DAX Interface
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
operating characteristics (see Note 6 and Figure 13)
coprocessor interface
NO.
1
PARAMETER
td(COPFULL)
Delay time, from CLOCK↑ to COPFULL↑
MIN
MAX
5
15
UNIT
ns
NOTE 6: The COPFULL signal is asserted high after the last byte of the seventh cell in the UTOPIA FIFO is received by the TNETA1585, or if
a new RXSOC is received by the TNETA1585 for the cell that fills the FIFO. It remains high until a cell location is available in the FIFO.
CLOCK
(input)
...
1
COPFULL
(output)
Figure 13. COPFULL Timing
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
MECHANICAL DATA
PGF (S-PQFP-G176)
PLASTIC QUAD FLATPACK
132
89
88
133
0,27
0,17
0,08 M
0,50
0,13 NOM
176
45
1
44
Gage Plane
21,50 SQ
24,20
SQ
23,80
26,20
SQ
25,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040134 / B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
MECHANICAL DATA
PCM (S-PQFP-G***)
PLASTIC QUAD FLATPACK
(The TNETA1585 uses a 160-pin PCM package. See Note D).
144 PIN SHOWN
108
73
109
NO. OF
PINS***
A
144
22,75 TYP
160
25,35 TYP
72
0,38
0,22
0,13 M
0,65
144
37
0,16 NOM
1
36
A
28,20 SQ
27,80
31,45
SQ
30,95
3,60
3,20
Gage Plane
0,25
0,25 MIN
1,03
0,73
Seating Plane
4,10 MAX
0,10
4040024 / B 10/94
NOTES: A.
B.
C.
D.
30
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-022
The 144 PCM is identical to the 160 PCM except that four leads per corner are removed.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
TNETA1585PCM
TNETA1585PGF
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
Package
Type
Package
Drawing
OBSOLETE
QFP
PCM
160
TBD
Call TI
Call TI
OBSOLETE
LQFP
PGF
176
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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