TSC2003-Q1 www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008 I2C TOUCH SCREEN CONTROLLER FEATURES APPLICATIONS • • • • • • • • • • • • • 1 2 • • Qualified for Automotive Applications 2.5-V To 5.25-V Operation Internal 2.5-V Reference Direct Battery Measurement (0.5 V To 6 V) On-Chip Temperature Measurement Touch-Pressure Measurement I2C Interface Supports: Standard, Fast, And High-Speed Modes Auto Power Down TSSOP-16 Package Personal Digital Assistants Portable Instruments Point-of-Sale Terminals Pagers Touch Screen Monitors Cellular Phones DESCRIPTION The TSC2003 is a 4-wire resistive touch screen controller. It also features direct measurement of two batteries, two auxiliary analog inputs, temperature measurement, and touch-pressure measurement. The TSC2003 has an on-chip 2.5-V reference that can be utilized for the auxiliary inputs, battery monitors, and temperature-measurement modes. The reference can also be powered down when not used to conserve power. The internal reference operates down to 2.7-V supply voltage while monitoring the battery voltage from 0.5 V to 6 V. The TSC2003 is available in the small TSSOP-16 package and is specified over the –40°C to 85°C temperature range. VDD PENIRQ TEMP0 TEMP1 X+ X– SCL VDD SAR 2 Y+ Y– IC Interface and Control Logic Comparator MUX IN1 IN2 VBAT1 CDAC Channel Select SDA A0 Internal Clock A1 VBAT2 VREF Internal 2.5-V REF 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated TSC2003-Q1 SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 85°C (1) (2) TSSOP – PW ORDERABLE PART NUMBER Reel of 2000 TSC2003IPWRQ1 TOP-SIDE MARKING T2003Q1 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. PW PACKAGE (TOP VIEW) VDD 1 16 IN1 X+ 2 15 IN2 Y+ 3 14 A0 X– 4 13 A1 Y– 5 12 SCL GND 6 11 SDA VBAT1 7 10 PENIRQ VBAT2 8 9 VREF TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION VDD 1 X+ 2 I X+ position Y+ 3 I Y+ position X– 4 I X– position Y– 5 I Y– position GND 6 VBAT1 7 I Battery monitor 1 VBAT2 8 I Battery monitor 1 VREF 9 I/O Voltage reference PENIRQ 10 O Pen interrupt. Open-drain, requires 30-kΩ to 100-kΩ external pullup resistor. SDA 11 I/O Serial data SCL 12 I Serial clock A1 13 I I2C bus address A1 A0 14 I I2C bus address A0 IN2 15 I Auxiliary analog-to-digital converter input 2 IN1 16 I Auxiliary analog-to-digital converter input 1 2 Power supply Ground Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 TSC2003-Q1 www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008 ABSOLUTE MAXIMUM RATINGS (1) (2) over operating free-air temperature range (unless otherwise noted) VDD Supply voltage range –0.3 V to 6 V Digital inputs –0.3 V to VDD + 0.3 V All analog inputs except pins 7 and 8 –0.3 V to VDD + 0.3 V VI Input voltage range PD Power dissipation θJA Package thermal impedance, junction to free air TA Operating free-air temperature range TJ Maximum junction temperature Tstg Storage temperature range Analog input pins 7 and 8 (1) (2) –0.3 V to 6 V (TJ(max) – TA)/θJA 115.2°C –40°C to 85°C 150°C –65°C to 150°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are referenced to GND. ELECTRICAL CHARACTERISTICS TA = –40°C to 85°C, VDD = 2.7 V, VREF = 2.5-V external voltage, I2C bus frequency = 3.4 MHz, 12-bit mode, digital inputs = GND or VDD (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VREF V Analog Input VI Full-scale input voltage span 0 VI Absolute input voltage Ci Capacitance 25 pF Ileak Leakage current 0.1 µA 12 bits –0.2 VDD + 0.2 V System Performance Resolution No missing codes Integral linearity error Standard and fast modes 11 High-speed mode 10 bits Standard and fast modes ±2 High-speed mode ±4 Offset error Gain error Vn Noise PSRR Power-supply rejection ratio Including internal VREF, RMS LSB (1) ±6 LSB ±4 LSB 70 µV 70 dB Sampling Dynamics Throughput rate 50 ksps 100 dB Y+, X+ on-resistance 5.5 Ω Y–, X– on-resistance 7.3 Channel-to-channel isolation VIN = 2.5 Vpp at 50 kHz Switch Drivers Drive current (2) (1) (2) Duration 100 ms Ω 50 mA LSB = least significant bit. With VREF equal to 2.5 V, one LSB is 610 µV. Specified by design. Exceeding 50-mA source current may result in device degradation. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 3 TSC2003-Q1 SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to 85°C, VDD = 2.7 V, VREF = 2.5-V external voltage, I2C bus frequency = 3.4 MHz, 12-bit mode, digital inputs = GND or VDD (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 2.45 2.50 2.55 UNIT Reference Output Internal reference voltage Internal reference drift ZO Output impedance IQ Quiescent current V ppm/ °C 25 Ω Internal reference on 300 Internal reference off 1 GΩ 750 µA PD1 = 1, PD0 = 0, SDA and SCL high Reference Input VI Input voltage RI Resistance 2 PD1 = PD0 = 0 VDD 1 V GΩ Battery Monitor VI ZI Input voltage Input impedance Accuracy 0.5 Sampling battery 6 10 Battery monitor off V kΩ 1 GΩ External VREF = 2.5 V –2 +2 Internal reference –3 +3 % Temperature Measurement Temperature range Resolution Accuracy –40 85 Differential method (3) 1.6 TEMP0 (4) 0.3 Differential method (3) ±2 TEMP0 (4) ±3 °C °C °C Digital Input/Output VIH High-level input voltage, all except PENIRQ (5) | IIH | ≤ 5 µA 0.7 × VDD VDD + 0.3 V VIL Low-level input voltage, all except | IIL | ≤ 5 µA PENIRQ (5) –0.3 0.3 × VDD V VOH High-level output voltage, all except PENIRQ IOH = –250 µA VOL Low-level output voltage, all except PENIRQ IOL = 250 µA 0.4 V VOL Low-level output voltage, PENIRQ 30-kΩ pullup 0.4 V Ci Input capacitance SDA, SCL 10 pF (3) (4) (5) 4 0.8 × VDD V Difference between TEMP0 and TEMP1 measurement. No calibration necessary. Temperature drift is –2.1 mV/°C Specified by design Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 TSC2003-Q1 www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008 ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to 85°C, VDD = 2.7 V, VREF = 2.5-V external voltage, I2C bus frequency = 3.4 MHz, 12-bit mode, digital inputs = GND or VDD (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power Supply Requirements VDD Supply voltage IQ Quiescent current Specified performance 2.7 3.6 Operating range 2.5 5.25 Internal reference off, PD1 = PD0 = 0 High-speed mode (SCL = 3.4 MHz) 254 Fast mode (SCL = 400 kHz) 95 Standard mode (SCL = 100 kHz) 63 Internal reference on, PD0 = 0 Power-down current when part is not addressed IPD Internal reference off, PD1 = PD0 = 0 Power dissipation µA 1005 High-speed mode (SCL = 3.4 MHz) 90 Fast mode (SCL = 400 kHz) 21 Standard mode (SCL = 100 kHz) 4 PD1 = PD0 = 0, SDA = SCL = VDD PD 650 µA 3 VDD = 2.7 V 1.8 mW 85 °C Temperature Range TA Operating free-air temperature Specified performance –40 TIMING CHARACTERISTICS (1) (2) TA = –40°C to 85°C, VDD = 2.7 V (unless otherwise noted) (see Figure 1) PARAMETER fSCL TEST CONDITIONS SCL clock frequency Bus free time between Stop and Start conditions tBUF MIN MAX Standard mode 0 100 Fast mode 0 400 High-speed mode, Cb = 100 pF max 0 3.4 High-speed mode, Cb = 400 pF max 0 1.7 Standard mode 4.7 Fast mode 1.3 Standard mode tHD; STA tlow Hold time (repeated) Start condition Low period of the SCL clock 4 Fast mode 600 High-speed mode 160 Standard mode 4.7 Fast mode 1.3 High-speed mode, Cb = 100 pF max 160 High-speed mode, Cb = 400 pF max 320 Standard mode thigh (1) (2) Fast mode High period of the SCL clock tSU; STA 4 Setup time for a repeated Start condition UNIT kHz MHz µs µs ns µs ns µs 600 High-speed mode, Cb = 100 pF max 60 High-speed mode, Cb = 400 pF max 120 Standard mode 4.7 Fast mode 600 High-speed mode 160 ns µs ns All values referred to VIHMIN and VILMAX levels. Not production tested Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 5 TSC2003-Q1 SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com TIMING CHARACTERISTICS (continued) TA = –40°C to 85°C, VDD = 2.7 V (unless otherwise noted) (see Figure 1) PARAMETER tSU; DAT TEST CONDITIONS Data setup time MIN Standard mode 250 Fast mode 100 High-speed mode tHD; DAT Data hold time 10 0 3.45 Fast mode 0 0.9 High-speed mode, Cb = 100 pF max 0 70 High-speed mode, Cb = 400 pF max 0 150 20 + 0.1Cb 300 High-speed mode, Cb = 100 pF max 10 80 High-speed mode, Cb = 400 pF max 20 Standard mode trCL1 Rise time of SCL signal after a repeated Start condition and after an acknowledge bit Fast mode 20 + 0.1Cb 300 10 80 High-speed mode, Cb = 400 pF max 20 160 300 High-speed mode, Cb = 100 pF max 10 80 High-speed mode, Cb = 400 pF max 20 20 + 0.1Cb 300 10 80 High-speed mode, Cb = 400 pF max 20 160 20 + 0.1Cb 300 High-speed mode, Cb = 100 pF max 10 80 High-speed mode, Cb = 400 pF max 20 160 Standard mode tSU; STO Cb Setup time for Stop condition Capacitive load for SDA or SCL Fast mode 600 High-speed mode 160 Pulse width of spike suppressed VnH Noise margin at the high level for each connected device (including hysteresis) ns µs 4 ns Standard mode 400 Fast mode 400 High-speed mode, SCL = 1.7 MHz 400 High-speed mode, SCL = 3..4 MHz tSP ns 300 Fast mode Fall time of SDA signal 160 High-speed mode, Cb = 100 pF max Standard mode tfDA ns 1000 Fast mode Rise time of SDA signal ns 300 20 + 0.1Cb Standard mode trDA ns 160 High-speed mode, Cb = 100 pF max Fast mode Fall time of SCL signal ns 1000 Standard mode tfCL µs 1000 Fast mode Rise time of SCL signal UNIT ns Standard mode Standard mode trCL MAX pF 100 Fast mode 0 50 High-speed mode 0 10 ns Standard mode Fast mode 0.2 × VDD V 0.1 × VDD V High-speed mode Standard mode VnL Noise margin at the low level for each connected device (including hysteresis) Fast mode High-speed mode 6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 TSC2003-Q1 www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008 trDA tfDA SDA tBUF tLOW trCL tSP tHD; STA tfCL SCL tHD; STA tSU; DAT tHD; DAT tSU; STA tHIGH Stop Start trCL1 tSU; STO Repeated Start Figure 1. Timing Diagram Power-On Sequence Timing During TSC2003 power-up, the I2C bus should be idle. In other words, the SDA and SCL lines must be high before the TSC2003 supply (VDD) ramps up greater than 0.9 V. If the TSC2003 uses the same supply as the I2C bus pullup resistors (VI2C), then a 1-µF capacitor placed very close to the TSC2003 supply pin causes the TSC2003 supply to ramp up more slowly (see Figure 2). If the TSC2003 supply (VDD) is different than the supply to the I2C bus pullup resistors (VI2C), then VI2C should be turned on before the TSC2003 supply (VDD) is powered up. t1 ≥ 0 100% VDD VDD ~ 0.9 V 0V 100% VI2C SCL SDA SCL High 2 I C Bus Activity ~ 0.9 V 0V 100% VI2C ~ 0.9 V 0V SDA Low I2C Bus Activity Figure 2. Power-On Sequence Timing Diagram Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 7 TSC2003-Q1 SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs V DD 300 1200 1100 1000 High-Speed Mode = 3.4MHz Supply Current (µA) Supply Current (µA) 250 200 150 Fast Mode = 400kHz 100 50 0 Ð20 0 20 40 60 80 600 500 400 300 Fast Mode = 400kHz Standard Mode = 100kHz 200 100 0 Standard Mode = 100kHz Ð40 High-Speed Mode = 3.4MHz 900 800 700 100 2.5 3.0 3.5 Temperature ( °C) SUPPLY CURRENT vs I 2C BUS FREQUENCY 4.5 5.0 5.5 SUPPLY CURRENT (Part Not Addressed) vs V DD 1000 300 900 High-Speed Mode = 3.4MHz 800 Supply Current (µA) 250 Supply Current (µA) 4.0 VDD (V) High-Speed Mode 200 150 700 600 500 Fast Mode = 400kHz 400 300 Standard Mode = 100kHz 200 100 100 Fast/Standard Mode 50 10 100 1000 0 2.5 10000 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) I2C Bus Frequency (kHz) CHANGE IN GAIN vs TEMPERATURE SUPPLY CURRENT (Part Not Addressed) vs TEMPERATURE 4.0 100 3.0 Supply Current (µA) 80 Gain Delta from +25ûC (LSB) 90 High-Speed Mode = 3.4MHz 70 60 50 Fast Mode = 400kHz 40 30 20 Standard Mode = 100kHz 10 2.0 1.0 0.0 Ð1.0 Ð2.0 Ð3.0 Ð4.0 0 Ð40 Ð40 Ð20 0 20 40 60 80 100 Ð20 0 20 40 60 80 100 Temperature ( °C) Temperature ( °C) 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 TSC2003-Q1 www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) EXTERNAL REFERENCE CURRENT vs TEMPERATURE CHANGE IN OFFSET vs TEMPERATURE 5.0 10 4.0 9 External Reference Current (µA) Offset Delta from +25°C (LSB) 6.0 3.0 2.0 1.0 0.0 –1.0 –2.0 –3.0 –4.0 –5.0 8 6 5 4 –20 0 20 40 60 80 Fast Mode = 400kHz 3 Standard Mode = 100kHz 2 1 –6.0 –40 High-Speed Mode = 3.4MHz 7 100 0 –40 Temperature ( °C) –20 0 20 60 40 80 100 Temperature ( °C) 9 9 8 8 X– 7 7 6 6 Y– RON (Ω) RON (Ω) SWITCH-ON RESISTANCE vs VDD (X+, Y+: +V DD to Pin; X–, Y– : Pin to GND) 5 4 X+ 3 Y+ SWITCH-ON RESISTANCE vs TEMPERATURE (X+, Y+: +VDD to Pin; X –, Y –: Pin to GND) X– Y– 5 Y+ 4 X+ 3 2 2 1 1 0 0 2.5 3 3.5 4 4.5 5 –40 5.5 –20 0 INTERNAL V REF vs TEMPERATURE 60 80 100 INTERNAL V REF vs V DD 2.55 2.54 2.54 2.53 2.53 2.52 2.52 Internal VREF (V) 2.55 2.51 2.50 2.49 2.48 2.51 2.50 2.49 2.48 2.47 2.47 2.46 2.46 2.45 2.45 –40 –35 –30 –25 –20 –15 –10 –05 0 05 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 Internal VREF (V) 40 20 Temperature ( °C) VDD (V) 2.5 Temperature ( °C) 3 3.5 4 4.5 5 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 5.5 VDD (V) 9 TSC2003-Q1 SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) TEMP0 DIODE VOLTAGE vs VDD (25°C) TEMPERATURE DIODE VOLTAGE vs TEMPERATURE 614 800 TEMP1 TEMP0 Diode Voltage (mV) Temperature Diode Voltage (mV) 850 750 700 650 600 TEMP0 550 500 450 613 612 611 –40 –35 –30 –25 –20 –15 –10 –05 0 05 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 610 2.5 3.0 3.5 Temperature ( °C) 4.0 4.5 5.0 5.5 VDD (V) TEMP1 DIODE VOLTAGE vs V DD (25°C) 738 TEMP1 Diode Voltage (mV) 736 734 732 730 728 726 724 722 720 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 TSC2003-Q1 www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008 DEVICE INFORMATION The TSC2003 is a classic Successive Approximation Register (SAR) analog-to-digital converter (ADC). The architecture is based on capacitive redistribution which inherently includes a sample-and-hold function. The converter is fabricated on a 0.6µ CMOS process. The basic operation of the TSC2003 is shown in Figure 3. The device features an internal 2.5-V reference and an internal clock. Operation is maintained from a single supply of 2.7 V to 5.25 V. The internal reference can be overdriven with an external, low-impedance source between 2 V and VDD. The value of the reference voltage directly sets the input range of the converter. The analog input (X, Y, and Z parallel coordinates, auxiliary inputs, battery voltage, and chip temperature) to the converter is provided via a multiplexer. A unique configuration of low on-resistance switches allows an unselected ADC input channel to provide power and an accompanying pin to provide ground for an external device. By maintaining Figure 3, a differential input to the converter, and a differential reference architecture, it is possible to negate the switch’s on-resistance error (should this be a source of error for the particular measurement). Voltage Regulator +2.7V to +5V 1.2kΩ 1µF + to 10µF (Optional) 50kΩ TSC2003 0.1µF Touch Screen 1 +VDD IN1 16 Auxiliary Input 2 X+ IN2 15 Auxiliary Input 3 Y+ A0 14 4 X– A1 13 5 Y– SCL 12 Serial Clock 6 GND SDA 11 Serial Data 7 VBAT1 PENIRQ 10 8 VBAT2 VREF Pen Interrupt 9 + 0.1µF Main Battery 1.2kΩ 1µF to 10µF (Optional) Secondary Battery Figure 3. Basic Operation of the TSC2003 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 11 TSC2003-Q1 SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com Analog Input See Figure 4 for a block diagram of the input multiplexer on the TSC2003, the differential input of the ADC, and the converter's differential reference. When the converter enters the Hold mode, the voltage difference between the +IN and –IN inputs (see Figure 4) is captured on the internal capacitor array. The input current on the analog inputs depends on the conversion rate of the device. During the sample period, the source must charge the internal sampling capacitor (typically 25 pF). After the capacitor has been fully charged, there is no further input current. The amount of charge transfer from the analog source to the converter is a function of conversion rate. +VDD PENIRQ TEMP1 VREF TEMP0 C2-C0 (Shown 101B) C3 (Shown HIGH) X+ X– Ref ON/OFF Y+ +IN Y– +REF Converter –IN 2.5-V Reference –REF 7.5kΩ VBAT1 7.5kΩ VBAT2 2.5kΩ 2.5kΩ Battery On Battery On IN1 IN2 GND Figure 4. Simplified Diagram of the Analog Input 12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 TSC2003-Q1 www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008 Internal Reference The TSC2003 has an internal 2.5-V voltage reference that can be turned on or off with the power-down control bits, PD0 and PD1 (see Table 2 and Figure 5). The internal reference is powered down when power is first applied to the device. The internal reference voltage is only used in the single-ended reference mode for battery monitoring, temperature measurement, and for measuring the auxiliary input. Optimal touch screen performance is achieved when using a ratiometric conversion; thus, all touch screen measurements are done automatically in the differential mode. Reference Power Down Band Gap VREF Buffer To CDAC Optional Figure 5. Simplified Diagram of the Internal Reference Reference Input The voltage difference between +REF and –REF (see Figure 4) sets the analog input range. The TSC2003 operates with a reference in the range of 2 V to VDD. There are several critical items concerning the reference input and its wide-voltage range. As the reference voltage is reduced, the analog voltage weight of each digital output code is also reduced. This is often referred to as the LSB (least significant bit) size, and is equal to the reference voltage divided by 4096 (256 if in 8-bit mode). Any offset or gain error inherent in the ADC appears to increase, in terms of LSB size, as the reference voltage is reduced. For example, if the offset of a given converter is 2 LSBs with a 2.5-V reference, it is typically 2.5 LSBs with a 2-V reference. In each case, the actual offset of the device is the same, 1.22 mV. With a lower reference voltage, more care must be taken to provide a clean layout including adequate bypassing, a clean (low noise, low ripple) power supply, a low-noise reference (if an external reference is used), and a low-noise input signal. The voltage into the VREF input is not buffered, and directly drives the capacitor digital-to-analog converter (CDAC) portion of the TSC2003. Therefore, the input current is very low, typically < 6 µA. Reference Mode There is a critical item regarding the reference when making measurements while the switch drivers are on. For this discussion, it is useful to consider the basic operation of the TSC2003 (see Figure 3). This particular application shows the device being used to digitize a resistive touch screen. A measurement of the current Y position of the pointing device is made by connecting the X+ input to the ADC, turning on the Y+ and Y– drivers, and digitizing the voltage on X+, as shown in Figure 6. For this measurement, the resistance in the X+ lead does not affect the conversion; it does, however, affect the settling time, but the resistance is usually small enough that this is not a concern. However, because the resistance between Y+ and Y– is fairly low, the on-resistance of the Y drivers does make a small difference. Under the situation outlined so far, it would not be possible to achieve a 0-V input or a full-scale input regardless of where the pointing device is on the touch screen because some voltage is lost across the internal switches. In addition, the internal switch resistance is unlikely to track the resistance of the touch screen, providing an additional source of error. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 13 TSC2003-Q1 SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com VREF +VDD Y+ +REF +IN X+ Converter –IN –REF Y– GND Figure 6. Simplified Diagram of Single-Ended Reference This situation is remedied, as shown in Figure 7, by using the differential mode: the +REF and –REF inputs are connected directly to Y+ and Y–, respectively. This makes the ADC ratiometric. The result of the conversion is always a percentage of the external reference, regardless of how it changes in relation to the on-resistance of the internal switches. +VDD Y+ +REF +IN X+ Converter –IN –REF Y– GND Figure 7. Simplified Diagram of Differential Reference (Y Switches Enabled, X+ is Analog Input) Differential reference mode always uses the supply voltage, through the drivers, as the reference voltage for the ADC. VREF cannot be used as the reference voltage in differential mode. It is possible to use a high-precision reference on VREF in single-ended reference mode for measurements which do not need to be ratiometric (i.e., battery voltage, temperature measurement, etc.). In some cases, it could be possible to power the converter directly from a precision reference. Most references can provide enough power for the TSC2003, but they might not be able to supply enough current for the external load, such as a resistive touch screen. 14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 TSC2003-Q1 www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008 Touch Screen Settling In some applications, external capacitors may be required across the touch screen for filtering noise picked up by the touch screen (i.e., noise generated by the LCD panel or backlight circuitry). These capacitors provide a low-pass filter to reduce the noise, but they also cause a settling time requirement when the panel is touched. The settling time typically shows as a gain error. The problem is that the input and/or reference has not settled to its final steady-state value prior to the ADC sampling the input(s) and providing the digital output. Additionally, the reference voltage may still be changing during the measurement cycle. To resolve these settling time problems, the TSC2003 can be commanded to turn on the drivers only without performing a conversion (see Table 1). Time can then be allowed before the command is issued to perform a conversion. Generally, the time it takes to communicate the conversion command over the I2C bus is adequate for the touch screen to settle. Temperature Measurement In some applications, such as battery recharging, a measurement of ambient temperature is required. The temperature measurement technique used in the TSC2003 relies on the characteristics of a semiconductor junction operating at a fixed current level to provide a measurement of the temperature of the TSC2003 chip. The forward diode voltage (VBE) has a well-defined characteristic versus temperature. The temperature can be predicted in applications by knowing the 25°C value of the VBE voltage and then monitoring the delta of that voltage as the temperature changes. The TSC2003 offers two modes of temperature measurement. The first mode requires calibrations at a known temperature, but only requires a single reading to predict the ambient temperature. A diode is used during this measurement cycle. The voltage across the diode is connected through the MUX for digitizing the diode forward bias voltage by the ADC with an address of C3 = 0, C2 = 0, C1 = 0, and C0 = 0 (see Table 1 and Figure 8 for details). This voltage is typically 600 mV at 25°C, with a 20-µA current through it. The absolute value of this diode voltage can vary a few millivolts; the temperature coefficient (TC) of this voltage is very consistent at –2.1 mV/°C. During the final test of the end product, the diode voltage would be stored at a known room temperature, in memory, for calibration purposes by the user. The result is an equivalent temperature measurement resolution of 0.3°C/LSB. X+ MUX A/D Converter Temperature Select TEMP0 TEMP1 Figure 8. Temperature Measurement Mode Functional Block Diagram The second mode does not require a test temperature calibration, but instead uses a two-measurement method to eliminate the need for absolute temperature calibration and for achieving 2°C/LSB accuracy. This mode requires a second conversion with an address of C3 = 0, C2 = 1, C1 = 0, and C0 = 0, with a 91 times larger current. The voltage difference between the first and second conversion using 91 times the bias current is represented by kT/q × 1n (N), where N is the current ratio (91), k is Boltzmann's constant (1.38054 × 10–23 electron-volts/degree Kelvin), q is the electron charge (1.602189 × 10–19 C), and T is the temperature in degrees Kelvin. This mode can provide improved absolute temperature measurement over the first mode, but at the cost of less resolution (1.6°C/LSB). Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 15 TSC2003-Q1 SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com The equation to solve for °K is shown in Equation 1: °K = q • ∆V k • 1n(N) (1) Where: ΔV V(I91) – V(I1) (in mV) ∴ °K 2.573 × ΔV°K/mV °C = 2.573 × ΔV(mV) – 273°K NOTE: The bias current for each diode temperature measurement is only turned on during the acquisition mode, and, therefore, does not add any noticeable increase in power, especially if the temperature measurement only occurs occasionally. Battery Measurement An added feature of the TSC2003 is the ability to monitor the battery voltage on the other side of the voltage regulator (dc/dc converter), as shown in Figure 9. The battery voltage can vary from 0.5 V to 6 V, while the voltage regulator maintains the voltage to the TSC2003 at 2.7 V, 3.3 V, etc. The input voltage (VBAT1 or VBAT2) is divided down by 4 so that a 6-V battery voltage is represented as 1.5 V to the ADC. The simplifies the multiplexer and control logic. To minimize the power consumption, the divider is only on during the sample period which occurs after control bits C3 = 0, C2 = 0, C1 = 0, and C0 = 1 (VBAT1) or C3 = 0, C2 = 1, C1 = 0, and C0 = 1 (VBAT2) are received. See Table 1 and Table 2 for the relationship between the control bits and configuration of the TSC2003. DC/DC Converter Battery 0.5V + to 6.0V 2.7V VDD 0.125V to 1.5V VBAT A/D Converter 7.5kΩ 2.5kΩ Figure 9. Battery Measurement Functional Block Diagram 16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 TSC2003-Q1 www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008 Pressure Measurement Measuring touch pressure can also be done with the TSC2003. To determine pen or finger touch, the pressure of the "touch" needs to be determined. Generally, it is not necessary to have high accuracy for this test, therefore, the 8-bit resolution mode is recommended. However, calculations are shown with the 12-bit resolution mode. There are several different ways of performing this measurement, and the TSC2003 supports two methods. The first method requires knowing the X-Plate resistance, measurement of the X-Position, and two additional cross-panel measurements (Z2 and Z1) of the touch screen, as shown in Figure 10. Use Equation 2 to calculate the touch resistance: RTOUCH = RX-Plate • X-Position 4096 Z2 –1 Z1 (2) The second method requires knowing both the X-Plate and Y-Plate resistance, measurement of X-Position and Y-Position, and Z1. Equation 3 calculates the touch resistance using the second method: R TOUCH = R X −Plate • X-Position 4096 Y-Position 4096 –1 – R Y −Plate • 1– 4096 Z1 (3) Measure X-Position X+ Y+ Touch X-Position Y– X– Measure Z1-Position Y+ X+ Touch Z1-Position X– Y– Y+ X+ Touch Z2-Position X– Y– Measure Z2-Position Figure 10. Pressure Measurement Block Diagrams Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 17 TSC2003-Q1 SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com Digital Interface The TSC2003 supports the I2C serial bus and data transmission protocol in all three defined modes: standard, fast, and high-speed. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are slaves. The bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the Start and Stop conditions. The TSC2003 operates as a slave on the I2C bus. Connections to the bus are made via the open-drain I/O lines SDA and SDL. The following bus protocol has been defined, as shown in Figure 11: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are interpreted as control signals. SDA Slave Address R/W Direction Bit Acknowledgement Signal from Receiver Acknowledgement Signal from Receiver 1 SCL 2 6 7 8 9 1 ACK Start Condition 2 3-7 8 9 ACK Repeated If More Bytes Are Transferred Stop Condition or Repeated Start Condition Figure 11. I2C Bus Protocol Accordingly, the following bus conditions have been defined: Bus Not Busy: Both data and clock lines remain high. Start Data Transfer: A change in the state of the data line, from high to low, while the clock is high defines a Start condition. Stop Data Transfer: A change in the state of the data line, from low to high, while the clock line is high defines a Stop condition. Data Valid: The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of data bytes transferred between Start and Stop conditions is not limited, and is determined by the master device. The information is transferred byte-wise, and each receiver acknowledges with a ninth-bit. Within the I2C bus specifications, a standard mode (100-kHz clock rate), a fast mode (400-kHz clock rate), and a high-speed mode (3.4-MHz clock rate) are defined. The TSC2003 works in all three modes. Acknowledge: Each receiving device, when accessed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse, which is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the Stop condition. 18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 TSC2003-Q1 www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008 Figure 11 details how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two types of data transfer are possible: • Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after the slave address and each received byte. • Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next, a number of data bytes are transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last one. At the end of the last received byte, a ‘not acknowledge’ is returned. The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or a repeated Start condition. Because a repeated Start condition is also the beginning of the next serial transfer, the bus is not released. The TSC2003 may operate in the following two modes: • Slave receiver mode: Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. Start and Stop conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. • Slave transmitter mode: The first byte (the slave address) is received and handled as in the slave receiver mode. However, in this mode the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the TSC2003 while the serial clock is input on SCL. Start and Stop conditions are recognized as the beginning and end of a serial transfer. Address Byte The address byte, as shown in Figure 12, is the first byte received following the Start condition from the master device. The first five bits (MSBs) of the slave address are factory preset to 10010. The next two bits of the address byte are the device select bits: A1 and A0. Input pins (A1 and A0) on the TSC2003 determine these two bits of the device address for a particular TSC2003. Therefore, a maximum of four devices with the same preset code can be connected on the same bus at one time. LSB MSB 1 0 0 1 0 A1 A0 R/W Figure 12. Address Byte The A1–A0 address inputs can be connected to VDD or digital ground. The last bit of the address byte (R/W) defines the operation to be performed. When set to a "1", a read operation is selected; when set to a "0", a write operation is selected. Following the Start condition, the TSC2003 monitors the SDA bus and checks the device type identifier being transmitted. Upon receiving the 10010 code, the appropriate device select bits, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line. Command Byte The TSC2003 operating mode is determined by a command byte, which is shown in Figure 13. LSB MSB C3 C2 C1 C0 PD1 PD0 M X Figure 13. Command Byte The bits in the device command byte are defined as follows: • C3–C0: Configuration bits. These bits set the input multiplexer address and functions that the TSC2003 will perform, as shown in Table 1. • PD1–PD0: Power-down bits. These two bits select the power-down mode that the TSC2003 will enter after the current command completes, as shown in Table 2. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 19 TSC2003-Q1 SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com Table 1. Possible Input Configurations C3 C2 C1 C0 FUNCTION INPUT TO ADC X DRIVERS Y DRIVERS REFERENCE MODE 0 0 0 0 Measure TEMP0 TEMP0 Off Off Single ended 0 0 0 1 Measure VBAT1 VBAT1 Off Off Single ended 0 0 1 0 Measure IN1 IN1 Off Off Single ended 0 0 1 1 Reserved — — — Single ended 0 1 0 0 Measure TEMP1 TEMP1 Off Off Single ended 0 1 0 1 Measure VBAT2 VBAT2 Off Off Single ended 0 1 1 0 Measure IN2 IN2 Off Off Single ended 0 1 1 1 Reserved — — — Single ended 1 0 0 0 Activate X– Drivers — On Off Differential 1 0 0 1 Activate Y– Drivers — Off On Differential 1 0 1 0 Activate Y+, X– Drivers — X– On Y+ On Differential 1 0 1 1 Reserved — — — Differential 1 1 0 0 Measure X Position Y+ On Off Differential 1 1 0 1 Measure Y Position X+ Off On Differential 1 1 1 0 Measure Z1 Position X+ X– On Y+ On Differential 1 1 1 1 Measure Z2 Position Y– X– On Y+ On Differential Table 2. Power-Down Bit Functions PD1 PD0 PENIRQ 0 0 Enabled Power-down between conversions DESCRIPTION 0 1 Disabled Internal reference off, ADC on 1 0 Enabled Internal reference on, ADC off 1 1 Disabled Internal reference on, ADC on The internal reference voltage can be turned on or off independently of the ADC. This can allow extra time for the internal reference voltage to settle to its final value prior to making a conversion. Allow this extra wakeup time if the internal reference was powered down. Also note that the status of the internal reference power down is latched into the part (internally) when a Stop or repeated Start occurs at the end of a command byte (see Figure 14 and Figure 16). Therefore, to turn off the internal reference, an additional write to the TSC2003 with PD1 = 0, is required after the channel has been converted. It is recommended to set PD0 = 0 in each command byte to get the lowest power consumption possible. If multiple X-, Y-, and Z-position measurements are done one right after another, such as when averaging, PD0 = 1 leaves the touch screen drivers on at the end of each conversion cycle. • M: Mode bit. If M is 0, the TSC2003 is in 12-bit mode. If M is 1, 8-bit mode is selected. • X: Don’t care When the TSC2003 powers up, the power-down mode bits need to be written to ensure that the part is placed into the desired mode to achieve lowest power. Therefore, immediately after power-up, a command byte should be sent which sets PD1 = PD0 = 0, so that the device is in the lowest power mode, powering down between conversions. Start Conversion/Write Cycle A conversion/write cycle begins when the master issues the address byte containing the slave address of the TSC2003, with the eighth bit equal to a 0 (R/W = 0), as shown in Figure 12. Once the eighth bit has been received, and the address matches the A1–A0 address input pin setting, the TSC2003 issues an acknowledge. Once the master receives the acknowledge bit from the TSC2003, the master writes the command byte to the slave (see Figure 13). After the command byte is received by the slave, the slave issues another acknowledge bit. The master then ends the write cycle by issuing a repeated Start or a Stop condition, as shown in Figure 14. 20 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 TSC2003-Q1 www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008 If the master sends additional command bytes after the initial byte, before sending a Stop or repeated Start condition, the TSC2003 does not acknowledge those bytes. The input multiplexer for the ADC has its channel selected when bits C3 through C0 are clocked in. If the selected channel is an X-,Y-, or Z-position measurement, the appropriate drivers turn on once the acquisition period begins. When R/W = 0, the input sample acquisition period starts on the falling edge of SCL once the C0 bit of the command byte has been latched, and ends when a Stop or repeated Start condition has been issued. A/D conversion starts immediately after the acquisition period. The multiplexer inputs to the ADC are disabled once the conversion period starts. However, if an X-, Y-, or Z-position is being measured, the respective touch screen drivers remain on during the conversion period. A complete write cycle is shown in Figure 14. SCL Address Byte 1 SDA 0 0 1 Command Byte A1 0 A0 R/W 0 0 C3 C2 C1 C0 PD1 PD0 TSC2003 ACK M 0 X TSC2003 ACK Acquisition Start Conversion Stop or Repeated Start Figure 14. Complete I2C Serial Write Transmission Read a Conversion/Read Cycle For best performance, the I2C bus should remain in an idle state while an A/D conversion is taking place. This prevents digital clock noise from affecting the bit decisions being made by the TSC2003. The master should wait for at least 10 µs before attempting to read data from the TSC2003 to realize this best performance. However, the master does not need to wait for a completed conversion before beginning a read from the slave, if full 12-bit performance is not necessary. Data access begins with the master issuing a Start condition followed by the address byte (see Figure 12) with R/W = 1. Once the eighth bit has been received, and the address matches, the slave issues an acknowledge. The first byte of serial data follows (D11 to D4, MSB first). After the first byte has been sent by the slave, it releases the SDA line for the master to issue an acknowledge. The slave responds with the second byte of serial data upon receiving the acknowledge from the master (D3-D0, followed by four 0 bits). The second byte is followed by a NOT acknowledge bit (ACK = 1) from the master to indicate that the last data byte has been received. If the master acknowledges the second data byte, then the data repeats on subsequent reads with ACKs between bytes. This is true in both 12-bit and 8-bit mode. The master then issues a Stop condition, which ends the read cycle, as shown in Figure 15. SCL Address Byte SDA Start 1 0 0 1 0 Date Byte 2 Date Byte 1 A1 A0 R/W 1 0 D11 D10 TSC2003 ACK D9 D8 D7 D6 D5 D4 0 D3 D2 D1 D0 0 0 0 0 1 Master NACK Master ACK Stop or Repeated Start Figure 15. Complete I2C Serial Read Transmission Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 21 TSC2003-Q1 SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com I2C High-Speed Operation The TSC2003 can operate with high-speed I2C masters. To do so, the simple resistor pullup on SCL must be changed to the active pullup, as recommended in the I2C specification. The I2C bus operates in standard or fast mode initially. Following a Start condition, the master sends the code 00001xxx, which the slave does not acknowledge. The bus now operates in high-speed mode and remains in high-speed mode until a Stop condition occurs. Therefore, to maximize throughput, only repeated Starts should be used to separate transactions. Because the TSC2003 may not have completed a conversion before a read to the part can be requested, the TSC2003 is capable of stretching the clock until the converted data is stored in its internal shift register. Once the data is latched, the TSC2003 releases the clock line so that the master can receive the converted data. A complete high-speed conversion cycle is shown in Figure 16. HS-Mode Enabled F/S Mode S 0 0 0 Sr 1 0 0 0 X 1 X X N A/D Converter Powers Up and Begins Sampling A/D Converter Power-Down Mode 1 A1 0 A0 W C3 A C2 C1 C0 PD1 PD0 M X A Programmable Fixed Address Part A/D Converter Stops Sampling and Begins Conversion Using Internal Clock Sr 1 0 0 1 A1 0 A0 R SCLH is stretched LOW until A/D Converter is finished converting data. A A/D Converter Goes Into Power-Down Mode After Finishing Conversion (If PD0 = 0) D11 D10 D9 D8 D7 D5 D6 D4 A Exit HS-Mode and Enter F/S Mode D1 D2 D3 D0 0 0 0 0 N P 16 Bits + Ack S = Start Sr = Repeated Start P = Stop = Master Controls Bus = Slave Controls Bus Figure 16. High-Speed I2C Mode Conversion Cycle Data Format The TSC2003 output data is in straight binary format, as shown in Figure 17. This shows the ideal output code for the given input voltage, and does not include the effects of offset, gain, or noise. FS = Full-Scale Voltage = V REF(1) 1LSB = V REF(1)/4096 1LSB 11...111 Output Code 11...110 11...101 00...010 00...001 00...000 FS – 1LSB 0V Input Voltage (2) (V) NOTES: (1) Reference voltage at converter: +REF – (–REF). See Figure 2. (2) Input voltage at converter, after multiplexer: +IN – (–IN). See Figure 2 Figure 17. Ideal Input Voltages and Output Codes 22 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 TSC2003-Q1 www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008 8-Bit Conversion The TSC2003 provides an 8-bit conversion mode (M = 1) that can be used when faster throughput is needed, and the digital result is not as critical (for example, measuring pressure). By switching to the 8-bit mode, a conversion result can be read by transferring only one data byte. This shortens each conversion by four bits and reduces data transfer time which results in fewer clock cycles and provides lower power consumption. Layout The following layout suggestions should provide optimum performance from the TSC2003. However, many portable applications have conflicting requirements concerning power, cost, size, and weight. In general, most portable devices have fairly "clean" power and grounds because most of the internal components are very low power. This situation would mean less bypassing for the converter's power, and less concern regarding grounding. Still, each situation is unique, and the following suggestions should be reviewed carefully. For optimum performance, care should be taken with the physical layout of the TSC2003 circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Therefore, during any single conversion for an n-bit SAR converter, there are n "windows" in which large external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and high-power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. The error can change if the external event changes in time with respect to the SCL input. With this in mind, power to the TSC2003 should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1-µF to 10-µF capacitor may also be needed if the impedance of the connection between VDD and the power supply is high. A bypass capacitor is generally not needed on the VREF pin because the internal reference is buffered by an internal op amp. If an external reference voltage originates from an operational amplifier, ensure that it can drive any bypass capacitor that is used without oscillation. The TSC2003 architecture offers no inherent rejection of noise or voltage variation in regards to using an external reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply appears directly in the digital results. While high-frequency noise can be filtered out, voltage variation due to line frequency (50 Hz or 60 Hz) can be difficult to remove. The GND pin should be connected to a clean ground point. In many cases, this is the "analog" ground. Avoid connections which are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply entry point. The ideal layout includes an analog ground plane dedicated to the converter and associated analog circuitry. In the specific case of use with a resistive touch screen, care should be taken with the connection between the converter and the touch screen. Because resistive touch screens have fairly low resistance, the interconnection should be as short and robust as possible. Longer connections can be a source of error, much like the on-resistance of the internal switches. Likewise, loose connections can be a source of error when the contact resistance changes with flexing or vibrations. As indicated previously, noise can be a major source of error in touch screen applications (e.g., applications that require a backlit LCD panel). This EMI noise can be coupled through the LCD panel to the touch screen and cause "flickering" of the converted data. Several things can be done to reduce this error, such as utilizing a touch screen with a bottom-side metal layer connected to ground. This couples the majority of noise to ground. Additionally, filtering capacitors from Y+, Y–, X+, and X– to ground can also help. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 23 TSC2003-Q1 SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com PENIRQ Output The pen-interrupt output function is shown in Figure 18. By connecting a pullup resistor to VDD (typically 100 kΩ), the PENIRQ output is high. While in the power-down mode, with PD0 = 0, the Y– driver is on and connected to GND, and the PENIRQ output is connected to the X+ input. When the panel is touched, the X+ input is pulled to ground through the touch screen, and PENIRQ output goes low due to the current path through the panel to GND, initiating an interrupt to the processor. During the measurement cycle for X, Y, and Z positions, the X+ input is disconnected from the PENIRQ pulldown transistor to eliminate any leakage current from the pullup resistor to flow through the touch screen, thus causing no errors. VDD 30kΩ to 100kΩ VDD PENIRQ VDD 10kΩ TEMP0 TEMP1 Y+ HIGH except when TEMP0, TEMP1 activated TEMP DIODE X+ Y– ON Y+ or X+ drivers on, or TEMP0, TEMP1 measurements activated Figure 18. PENIRQ Functional Block Diagram In addition to the measurement cycles for X-, Y-, and Z-position, commands which activate the X-drivers, Y-drivers, Y+ and X-drivers without performing a measurement also disconnect the X+ input from the PENIRQ pulldown transistor and disable the pen-interrupt output function regardless of the value of the PD0 bit. Under these conditions, the PENIRQ output is forced low. Furthermore, if the last command byte written to the TSC2003 contains PD0 = 1, the pen-interrupt output function is disabled and is not able to detect when the panel is touched. To re-enable the pen-interrupt output function under these circumstances, a command byte needs to be written to the TSC2003 with PD0 = 0. Once the bus master sends the address byte with R/W = 0 (see Figure 12) and the TSC2003 sends an acknowledge, the pen-interrupt function is disabled. If the command that follows the address byte has PD0 = 0, then the pen-interrupt function is enabled at the end of a conversion. This is approximately 10 µs (12-bit mode) or 7 µs (8-bit mode) after the TSC2003 receives a Stop/Start condition following the reception of a command byte (see Figure 14 and Figure 16 for further details of when the conversion cycle begins). In both cases listed above, it is recommended that the master processor mask the interrupt which the PENIRQ is associated with whenever the host writes to the TSC2003. This prevents false triggering of interrupts when the PENIRQ line is disabled in the cases listed above. 24 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TSC2003-Q1 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TSC2003IPWRQ1 ACTIVE TSSOP PW Pins Package Eco Plan (2) Qty 16 2500 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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